DE10110150A1 - Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray - Google Patents

Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray

Info

Publication number
DE10110150A1
DE10110150A1 DE10110150A DE10110150A DE10110150A1 DE 10110150 A1 DE10110150 A1 DE 10110150A1 DE 10110150 A DE10110150 A DE 10110150A DE 10110150 A DE10110150 A DE 10110150A DE 10110150 A1 DE10110150 A1 DE 10110150A1
Authority
DE
Germany
Prior art keywords
layer
memory cell
gate
cell array
bit lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10110150A
Other languages
German (de)
English (en)
Inventor
Josef Willer
Ronald Kakoschke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10110150A priority Critical patent/DE10110150A1/de
Priority to US09/917,867 priority patent/US6686242B2/en
Priority to KR1020037011519A priority patent/KR100608407B1/ko
Priority to JP2002578576A priority patent/JP2004530296A/ja
Priority to EP02757712A priority patent/EP1364409A2/de
Priority to PCT/EP2002/001508 priority patent/WO2002080275A2/de
Priority to AU2002338242A priority patent/AU2002338242A1/en
Priority to CNB028058798A priority patent/CN100336227C/zh
Priority to TW091103791A priority patent/TW540141B/zh
Publication of DE10110150A1 publication Critical patent/DE10110150A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE10110150A 2001-03-02 2001-03-02 Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray Withdrawn DE10110150A1 (de)

Priority Applications (9)

Application Number Priority Date Filing Date Title
DE10110150A DE10110150A1 (de) 2001-03-02 2001-03-02 Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray
US09/917,867 US6686242B2 (en) 2001-03-02 2001-07-26 Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array
KR1020037011519A KR100608407B1 (ko) 2001-03-02 2002-02-13 비트 라인 생성 방법 및 메모리 셀 어레이 생성 방법 및메모리 셀 어레이
JP2002578576A JP2004530296A (ja) 2001-03-02 2002-02-13 メモリセルアレイの金属性ビット線の製造方法、メモリセルアレイの製造方法、およびメモリセルアレイ
EP02757712A EP1364409A2 (de) 2001-03-02 2002-02-13 Verfahren zum herstellen von metallischen bitleitungen für speicherzellenarrays, verfahren zum herstellen von speicherzellenarrays und speicherzellenarray
PCT/EP2002/001508 WO2002080275A2 (de) 2001-03-02 2002-02-13 Speicherzellenarrays und deren herstellungssverfahren
AU2002338242A AU2002338242A1 (en) 2001-03-02 2002-02-13 Memory cell arrays and method for the production thereof
CNB028058798A CN100336227C (zh) 2001-03-02 2002-02-13 存储单元阵列位线的制法、存储单元阵列及其制造方法
TW091103791A TW540141B (en) 2001-03-02 2002-03-01 Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10110150A DE10110150A1 (de) 2001-03-02 2001-03-02 Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray

Publications (1)

Publication Number Publication Date
DE10110150A1 true DE10110150A1 (de) 2002-09-19

Family

ID=7676114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10110150A Withdrawn DE10110150A1 (de) 2001-03-02 2001-03-02 Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray

Country Status (9)

Country Link
US (1) US6686242B2 (enExample)
EP (1) EP1364409A2 (enExample)
JP (1) JP2004530296A (enExample)
KR (1) KR100608407B1 (enExample)
CN (1) CN100336227C (enExample)
AU (1) AU2002338242A1 (enExample)
DE (1) DE10110150A1 (enExample)
TW (1) TW540141B (enExample)
WO (1) WO2002080275A2 (enExample)

Cited By (12)

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WO2003030253A3 (en) * 2001-10-01 2003-08-28 Advanced Micro Devices Inc Salicided gate for virtual ground arrays
DE102005038939A1 (de) * 2005-08-17 2007-03-01 Infineon Technologies Ag Halbleiterspeicherbauelement und Herstellungsverfahren
DE102005048197B3 (de) * 2005-09-30 2007-04-26 Infineon Technologies Ag Halbleiterspeicherbauelement mit vergrabenen Bitleitungen und selbstjustierenden Bitleitungskontakten und dessen Herstellungsverfahren
WO2007047265A1 (en) * 2005-10-21 2007-04-26 Spansion Llc Bit line implant
US7285499B1 (en) 2005-05-12 2007-10-23 Advanced Micro Devices, Inc. Polymer spacers for creating sub-lithographic spaces
DE102006032958A1 (de) * 2006-06-30 2008-01-17 Qimonda Ag Vergrabene Bitleitung mit reduziertem Widerstand
DE10392392B4 (de) * 2002-03-14 2008-02-21 Spansion LLC (n.d.Ges.d. Staates Delaware), Sunnyvale Verfahren zur Herstellung einer integrierten Schaltung mit nichtflüchtigem Speicherbauelement ohne Bitleitungskurzschlüsse
US7341956B1 (en) 2005-04-07 2008-03-11 Spansion Llc Disposable hard mask for forming bit lines
US7368350B2 (en) 2005-12-20 2008-05-06 Infineon Technologies Ag Memory cell arrays and methods for producing memory cell arrays
DE10326771B4 (de) * 2002-06-14 2010-08-19 Qimonda Flash Gmbh Integrierte Speicherschaltung und Verfahren zum Bilden einer integrierten Speicherschaltung
DE112006000208B4 (de) * 2005-01-12 2014-04-03 Spansion Llc Speicherbauelement mit trapezförmigen Bitleitungen und Verfahren zur Herstellung desselben, und Array von Speicherelementen
DE102006048392B4 (de) * 2006-09-29 2014-05-22 Qimonda Ag Verfahren zur Herstellung eines Halbleiterspeicherbauelementes

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US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6700818B2 (en) * 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US20030181053A1 (en) * 2002-03-20 2003-09-25 U-Way Tseng Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof
TWI291748B (en) * 2002-03-20 2007-12-21 Macronix Int Co Ltd Method and structure for improving reliability of non-volatile memory cell
US8080453B1 (en) 2002-06-28 2011-12-20 Cypress Semiconductor Corporation Gate stack having nitride layer
US7256083B1 (en) * 2002-06-28 2007-08-14 Cypress Semiconductor Corporation Nitride layer on a gate stack
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
KR100452037B1 (ko) * 2002-07-18 2004-10-08 주식회사 하이닉스반도체 반도체 소자의 제조방법 및 그 소자
DE10239491A1 (de) * 2002-08-28 2004-03-18 Infineon Technologies Ag Verfahren zur Herstellung vergrabener Bitleitungen in einem Halbleiterspeicher
US6773988B1 (en) * 2002-09-13 2004-08-10 Advanced Micro Devices, Inc. Memory wordline spacer
US6815274B1 (en) * 2002-09-13 2004-11-09 Taiwan Semiconductor Manufacturing Co. Resist protect oxide structure of sub-micron salicide process
US7049188B2 (en) * 2002-11-26 2006-05-23 Advanced Micro Devices, Inc. Lateral doped channel
DE10258194B4 (de) * 2002-12-12 2005-11-03 Infineon Technologies Ag Halbleiterspeicher mit Charge-trapping-Speicherzellen und Herstellungsverfahren
DE10258420B4 (de) * 2002-12-13 2007-03-01 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterspeichereinrichtung mit Charge-trapping-Speicherzellen und vergrabenen Bitleitungen
DE10259783A1 (de) * 2002-12-19 2004-07-15 Infineon Technologies Ag Verfahren zur Verbesserung der Prozessschrittfolge bei der Herstellung von Halbleiterspeichern
US7178004B2 (en) * 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
DE10324052B4 (de) * 2003-05-27 2007-06-28 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterspeichers mit Charge-Trapping-Speicherzellen
JP4818578B2 (ja) * 2003-08-06 2011-11-16 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置およびその製造方法
US7123532B2 (en) * 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7371637B2 (en) * 2003-09-26 2008-05-13 Cypress Semiconductor Corporation Oxide-nitride stack gate dielectric
US7041545B2 (en) * 2004-03-08 2006-05-09 Infineon Technologies Ag Method for producing semiconductor memory devices and integrated memory device
US6989320B2 (en) * 2004-05-11 2006-01-24 Advanced Micro Devices, Inc. Bitline implant utilizing dual poly
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060084219A1 (en) * 2004-10-14 2006-04-20 Saifun Semiconductors, Ltd. Advanced NROM structure and method of fabrication
US7638850B2 (en) * 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US20060146624A1 (en) * 2004-12-02 2006-07-06 Saifun Semiconductors, Ltd. Current folding sense amplifier
CN1838328A (zh) * 2005-01-19 2006-09-27 赛芬半导体有限公司 擦除存储器阵列上存储单元的方法
US7186607B2 (en) * 2005-02-18 2007-03-06 Infineon Technologies Ag Charge-trapping memory device and method for production
JP4275086B2 (ja) * 2005-02-22 2009-06-10 Necエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
US7405441B2 (en) * 2005-03-11 2008-07-29 Infineon Technology Ag Semiconductor memory
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
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US7208373B2 (en) * 2005-05-27 2007-04-24 Infineon Technologies Ag Method of forming a memory cell array and a memory cell array
US20060281255A1 (en) * 2005-06-14 2006-12-14 Chun-Jen Chiu Method for forming a sealed storage non-volative multiple-bit memory cell
EP1746645A3 (en) * 2005-07-18 2009-01-21 Saifun Semiconductors Ltd. Memory array with sub-minimum feature size word line spacing and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US20070096199A1 (en) * 2005-09-08 2007-05-03 Eli Lusky Method of manufacturing symmetric arrays
US20080025084A1 (en) * 2005-09-08 2008-01-31 Rustom Irani High aspect ration bitline oxides
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US20070082446A1 (en) * 2005-10-07 2007-04-12 Dominik Olligs Methods for fabricating non-volatile memory cell array
US20070120180A1 (en) * 2005-11-25 2007-05-31 Boaz Eitan Transition areas for dense memory arrays
US7538384B2 (en) * 2005-12-05 2009-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory array structure
US7352627B2 (en) * 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) * 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US20070173017A1 (en) * 2006-01-20 2007-07-26 Saifun Semiconductors, Ltd. Advanced non-volatile memory array and method of fabrication thereof
US7692961B2 (en) * 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) * 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7760554B2 (en) * 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7811935B2 (en) * 2006-03-07 2010-10-12 Micron Technology, Inc. Isolation regions and their formation
US7408222B2 (en) * 2006-03-27 2008-08-05 Infineon Technologies Ag Charge trapping device and method of producing the charge trapping device
US7531867B2 (en) * 2006-03-27 2009-05-12 Infineon Technologies Ag Method for forming an integrated memory device and memory device
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7790516B2 (en) * 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells
US7608504B2 (en) * 2006-08-30 2009-10-27 Macronix International Co., Ltd. Memory and manufacturing method thereof
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US20080111182A1 (en) * 2006-11-02 2008-05-15 Rustom Irani Forming buried contact etch stop layer (CESL) in semiconductor devices self-aligned to diffusion
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US20080150011A1 (en) * 2006-12-21 2008-06-26 Spansion Llc Integrated circuit system with memory system
US8536640B2 (en) 2007-07-20 2013-09-17 Cypress Semiconductor Corporation Deuterated film encapsulation of nonvolatile charge trap memory device
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JP5390822B2 (ja) * 2008-10-02 2014-01-15 スパンション エルエルシー 半導体装置及び半導体装置の製造方法
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003030253A3 (en) * 2001-10-01 2003-08-28 Advanced Micro Devices Inc Salicided gate for virtual ground arrays
DE10392392B4 (de) * 2002-03-14 2008-02-21 Spansion LLC (n.d.Ges.d. Staates Delaware), Sunnyvale Verfahren zur Herstellung einer integrierten Schaltung mit nichtflüchtigem Speicherbauelement ohne Bitleitungskurzschlüsse
DE10326771B4 (de) * 2002-06-14 2010-08-19 Qimonda Flash Gmbh Integrierte Speicherschaltung und Verfahren zum Bilden einer integrierten Speicherschaltung
DE112006000208B4 (de) * 2005-01-12 2014-04-03 Spansion Llc Speicherbauelement mit trapezförmigen Bitleitungen und Verfahren zur Herstellung desselben, und Array von Speicherelementen
US7341956B1 (en) 2005-04-07 2008-03-11 Spansion Llc Disposable hard mask for forming bit lines
US7285499B1 (en) 2005-05-12 2007-10-23 Advanced Micro Devices, Inc. Polymer spacers for creating sub-lithographic spaces
DE102005038939A1 (de) * 2005-08-17 2007-03-01 Infineon Technologies Ag Halbleiterspeicherbauelement und Herstellungsverfahren
DE102005038939B4 (de) * 2005-08-17 2015-01-08 Qimonda Ag Halbleiterspeicherbauelement mit oberseitig selbstjustiert angeordneten Wortleitungen und Verfahren zur Herstellung von Halbleiterspeicherbauelementen
DE102005048197B3 (de) * 2005-09-30 2007-04-26 Infineon Technologies Ag Halbleiterspeicherbauelement mit vergrabenen Bitleitungen und selbstjustierenden Bitleitungskontakten und dessen Herstellungsverfahren
US7642158B2 (en) 2005-09-30 2010-01-05 Infineon Technologies Ag Semiconductor memory device and method of production
WO2007047265A1 (en) * 2005-10-21 2007-04-26 Spansion Llc Bit line implant
US7432178B2 (en) 2005-10-21 2008-10-07 Advanced Micro Devices, Inc. Bit line implant
US7368350B2 (en) 2005-12-20 2008-05-06 Infineon Technologies Ag Memory cell arrays and methods for producing memory cell arrays
DE102006032958B4 (de) * 2006-06-30 2013-04-11 Qimonda Ag Speicherzellenarray mit vergrabener Bitleitung mit reduziertem Widerstand und Herstellungsverfahren hierfür
DE102006032958A1 (de) * 2006-06-30 2008-01-17 Qimonda Ag Vergrabene Bitleitung mit reduziertem Widerstand
DE102006048392B4 (de) * 2006-09-29 2014-05-22 Qimonda Ag Verfahren zur Herstellung eines Halbleiterspeicherbauelementes

Also Published As

Publication number Publication date
JP2004530296A (ja) 2004-09-30
US20020132430A1 (en) 2002-09-19
WO2002080275A3 (de) 2003-01-30
AU2002338242A1 (en) 2002-10-15
KR100608407B1 (ko) 2006-08-03
CN1502134A (zh) 2004-06-02
US6686242B2 (en) 2004-02-03
TW540141B (en) 2003-07-01
KR20030088444A (ko) 2003-11-19
EP1364409A2 (de) 2003-11-26
CN100336227C (zh) 2007-09-05
WO2002080275A2 (de) 2002-10-10

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