TW463331B - Self-aligned drain contact PMOS flash memory and process for making same - Google Patents

Abstract

A process and structure reduces the amount of dielectric, such as silicon dioxide, needed to separate polysilicon gates from drain contacts, thereby reducing the size of the individual memory cells and increasing the density of the associated memory array. Silicon nitride is formed on top and on the sides of the polysilicon gates prior to source and drain formation and self-aligned drain contact masking and etching. The presence of the silicon nitride spacers prevents the subsequent oxide etch, which forms the openings to the drain regions for the conducting drain contact, from removing polysilicon in the event of mask misalignment. Therefore, additional oxide, which was necessary to protect the polysilicon gates during the formation of the drain contact window when mask misalignment occurs, is no longer needed between the polysilicon gates and the drain contacts, resulting in higher density memory arrays.

Description

4 6 3 331 Five 'Invention Description (1) ft Field of Invention, — ▲ 丨. _. The present invention relates to a method for generating and connecting regions in a semiconductor device, more specifically, it is used for The drain region is connected to the P-channel flash memory unit to reduce the size of the memory array device. Related Articles A flash memory array contains an array of flash memory cells. The P-channel flash of the prior art used in this array can eliminate processable read-only memory (EPROM) cells 100 shown in Figures 1-3. In the figure, the top view of the memory cell 100 shows a drain contact π 0, a P + drain region 丨 2 〇, a floating gate 130 control gate 1 4 0 ′% oxide region 1 5 〇 a and 15 0 b, and P + source region and 160b, the middle source region 160a is the source of the memory cell 10G and the source region 160b is a 16-ton extension of the source region to connect adjacent Source region of the memory cell. FIG. 2 is a cross-sectional view of the memory cell 100 taken along line AA in FIG. A source of P + drain, 20 is formed in an N # 2 00 and a channel is formed between the two. The floating gate 130 is separated from the channel insulation by a tunnel oxide 21O. It should be noted here that the term tunnel oxide originally meant " gate oxide, only because in such memory devices, that is, flash memory cells, the oxide under the gate must allow electrons to tunnel The effect causes electrons to shuttle back and forth between the floating gate and the silicon substrate. The use of the term "tunnel oxide" is used to reflect the dual function of this kind of gate oxide (ie, insulation and electron tunneling effects ...). Above the floating gate 130, an inner polycrystalline dielectric material 22 provides insulation from the control gate 140. One doped oxide 2 3 〇 such as borophosphosilicate glass two

C: \ Program Files \ Patent \ 54734. Ptd Page 5 463331 V. Description of Invention (2) (BPSG) or other appropriate substance to insulate it from the underlying layer. The drain contact 110 includes a titanium argon (TlN) layer 2 40 and a titanium metal (T 1) layer 250 located between the electrode 120 and the tungsten plug 2 60. FIG. 3 is a cross-sectional view of the memory cell 100 along the center line B_B, which shows the field oxide 150 and the tunnel oxide 21〇, and the polycrystalline dielectric within the floating gate 130 ′. Substance 2 2 0 is separated from control gate 1 4 0. " In the design of flash memory arrays, one of the main goals is to increase the degree of chaos. Therefore, for a certain number of memory cells, reduce the size of the array. A typical way to increase the density of an array is to reduce the size of the memory that makes up the individual cells by 1000. One of the areas where it is difficult to reduce the area of the cell is at the pole contact 11. The area between floating gate 30 and control gate 140. See Figures 1 and 2 for 7F. The reason why it is difficult to reduce is because the gates 300 and 140 must be protected from being etched out during the formation of the pole contacts 110. In the formation of the drain contact Y 0, a photomask shaping operation first defines a contact area above the drain 1 2 0. The unprotected oxide layer 230 is then etched away to expose the desired drain, the contact area is exposed, and then a tungsten plug 2 60 is formed in this area. A barrier layer of titanium metal 25 0 and titanium nitride 24 0 are separated to create a drain contact 11 1. If the alignment operation is misaligned such that the control gates 4 and / or floating gates 1 30 are not protected, the subsequent etching of the oxide layer 23 0 will remove parts of these gates, thereby damaging the cell 1 0. 〇. As a result, the 'drain region'; 20 and the halide region 23 which separates the drain contact 11 and the gates 13 and 4 must be larger than ideal to ensure that if a type misalignment occurs, During the formation of the drain contact 〇, the gates 130 and 140 are not etched away. Therefore, the flash memory cell we want has a reduced oxide separation distance between its drain contact and floating and & brake, resulting in a smaller memory

C: \ Pr〇gram Files \ Patent \ 54734. Ptd p. 6 Line aligned with the interlayer oxide Shi Xi layer and nitrogen etched along. Dielectric deposited on the etch. Extraction 1 belongs to the polysilicon gate. The crystalline silicon is etched and the drain electrode is connected to this result. The size is increased to make it more 463331. V. Description of the invention (3) Recall the body cell and therefore a higher ^ A degree memory Body cell. According to the present invention, there is provided a reduction in flow at the pole contact, and. , * 11 recalls the separation distance formed in the somatic cell. In the present invention, the inner electrode contact and the floating and control gate compound layer are formed on the stacked polycrystalline silicon :, in the example, '-dioxide is formed on the side of the stacked gate structure to form oxygen :: on the control gate, then the nitride spacer, and the stack Gate junctions and nitride spacers such as BPSG or BPTEOS will return to the front and the top and source regions. The contact mask will be between the nitrides: the two are used to mask the mask and the dielectric material is etched away. :: The drain portion exposes these areas and is shaped like: = pole contact area. The nitride spacers around Crane Gold do not require additional oxides between the two oxide points to protect more: silicon; two The drain contact can be closer to the poly-silicon gate, so the density of the memory array is increased. The reduction of the cell's 2 is described in the following details and it will be clearly understood by the person. A conventional PMOS flash memory cell is viewed from the top; FIG. 2 is a cross-sectional view of the memory cell along the line in FIG. 1, and FIG. 3 is a cross-sectional view of the memory cell along the line β_B ′ in FIG. 1. ◦It is self-aligning non-polar contact according to the present invention.

C: \ ProgramFiles \ Patent \ 54734.ptd Page 7 463331 V. Description of the invention (4) A cross-sectional view of the EPROM process; Figure Π is a top view of a PMOS flash memory cell according to the present invention; Figure 1 2 is a memory in 囷 Π Sectional view of body cell along line segment cc; Figure 13 is a sectional view of memory cell along line segment D_D in Figure 11; Similar reference numerals are used in different figures to indicate similar or identical substances. DETAILED DESCRIPTION According to the present invention, a method and structure are provided to reduce the size of the flash memory cell by reducing the oxide separation distance between the drain contact and the polysilicon gate by using a nitride layer. Figures 4 to 10 are side views showing the flow formation of self-aligned drain contacts formed in EPROM cells according to an embodiment of the present invention. In "4", the traditional method first forms a thick and thick tunnel oxide layer on a silicon substrate or # 400. A first polycrystalline silicon layer (P 0 1 y 1) 4 2 0 to be used later to form a memory array floating gate is deposited on the tunnel oxide 4 J 0. Then, an inner polycrystalline dielectric substance layer 43 is formed on poll 420. For example, the dielectric material layer 4 3 0 may be an oxide_nitride_oxide (0N0) layer to form or deposit a silicon dioxide layer on poiyi 420, and then deposit a silicon nitride or other suitable insulation The nitride layer then generates or deposits another silicon dioxide layer. A second polycrystalline silicon layer (p0y2) 44 or a polycrystalline layer is then deposited on top of the dielectric substance layer 430, where p2ly2 44o finally forms a control gate for the memory array. Another silicon dioxide layer 45 is formed on Poly2 4 40, and then a silicon nitride layer (Nitridel) 46 is formed on silicon dioxide layer 450. Silicon dioxide became the filling material between p〇 丨 y2 44〇 and htri del 460. The preferred thickness and range of these layers are listed below.

C; \ Program F ies \ Patent \ 54734. Ptd page 8 463331 5. Description of the invention (5) is shown in Table 1 below. Using conventional stacked gate sizing and etching techniques to etch layers 4 丨 0 to 4 6 0, a stacked gate structure 500 can be formed as shown in FIG. 5. In FIG. 6, a layer of dioxide (not shown here) is first A thermal growth method is formed on the side wall β of the polycrystalline silicon of the stacked gate structure, and then another layer of silicon dioxide 6 is deposited on the surface of the structure. Because the deposited fossil layer flattened the structure surface as shown in FIG. 5, a carpet-type money engraving, that is, oxide etching without a photomask, made the horizontal part of the flat dioxide layer more Thin areas are removed, but where the vertical portion of the flat silicon dioxide layer is thicker, oxide spacers 610 are formed on the vertical side walls of the stacked gate structure 500. The second layer of silicon nitride (Nitride2) 62 is then deposited as a conformal layer and is engraved isotropically, thus forming a nitride spacer 71 0 as shown in FIG. 7, which is subsequently etched at the drain contact. The edge of the stack is protected during this period. If desired, a conventional self-aligned source (SAS) etch (simplified and not shown here) can be performed here to reduce the size of the source region to be formed. According to FIG. 1, before the source / drain ion implantation, the field oxide 150 b is etched away and the silicon substrate under it is exposed. This is also where the source region dopants are implanted. The SAS etch aligns the floating gates 130 and the control gates 4o with the source doped regions', thus removing the field oxide regions 15b that separate the polysilicon gates 130 and 4o from the source regions. demand. The dopant can therefore be implanted in the next step to form source regions 800a and 8001}, as shown in FIG. As a result, we no longer need the source at 16 0 b because the source region 8 0 0 b can connect the source region to adjacent memory cells. Therefore, SAS remainder is a method that can be used in-flash epr〇m process period

c ^ Program Files \ Patent \ 54734. ptd 463331 V. Description of the invention (6) —- By etching away excess field oxide, the source region is reduced and the size of the entire cell is reduced. The self-alignment of the source region allows the polysilicon gate to be placed more tightly ^ 'so less actual occlusion is required between one memory cell and the next memory cell (that is, a tighter memory cell can be placed) . ’The manufacturing process continues regardless of whether SAS etching is performed or not. In FIG. 8, the source 8000 and the drain 810 both form a p + region. For example, the dopant is implanted by ion implantation to form the source and drain regions and then the element structure is annealed at 800 to 20 to 40. minute. A layer of TEOS (BPTEOS) 8 20 or other suitable dielectric material, such as BpSG, is deposited on the disc and smoothed under reflux at 15 0 to 20 minutes. Then chemical / mechanical polishing (CMP) is performed to make it flat and reduce the thickness of the bp% layer 820 to 3000 to 3500A '. Table 1 below lists the preferred thickness and range of each layer.

Layer Range I. -Preferred oxide 410 95-105 angstroms 1 100 angstroms polycrystalline silicon 1 420 1000-1500 angstroms 1200 angstroms dielectric substance 430 170-200 angstroms 180 angstroms polycrystalline sand 2 / Polycide 440 1500-2000 angstroms 1700 angstroms of sand 450 250-400 angstroms 300 angstroms oxide 1 460 2500-3000 angstroms 1 2700 angstroms measuring wall oxide growth 150-200 angstroms 200 angstroms oxide deposition 600-1000 angstroms 800¼ oxide 2 620 1000-1200 angstroms 1000 Angstroms BPSG (deposited) 820 7000-10000 Angstroms_. Angstrom BPSG (after CMP) 820 3000-3500 Angstrom 3200 Angstrom ------ --1 Table 1

463331 V. Description of the invention (7) Then define the non-polar contact area by pass, unify the shape, or write directly to ㈣. = As in FIG. 9, after the 'on-layer photoresist (not shown here) is deposited on the nano layer 820, the photoresist is then shaped to define the drain contact region 9o. -Self-aligned contact ㈣ or highly selective oxide degassing of BPSG in the gaseous selective area to form the drain contact area 91 °. After the titanium metal is deposited to form a layer 920 with a thickness of 400 A and the titanium nitride is deposited on the titanium metal layer 920 to form a thick layer with a thickness of 100 000 $, the titanium and titanium nitride layers are exposed to nitrogen at Annealed at 585 ° C for 20 minutes to form a barrier layer for depositing tungsten plugs. In FIG. 10, a tungsten metal layer having a thickness of 600 Å is deposited in a non-contact region in a known manner ', for example, using a chemical vapor deposition (CVD) method. After the CMP or another suitable etching method, the tungsten metal layer is planarized and placed in the tungsten plug 1 G 2 0 to self-align the drain contacts 丨 〇 丨 〇. 11 to 13 show anatomical diagrams of a stacked memory cell 500 formed in accordance with the present invention in different directions. FIG. 11 is a top view of a cell 500, showing a non-polar contact 1 01 0 'P + a drain 8 1 0' P + a source 8 0 0 a and 8 0 0 b, a field compound 11 0 0 1 floating gate 4 2 0, and control gate 44 0. 12 and 13 are side views shown in FIG. 11 along the line segments C-C 'and D + D', respectively. As shown in Figs. 11 and 12, the size of the soma cell 500 is compared with the memory cell 100 in Figs. 1 and 2 compared to the source and sum; and the polar regions have been reduced. The field oxide 150b between the source 160b and the polysilicon gate 130 and 140 shown in FIG. 1 was removed by using conventional SAS money to reduce the source region. In the present invention, the drain region is also reduced because the drain contacts can be made closer to the polysilicon gate, so the amount of oxide between the polysilicon gate and the poly contacts is greatly reduced. This scab produces smaller memory cells and causes

C: \ Program Files \ Patent \ 54734. Ptd Page 11 463331

V. Description of the invention (8) A denser memory array. The additional oxide required to prevent non-polar alignment can also prevent the formation of nitride spacers that may be formed by the possible misalignment, because it is removed during the polysilicon gate cycle. As a result, the number of spacers between the polysilicon gate and the oxide structure is reduced by 500 parts. The gate etch is performed to form each stack gate over the substrate 400, as shown in FIG. The stacking gate structure of the Tsai / Bendo 5⑽-shaped dot etching without retaining the original use, can now implement the drain connection to greatly reduce the continuous memory = «& also the spacing between 3 u u, as shown in Figure 9. Therefore, according to the present invention, a self-aligned drain contact process is used to obtain a smaller memory cell size and a higher density memory array. The above embodiments of the present invention are for illustration only and are not limited thereto. Various changes and modifications can be made to those skilled in the art without departing from the broader considerations of the present invention. Therefore, the scope of subsequent patent applications includes all changes and modifications within the spirit and scope of the present invention.

C: \ Program Files \ Patent \ 54734. Ptd page 12

Claims (1)

463331 6. Scope of patent application 1. A self-aligned drain contact processing process, including the following steps: forming a silicon nitride layer on a silicon substrate, a memory cell to be formed, and a stack gate portion of at least two sides; Carrying the nitride breakdown layer and forming nitride spacers around the stacked gate structure adjacent to the source and drain regions to be formed; forming the source and non-electrode regions of each stacked gate structure in the dream substrate Opposite two sides, and places; and forming a self-aligned and drain contact between a selected region of the nitride spacer in the silicon substrate. 2. For the processing flow of the first patent application, the memory unit is an erasable programmable ROM (EP ROM) unit. 3. For the processing flow of the first scope of the patent application, the memory unit is a flash EPROM unit. 4. For the processing flow of item 1 of the scope of patent application, the memory unit is a PM0S flash EPROM unit. 5. For example, the processing flow of the first patent application range, wherein the stack gate portion of the memory cell to be formed includes the following steps: forming a first oxide layer and forming a first polycrystal on the rare earth substrate; A layer is formed on the oxide layer; an inner polycrystalline dielectric material layer is formed on the first polycrystalline silicon layer; a second polycrystalline silicon layer is formed on the inner polycrystalline dielectric material layer; Forming a second oxide layer on the second polycrystalline silicon layer; forming a second nitride stone layer on the second oxide layer; and etching the second gasification layer, the first And a second oxide layer, the first C: \ Program Files \ Patent \ 54734, ptd Page 13 463331 Six 'application for patent scope and second poly 6. If the application is in the process of forming this gas, please click the step, please click the pass, please accumulate one by one, one by one The shape of the cover of the application is engraved by Shen Shencheng, the engraving is engraved, and the engraving is as thick as the layer is in the photo-etched shape, which is the shape of the shape. Ten faces were formed into a quasi-balloon layer and the inner polycrystalline dielectric substance layer. The processing flow of item 1 of the patent scope further includes the following steps. Before the silicon layer is converted, at least the opposite two dream dioxide layers of the stacked gate memory cell. The dioxin step includes the steps of generating and depositing silicon dioxide. The process of item 1 of the patent scope, wherein the step of forming a self-pair includes the following steps: depositing a dielectric substance after the source and drain regions are kicked; a specific portion of the dielectric substance to expose the drain contact region; A portion of the dielectric substance exposes the drain contact region; and a conductive plug is in the drain contact region. The processing flow of item 8 of the patent scope, wherein the plug is made of. The process of aligning drain contacts includes the following steps: a polycrystalline silicon layer on a silicon substrate and an oxide layer; a silicon dioxide layer on the polycrystalline silicon layer; a silicon nitride layer on the silicon dioxide layer Above; Nitriding> 5th, 2nd, 2nd, polycrystalline, and oxide layers to form; Brother —- emulsified hard layer in the memory structure> 2nd silicon dioxide layer to form An oxide spacer; a second silicon nitride layer on the second silicon dioxide layer; a second silicon nitride layer to form a nitride spacer, and C: \ Program Files \ Patent \ 54734. Ptd Page 14 4 63 33 1 6. Scope of patent application Form a selected portion of the silicon substrate with self-aligned drain region between the silicon nitride spacer. 11. A memory array comprising: a dream substrate; a plurality of alternate drain and source regions formed in the silicon substrate * with the defined channel regions located therebetween; a plurality of memory structures located in the channel region The memory structure has at least one polycrystalline silicon gate; a plurality of dielectric substance spacers are located on a sidewall of the memory structure; and a plurality of drain contacts are positioned in the drain region, and the dielectric substance spacers and the The gates in the memory structure are separated. 1 2. The memory array according to item 11 of the patent application scope, further comprising a silicon dioxide layer located on the side wall of the memory structure and the dielectric substance spacer 1 3. The memory according to item 11 of the patent application scope A body array, wherein the memory structure comprises: an oxide is located on the channel region;-a polycrystalline silicon floating gate is located on the oxide; an internal polycrystalline dielectric substance is located on the floating gate; a polycrystalline silicon A control gate is located on the inner polycrystalline dielectric substance; a silicon dioxide layer is positioned on the control gate; and a chemical emission layer is positioned on the stone dioxide layer. 14. The memory array according to item 11 of the application, wherein the memory C: \ Program Files \ Patent \ 54734. Ptd Page 15 4 6 3 331 6. Scope of Patent Application The Li array is an EPROM array. 1 5. The memory array according to item 11 of the application, wherein the memory array is a flash EPROM array. 16. The memory array according to item 11 of the patent application scope, wherein the memory array is a PMOS flash EPROM array. C: \ Program Files \ Patent \ 54734.ptd page 16