Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

• the present invention relates to methods of metallic bit lines for memory cell arrays, methods for producing memory cell arrays which have such metallic bit lines, and to memory cell arrays produced thereby.
• the present invention relates to methods and devices which are suitable for planar EEPROMs for so-called “stand-alone” applications and for so-called “embedded” applications.
• SONOS silicon-oxide-nitride-oxide-silicon
• bit lines designed as diffusion areas become increasingly high-resistance with decreasing structure size, since the diffusion depth must also be scaled in order to counteract the risk of a punch-through between adjacent bit lines.
• the problem here is that higher-impedance bit lines only allow smaller cell blocks, so that the degree of utilization decreases here and the advantage of the smaller memory cells, which are purchased as a result of greater process expenditure, disappears.
• the object of the present invention is to provide methods and devices which allow the implementation of very compact memory cells even in larger cell blocks.
• This task is accomplished through a method of manufacturing
• the present invention provides methods for fabricating bit lines for a memory cell array, comprising the following steps:
• the metallizations being insulated from the gate region layer by the insulating spacer layers.
• the inventive method for producing a memory cell array has the following steps:
• word lines which are substantially perpendicular to the bit lines and which are each connected to a plurality of gate regions, the gate regions being produced when the word lines are generated by appropriately structuring the remaining parts of the gate region layer.
• the metallic bit lines are produced by performing a Ti or co-silicide process on the exposed substrate regions which have previously been subjected to a source / drain implantation, which can also be referred to as a bit line implantation.
• a source / drain implantation which can also be referred to as a bit line implantation.
• the later gate structures are preferably provided with a hard mask, which preferably consists of nitride.
• the regions subjected to the source / drain implantation serve as the source / drain regions of the memory transistors, the siliconization of these regions serving as a metallic bit line.
• the gate areas or gate structures that In the method according to the invention, they are initially designed as strips running along the bit line. When the word lines are generated, they are etched, preferably by dry etching, in relation to them.
• peripheral transistors can also be produced in areas outside the memory cell array using the method according to the invention.
• both peripheral transistors with so-called
• Single work function gates in which all polycrystalline gate areas are of a doping type, and also with so-called dual work function gates, in which the doping type of the polycrystalline gate area is based on the channel type, i.e. H. is adapted to the doping type of the source-drain regions can be realized.
• a memory cell array according to the invention comprises the following features:
• Word lines which are arranged in a first direction with respect to the memory cell array and are electrically conductively connected to gate regions of the memory cells;
• Bit lines that run in a second direction substantially perpendicular to the first direction between the memory cells
• bit lines are formed by metallic structures generated directly on source / drain regions of the memory cells, and wherein isolation means are provided between the metallic structures of the bit lines and the gate regions of the memory cells.
• the present invention thus creates methods for producing memory cell arrays with metallic bit lines that are self-aligned to gate structures, and memory cell arrays with such bit lines. Furthermore, according to the invention, self-aligned gate structures are produced for metallic word lines.
• the present invention also enables advantageous integration in terms of process technology with regard to a parallelization of memory cell array and peripheral circuit structures.
• the present invention enables large cell blocks with minimal periphery and thus high cell efficiency by producing metallic or metallized bit lines and furthermore by producing metallic or metallized word lines.
• the bit lines can be made so narrow that a cell area of 4F 2 can be realized, where F indicates the line width possible with a lithography technique used, line widths of 140 n being achieved with current lithography technologies.
• the bit line level and the word line level can be used as a metallic wiring level.
• the method according to the invention can also be combined with both the single work function technology and the dual work function technology.
• 1 shows a plan view of a section of a memory cell array
• 2 shows a schematic cross-sectional view of a layer sequence in an initial stage of the method according to the invention
• FIG. 3 shows a schematic plan view of a substrate section with bit line recess regions
• 4a to 4c are schematic cross-sectional views for explaining a first exemplary embodiment of the method according to the invention for producing a memory cell array
• FIG. 5 shows a schematic cross-sectional view of an intermediate stage in the production of a peripheral transistor according to the first exemplary embodiment
• 6a and 6b are schematic cross-sectional views of an advanced manufacturing stage to illustrate the course of word and bit
• FIG. 7 is a schematic cross-sectional view of an advanced manufacturing stage with respect to a peripheral transistor according to the first embodiment
• FIGS. 6a and 6b are schematic cross-sectional views corresponding to FIGS. 6a and 6b for a second exemplary embodiment of a method according to the invention for producing a memory cell array;
• FIG. 9 shows a schematic cross-sectional view corresponding to FIG. 7 for the second exemplary embodiment
• 10a and 10b are schematic cross-sectional views for explaining the generation of metallic word lines in the second exemplary embodiment.
• FIG. 11 is a schematic cross-sectional view for illustrating a peripheral transistor produced according to the second exemplary embodiment.
• FIG. 1 schematically shows sections of two word lines 2 which run perpendicular to bit lines 4, so that the word lines 2 form a grid structure together with the bit lines 4.
• the dashed lines represent the metallic bit lines 4 according to the invention, while the solid lines 8 represent the source / drain implantation region on which the metallic bit lines are formed.
• respective memory cells 6 are arranged below the word lines 2 between the bit lines 4.
• the gate areas are located under the word lines, while the diffusion areas or source / drain implantations arranged under the bit lines define the source / drain areas of a respective cell.
• the metallic bit lines, and also the word lines are preferably formed using a siliconization.
• a siliconization Such methods are known as siliciding, in which a suitable metal, for example cobalt, titanium, alloys thereof, or also nickel or tungsten, is first applied to silicon, whereupon one Temperature treatment is carried out. The temperature treatment causes a chemical reaction between the applied metal and the silicon, whereby a silicide layer is generated on the silicon. This generation of a metallic silicide layer on silicon is referred to as siliciding.
• a so-called polycide method for generating the word lines of the memory cell array and for generating the gate Structures of the peripheral transistors used.
• Polycide processes are understood to mean those processes in which an entire polycrystalline silicon layer is first applied or deposited, whereupon a WSi layer is deposited as an alloy over the entire surface of the polycrystalline silicon layer. Subsequently, a hard mask, preferably made of nitride, is generally applied to the WSi layer. The hard mask is subsequently structured using phototechnical processes, whereupon the WSi layer and the underlying polycrystalline silicon are etched in order to produce the desired structures.
• tungsten nitride layer is first applied to a polycrystalline silicon layer and then a tungsten layer.
• the tungsten nitride layer acts as a diffusion barrier, so that no tungsten silicide, ie no alloy, is created, but rather a correspondingly low-resistance, pure metal structure.
• DJ C ⁇ ⁇ 0 ⁇ O ⁇ • ⁇ DJ d H ⁇ - ⁇ C ⁇ ⁇ ⁇ - rt ⁇ ⁇ ⁇ - ⁇ j ⁇ ⁇ d «N 1 H 00 er O ⁇ li - li ⁇ ? d DJ Hi ⁇ d ⁇ - s: C ⁇ DJ 0- H d iQ ⁇ - ⁇ - 0 d ⁇ Hl
• CMP chemical mechanical polishing
• the p- and n-wells for the later CMOS area in the periphery of the memory cell array and the wells for the memory cells are produced by masked boron and phosphorus implantation and subsequent healing , The scatter oxide is then removed.
• a polysilicon layer serving as a gate region layer is first deposited onto this structure, on which in turn a nitride layer is deposited.
• a schematic cross-sectional view of a section of the resulting layer sequence in the memory cell area is shown in FIG. 2.
• a transistor trough 12 is formed in a silicon substrate 10.
• the described ONO triple layer 20, which consists of lower oxide layer 14, nitride layer 16 and upper oxide layer 18, is formed on transistor well 12. Outside the memory cell area, this ONO triple layer is replaced by a gate oxide.
• a polycrystalline layer 22, for example with a thickness of 100 nm, is formed on the ONO triple layer 20.
• a photo technique is carried out in order to produce elongate recesses 26 in the nitride layer 24, which run along the bit lines to be produced later, as shown in FIG. 3. These recesses 26 further define strips 28 along the later bit lines, which contribute to the definition of the later gate structures.
• the lacquer used in the phototechnology is stripped, whereupon the polycrystalline one
• bit line recesses 30 are formed in the nitride layer 24 and the polycrystalline layer 22, is shown in FIG. 4a.
• strip-shaped gate regions 34 are produced in the same, which extend along the later bit lines.
• This implantation is optional. In the case of n-channel memory transistors, this is preferably a boron implantation with a concentration of, for example, 1 ⁇ 10 14 crrf 3 .
• the implantations 32 serve, on the one hand, to generate a hard pn junction with the bit line implantations or source-drain implantations, which are produced later. On the other hand, the generation of the doped regions 32 results in under-scattering under the gate edge and thus penetration under the channel, so that an increased punch strength can be achieved thereby.
• Such an implantation 32 is particularly advantageous when 2-bit memory cells such as they are described, for example, in the Boaz Eitan document described above, are to be realized.
• insulating spacer layers 36 are produced on the side surfaces of the strip-shaped polycrystalline regions 34 and the parts of the nitride layer 24 arranged thereon using known methods.
• Source / drain implantations are formed through the openings in the ONO three-layer structure 20, in the case of n-channel memory transistors preferably by implantation with arsenic, a doping concentration of 3 ⁇ 10 15 cm 3.
• the source / drain implantations 38 run along the later ones Bit lines and can therefore also be referred to as bit line implantations.
• the entire ONO three-layer structure 20 does not have to be removed, but that the implantation can be carried out, for example, through the lower oxide layer 14, which then serves as a scattering oxide.
• the implantation is carried out through the lower oxide layer 14, this must subsequently be removed in order to to expose the upper surface of the substrate 12 in the region in which the source / drain implantation was carried out and in which the metallic bit lines are to be formed.
• a metal is deposited for a self-aligned siliconization, preferably Ti, Co or alloys thereof. This is followed by the tempering required for siliconization and then the removal of the non-siliconized material.
• the metallizations 40 shown in FIG. 4b are generated on the source / drain implantations 38, which represent the metallic bit lines 40.
• the remaining spaces are then filled with an insulating material 42, preferably using an oxide deposition (TEOS).
• TEOS oxide deposition
• the resulting surface is then subjected to planarization, for example using reactive ion etching or preferably a CMP technique, in which case the very hard nitride layer can serve as a mechanical grinding stop.
• the resulting structure is shown schematically in cross section in Fig. 4b.
• the nitride still present on the strip-shaped gate region 34 which is denoted by the reference symbol 44 in FIG. 4b, is first removed by wet chemistry, for which purpose hot phosphoric acid is preferably used.
• a layer structure composed of a second polycrystalline layer 46, a metallic layer 48 and a hard mask 50, preferably nitride is produced on the resulting structure.
• the second polycrystalline layer 46 is formed by deposition, while the metallic layer 48 is formed by deposition of WSi.
• a layer sequence of polycrystalline silicon, tungsten nitride and tungsten can be produced here, as was explained above.
• the nitride layer 50 is generated as a hard mask by a deposition.
• the layer structure resulting in the peripheral region from the method steps described above is shown in FIG. 5, the ONO three-layer structure 20 being replaced by a gate oxide layer 52 in the peripheral region, as described above.
• a photo technique is subsequently carried out in order to structure the word lines within the cell array and the gate regions in the hard mask 50 in the periphery.
• the word line structure consisting of first polycrystalline layer 22, second polycrystalline layer 46 and metal layer 48 is then etched with high selectivity to oxide.
• An optional anti-punch implantation is then carried out between the word lines, for example using a suitable photo technique.
• FIG. 6a A sectional view of the resulting structure defined by arrows A in FIG. 4c is shown in FIG. 6a, while a sectional view defined by arrows B is shown in FIG. 6b. 6a, the above-mentioned anti-punch implantations are designated by the reference symbol 54.
• FIG. 7 shows a gate stack of such a transistor gate consisting of first polycrystalline layer 22, second poly ⁇ crystalline layer 46, metallic layer 48 and remaining hard mask layer 50 is shown.
• Vu II t ⁇ ⁇ ⁇ DJ d O ⁇ OH ⁇ j O ⁇ 0 ⁇ - 0- ⁇ O t ⁇ 0 a - d rt ⁇ rt O o ⁇ ⁇ ⁇ - ⁇ - ⁇ DJ 0 d vQ ⁇ - zd C ⁇ iQ ⁇ d 0 1 DJ d ⁇ er a ⁇ ⁇ • • ⁇ ⁇ • - er 2 d 0- D ⁇ rt d J 2 rt ⁇
• the reoxidation is preferably carried out before the LDD implantation, so that an oxide produced thereby over the source / drain regions can serve as scatter oxide for the LDD implantation.
• Anisotropic etching processes remove the oxide generated on the horizontal surfaces during reoxidation.
• nitride spacer layers 62 are produced on the oxide layers 60, whereupon further oxide spacer layers 64 are applied to the lateral surfaces, see FIG. 11, which lead to a complete filling 66 of the word line interstices in the memory cell region.
• the design of the spacer layers or the choice of material thereof depends on the dielectric strength of the peripheral transistors to be produced.
• the outer oxide spacer layers 64 are in turn preferably produced by a conformal oxide deposition (from TEOS), whereupon the oxide deposited on horizontal surfaces is subsequently removed by anisotropic etching. With this etching, the remaining parts of the hard mask 56 are simultaneously removed, so that the remaining areas of the second polycrystalline layer 46 are exposed.
• a conformal oxide deposition from TEOS
• anisotropic etching With this etching, the remaining parts of the hard mask 56 are simultaneously removed, so that the remaining areas of the second polycrystalline layer 46 are exposed.
• a salicide process is subsequently carried out in order to provide both the word lines in the memory cell area and the gate stacks in the peripheral area with a metallization layer 70.
• a metal, Ti, Co or alloys thereof is first applied over the entire surface, whereupon an annealing step is carried out in order to produce the silicide layers 70.
• silicide layers 72 are also produced on the source / drain regions of the peripheral transistors.
• the parts of the applied metal layer which do not undergo a chemical reaction with silicon during the annealing step are preferably removed using a wet etching process. At this point it should be noted that during the tempering step of the siliconization also a
• Diffusion of the doping introduced into the second polycrystalline layer 46 during the implantation of the HDD regions 68 takes place in the first polycrystalline layer 22.
• the gate regions ie the gate polysilicon, can be p + -doped in the region of the memory cell array, which can have advantages with regard to the behavior of the memory cells.
• the present invention thus enables an advantageous process engineering integration of the generation of metallic bit lines, and metallic word lines, for memory cell arrays, which enables the construction of large cell blocks with a minimal cell area of the individual cells.
• the present invention further enables extensive
• Source / drain implantation 10 silicon substrate 12 transistor wells 14 lower oxide layer 16 nitride layer 18 upper oxide layer 20 ONO structure 22 polycrystalline silicon 24 hard mask layer 26 recesses in nitride layer 28 strips
• bit line recesses 32 doped regions 34 strip-shaped gate regions 36 insulating spacer layers 38 source / drain implantations 40 metallic bit line 42 insulating material / oxide 44 nitride 46 remaining on gate regions 46 second polycrystalline layer 48 metallic layer 50 hard mask 52 gate oxide layer 54 antipunch implantation 56 Oxide hard mask layer 58 LDD implantation 60 reoxidation layer 62 nitride spacer layer 64 outer oxide spacer layer 66 word line interstice filling 68 HDD implantation 70 silicide layer 72 Silicide layer on source / drain areas

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