KR100608407B1 - 비트 라인 생성 방법 및 메모리 셀 어레이 생성 방법 및메모리 셀 어레이 - Google Patents

비트 라인 생성 방법 및 메모리 셀 어레이 생성 방법 및메모리 셀 어레이 Download PDF

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KR100608407B1
KR100608407B1 KR1020037011519A KR20037011519A KR100608407B1 KR 100608407 B1 KR100608407 B1 KR 100608407B1 KR 1020037011519 A KR1020037011519 A KR 1020037011519A KR 20037011519 A KR20037011519 A KR 20037011519A KR 100608407 B1 KR100608407 B1 KR 100608407B1
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layer
bit line
region
gate region
storage medium
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KR20030088444A (ko
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카코쉬케롤랜드
빌러조세프
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인피네온 테크놀로지스 아게
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020037011519A 2001-03-02 2002-02-13 비트 라인 생성 방법 및 메모리 셀 어레이 생성 방법 및메모리 셀 어레이 Expired - Fee Related KR100608407B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10110150.3 2001-03-02
DE10110150A DE10110150A1 (de) 2001-03-02 2001-03-02 Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray
PCT/EP2002/001508 WO2002080275A2 (de) 2001-03-02 2002-02-13 Speicherzellenarrays und deren herstellungssverfahren

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KR20030088444A KR20030088444A (ko) 2003-11-19
KR100608407B1 true KR100608407B1 (ko) 2006-08-03

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US (1) US6686242B2 (enExample)
EP (1) EP1364409A2 (enExample)
JP (1) JP2004530296A (enExample)
KR (1) KR100608407B1 (enExample)
CN (1) CN100336227C (enExample)
AU (1) AU2002338242A1 (enExample)
DE (1) DE10110150A1 (enExample)
TW (1) TW540141B (enExample)
WO (1) WO2002080275A2 (enExample)

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6566194B1 (en) * 2001-10-01 2003-05-20 Advanced Micro Devices, Inc. Salicided gate for virtual ground arrays
US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6700818B2 (en) * 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6706595B2 (en) * 2002-03-14 2004-03-16 Advanced Micro Devices, Inc. Hard mask process for memory device without bitline shorts
TWI291748B (en) * 2002-03-20 2007-12-21 Macronix Int Co Ltd Method and structure for improving reliability of non-volatile memory cell
US20030181053A1 (en) * 2002-03-20 2003-09-25 U-Way Tseng Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof
US6777725B2 (en) * 2002-06-14 2004-08-17 Ingentix Gmbh & Co. Kg NROM memory circuit with recessed bitline
US8080453B1 (en) 2002-06-28 2011-12-20 Cypress Semiconductor Corporation Gate stack having nitride layer
US7256083B1 (en) * 2002-06-28 2007-08-14 Cypress Semiconductor Corporation Nitride layer on a gate stack
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
KR100452037B1 (ko) * 2002-07-18 2004-10-08 주식회사 하이닉스반도체 반도체 소자의 제조방법 및 그 소자
DE10239491A1 (de) * 2002-08-28 2004-03-18 Infineon Technologies Ag Verfahren zur Herstellung vergrabener Bitleitungen in einem Halbleiterspeicher
US6815274B1 (en) * 2002-09-13 2004-11-09 Taiwan Semiconductor Manufacturing Co. Resist protect oxide structure of sub-micron salicide process
US6773988B1 (en) * 2002-09-13 2004-08-10 Advanced Micro Devices, Inc. Memory wordline spacer
US7049188B2 (en) * 2002-11-26 2006-05-23 Advanced Micro Devices, Inc. Lateral doped channel
DE10258194B4 (de) * 2002-12-12 2005-11-03 Infineon Technologies Ag Halbleiterspeicher mit Charge-trapping-Speicherzellen und Herstellungsverfahren
DE10258420B4 (de) 2002-12-13 2007-03-01 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterspeichereinrichtung mit Charge-trapping-Speicherzellen und vergrabenen Bitleitungen
DE10259783A1 (de) * 2002-12-19 2004-07-15 Infineon Technologies Ag Verfahren zur Verbesserung der Prozessschrittfolge bei der Herstellung von Halbleiterspeichern
US7178004B2 (en) * 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
DE10324052B4 (de) * 2003-05-27 2007-06-28 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterspeichers mit Charge-Trapping-Speicherzellen
JP4818578B2 (ja) * 2003-08-06 2011-11-16 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置およびその製造方法
US7123532B2 (en) * 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7371637B2 (en) * 2003-09-26 2008-05-13 Cypress Semiconductor Corporation Oxide-nitride stack gate dielectric
US7041545B2 (en) * 2004-03-08 2006-05-09 Infineon Technologies Ag Method for producing semiconductor memory devices and integrated memory device
US6989320B2 (en) * 2004-05-11 2006-01-24 Advanced Micro Devices, Inc. Bitline implant utilizing dual poly
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) * 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US20060084219A1 (en) * 2004-10-14 2006-04-20 Saifun Semiconductors, Ltd. Advanced NROM structure and method of fabrication
US20060146624A1 (en) * 2004-12-02 2006-07-06 Saifun Semiconductors, Ltd. Current folding sense amplifier
US8125018B2 (en) 2005-01-12 2012-02-28 Spansion Llc Memory device having trapezoidal bitlines and method of fabricating same
CN1838328A (zh) 2005-01-19 2006-09-27 赛芬半导体有限公司 擦除存储器阵列上存储单元的方法
US7186607B2 (en) * 2005-02-18 2007-03-06 Infineon Technologies Ag Charge-trapping memory device and method for production
JP4275086B2 (ja) * 2005-02-22 2009-06-10 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
US7405441B2 (en) * 2005-03-11 2008-07-29 Infineon Technology Ag Semiconductor memory
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US20060223267A1 (en) * 2005-03-31 2006-10-05 Stefan Machill Method of production of charge-trapping memory devices
US7341909B2 (en) * 2005-04-06 2008-03-11 Micron Technology, Inc. Methods of forming semiconductor constructions
US7341956B1 (en) 2005-04-07 2008-03-11 Spansion Llc Disposable hard mask for forming bit lines
US7285499B1 (en) 2005-05-12 2007-10-23 Advanced Micro Devices, Inc. Polymer spacers for creating sub-lithographic spaces
US7208373B2 (en) * 2005-05-27 2007-04-24 Infineon Technologies Ag Method of forming a memory cell array and a memory cell array
US20060281255A1 (en) * 2005-06-14 2006-12-14 Chun-Jen Chiu Method for forming a sealed storage non-volative multiple-bit memory cell
EP1746645A3 (en) * 2005-07-18 2009-01-21 Saifun Semiconductors Ltd. Memory array with sub-minimum feature size word line spacing and method of fabrication
DE102005038939B4 (de) * 2005-08-17 2015-01-08 Qimonda Ag Halbleiterspeicherbauelement mit oberseitig selbstjustiert angeordneten Wortleitungen und Verfahren zur Herstellung von Halbleiterspeicherbauelementen
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US20080025084A1 (en) * 2005-09-08 2008-01-31 Rustom Irani High aspect ration bitline oxides
US20070096199A1 (en) * 2005-09-08 2007-05-03 Eli Lusky Method of manufacturing symmetric arrays
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7642158B2 (en) 2005-09-30 2010-01-05 Infineon Technologies Ag Semiconductor memory device and method of production
US20070082446A1 (en) * 2005-10-07 2007-04-12 Dominik Olligs Methods for fabricating non-volatile memory cell array
US7432178B2 (en) * 2005-10-21 2008-10-07 Advanced Micro Devices, Inc. Bit line implant
US20070120180A1 (en) * 2005-11-25 2007-05-31 Boaz Eitan Transition areas for dense memory arrays
US7538384B2 (en) * 2005-12-05 2009-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory array structure
US7368350B2 (en) 2005-12-20 2008-05-06 Infineon Technologies Ag Memory cell arrays and methods for producing memory cell arrays
US7352627B2 (en) * 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) * 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US20070173017A1 (en) * 2006-01-20 2007-07-26 Saifun Semiconductors, Ltd. Advanced non-volatile memory array and method of fabrication thereof
US8253452B2 (en) * 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) * 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) * 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7811935B2 (en) * 2006-03-07 2010-10-12 Micron Technology, Inc. Isolation regions and their formation
US7531867B2 (en) * 2006-03-27 2009-05-12 Infineon Technologies Ag Method for forming an integrated memory device and memory device
US7408222B2 (en) * 2006-03-27 2008-08-05 Infineon Technologies Ag Charge trapping device and method of producing the charge trapping device
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7678654B2 (en) * 2006-06-30 2010-03-16 Qimonda Ag Buried bitline with reduced resistance
US7790516B2 (en) * 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells
US7608504B2 (en) * 2006-08-30 2009-10-27 Macronix International Co., Ltd. Memory and manufacturing method thereof
US7605579B2 (en) * 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US20080081424A1 (en) * 2006-09-29 2008-04-03 Josef Willer Method of production of a semiconductor memory device and semiconductor memory device
US20080111182A1 (en) * 2006-11-02 2008-05-15 Rustom Irani Forming buried contact etch stop layer (CESL) in semiconductor devices self-aligned to diffusion
US8252640B1 (en) 2006-11-02 2012-08-28 Kapre Ravindra M Polycrystalline silicon activation RTA
US20080150011A1 (en) * 2006-12-21 2008-06-26 Spansion Llc Integrated circuit system with memory system
US8536640B2 (en) 2007-07-20 2013-09-17 Cypress Semiconductor Corporation Deuterated film encapsulation of nonvolatile charge trap memory device
US9018693B2 (en) 2007-07-20 2015-04-28 Cypress Semiconductor Corporation Deuterated film encapsulation of nonvolatile charge trap memory device
US7691751B2 (en) * 2007-10-26 2010-04-06 Spansion Llc Selective silicide formation using resist etchback
CN101587863B (zh) * 2008-05-23 2011-03-23 中芯国际集成电路制造(上海)有限公司 用于基于sonos的快闪存储的多晶硅栅极蚀刻方法和器件
JP5390822B2 (ja) * 2008-10-02 2014-01-15 スパンション エルエルシー 半導体装置及び半導体装置の製造方法
KR101194872B1 (ko) * 2010-04-19 2012-10-25 에스케이하이닉스 주식회사 반도체 기억 장치
US8441063B2 (en) * 2010-12-30 2013-05-14 Spansion Llc Memory with extended charge trapping layer
US8546226B2 (en) * 2011-07-25 2013-10-01 United Microelectronics Corp. SONOS non-volatile memory cell and fabricating method thereof
US9006827B2 (en) * 2011-11-09 2015-04-14 International Business Machines Corporation Radiation hardened memory cell and design structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0368097A2 (en) * 1988-11-10 1990-05-16 Texas Instruments Incorporated A cross-point contact-free floating-gate memory array with silicided buried bitlines
KR20000035785A (ko) * 1996-08-01 2000-06-26 칼 하인쯔 호르닝어 비휘발성 메모리 셀

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2755613B2 (ja) 1988-09-26 1998-05-20 株式会社東芝 半導体装置
US5238855A (en) * 1988-11-10 1993-08-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
JP2893894B2 (ja) * 1990-08-15 1999-05-24 日本電気株式会社 不揮発性メモリ及びその製造方法
US5270240A (en) * 1991-07-10 1993-12-14 Micron Semiconductor, Inc. Four poly EPROM process and structure comprising a conductive source line structure and self-aligned polycrystalline silicon digit lines
US5246874A (en) * 1992-06-02 1993-09-21 National Semiconductor Corporation Method of making fast access AMG EPROM
KR100277267B1 (ko) * 1992-11-25 2001-02-01 사와무라 시코 반도체 불휘발성 메모리 및 그 제조방법
US5292681A (en) * 1993-09-16 1994-03-08 Micron Semiconductor, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5467308A (en) 1994-04-05 1995-11-14 Motorola Inc. Cross-point eeprom memory array
US5838041A (en) * 1995-10-02 1998-11-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having memory cell transistor provided with offset region acting as a charge carrier injecting region
KR100199382B1 (ko) * 1996-06-27 1999-06-15 김영환 플래쉬 메모리 소자의 제조방법
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US5679591A (en) 1996-12-16 1997-10-21 Taiwan Semiconductor Manufacturing Company, Ltd Method of making raised-bitline contactless trenched flash memory cell
TW463331B (en) * 1997-09-26 2001-11-11 Programmable Microelectronics Self-aligned drain contact PMOS flash memory and process for making same
EP0986100B1 (en) 1998-09-11 2010-05-19 STMicroelectronics Srl Electronic device comprising EEPROM memory cells, HV transistors, and LV transistors with silicided junctions, as well as manufacturing method thereof
EP1017097A1 (en) * 1998-12-29 2000-07-05 STMicroelectronics S.r.l. Manufacturing method of salicide contacts for non-volatile memory
JP2001044391A (ja) * 1999-07-29 2001-02-16 Fujitsu Ltd 半導体記憶装置とその製造方法
US6117730A (en) 1999-10-25 2000-09-12 Advanced Micro Devices, Inc. Integrated method by using high temperature oxide for top oxide and periphery gate oxide

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0368097A2 (en) * 1988-11-10 1990-05-16 Texas Instruments Incorporated A cross-point contact-free floating-gate memory array with silicided buried bitlines
KR20000035785A (ko) * 1996-08-01 2000-06-26 칼 하인쯔 호르닝어 비휘발성 메모리 셀

Also Published As

Publication number Publication date
CN100336227C (zh) 2007-09-05
CN1502134A (zh) 2004-06-02
US20020132430A1 (en) 2002-09-19
JP2004530296A (ja) 2004-09-30
WO2002080275A2 (de) 2002-10-10
DE10110150A1 (de) 2002-09-19
TW540141B (en) 2003-07-01
WO2002080275A3 (de) 2003-01-30
KR20030088444A (ko) 2003-11-19
US6686242B2 (en) 2004-02-03
EP1364409A2 (de) 2003-11-26
AU2002338242A1 (en) 2002-10-15

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