CN1870860A - 电子基板的制造方法、半导体装置及电子机器的制造方法 - Google Patents

电子基板的制造方法、半导体装置及电子机器的制造方法 Download PDF

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CN1870860A
CN1870860A CNA2006100827202A CN200610082720A CN1870860A CN 1870860 A CN1870860 A CN 1870860A CN A2006100827202 A CNA2006100827202 A CN A2006100827202A CN 200610082720 A CN200610082720 A CN 200610082720A CN 1870860 A CN1870860 A CN 1870860A
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substrate
manufacture method
semiconductor device
insulating barrier
wiring pattern
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伊东春树
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种电子基板的制造方法，具有：在基板(5)上埋入电子部件(40～42)的工序；和喷出含有导电性材料的液滴，形成与埋入在基板(5)中的电子部件(40～42)的外部连接电极(40a～42a)连接的布线图案(23)的工序。

Description

电子基板的制造方法、半导体装置及电子机器的制造方法
技术领域
本发明涉及一种电子基板的制造方法、半导体装置的制造方法、及电子机器的制造方法。
背景技术
近年来，随着电子机器的高性能化/小型化的发展，越来越要求搭载了电子部件的电子基板的进一步的高密度/高功能化。例如，在特开平3-69191号公报中公开了：形成在基板上的铜布线上搭载有电子部件，从其上方由树脂一并覆盖而形成电子部件埋入层，并由粘接剂层叠该电子部件埋入层，通过上述而制造电子基板的技术。
在特开2004-55967号公报中公开了：在电绝缘体薄片上压入电子部件，并通过加热加压将具有与该电子部件的外部连接电极抵接的导体膏(paste)的电绝缘体薄片一体化，从而实现电子基板的薄型化的技术。
在专利文献1的技术中，由于在具有铜布线的基板材上搭载有电子部件，因此很难实现薄型化/高密度化。在专利文献2的技术中，需要另外准备在与电子部件的外部连接电极相对应的位置上形成有导体膏的电绝缘体薄片，具有导致成本增加及生产率下降的可能性。
发明内容
本发明正是鉴于上述问题而提出的，其目的在于，提供一种不会导致成本增加及生产率降低，而可实现薄型化/高密度化的电子基板的制造方法、半导体装置的制造方法、及电子机器的制造方法。
本发明的电子基板的制造方法，是在基板上搭载了电子部件的电子基板的制造方法，其特征在于，具有：在所述基板上埋入所述电子部件的工序；和喷出含有导电性材料的液滴，形成与埋入在所述基板中的所述电子部件的外部连接电极连接的布线图案的工序。
从而，在本发明的电子基板的制造方法中，由于电子部件被埋入在基板上，因此可以制造埋入的深度浅的电子基板，能够实现薄型化/高密度化。另外，在本发明中，由于以液滴喷出方式形成用于与埋入在基板中的电子部件的外部连接电极连接的布线图案，因此抑制材料消耗。另外，通过根据布线图案形状移动喷头，能够容易且简单地形成任意的形状。其结果，不会导致成本提高及生产率的下降而能够制造电子基板。
作为在基板上埋入所述电子部件的工序，通过采用加热所述电子部件的工序、和使加热的所述电子部件与所述基板抵接，使该基板软化的工序，能够将电子部件容易地埋入软化后的基板中。
另外，通过使用由半硬化状态的树脂薄片材料形成的基板，能够在基板上容易地埋入电子部件。
在使用由半硬化状态的树脂薄片材料形成的基板时，优选设置：在所述树脂薄片材料上形成所述布线图案之后，使所述树脂薄片材料及所述布线图案硬化的工序。
由此，在本发明中，可以提高布线图案对基板的密接性。
另外，在本发明中，可适合采用具有喷出含有绝缘性材料的液滴，形成绝缘层的工序的方法。由此，能够容易且简单地形成绝缘层。此时，优选设置：在半硬化状态的所述基板上形成所述绝缘层之后，使所述基板及所述绝缘层硬化的工序。由此，在本发明中，可以提高绝缘层对基板的密接性。
另外，在形成绝缘层时，优选设置：通过所述液滴的喷出而形成贯通所述绝缘层，并与所述外部连接电极和所述布线图案连接的导电柱的工序。由此，可以容易地电连接形成在绝缘层上的布线图案和电子部件的外部连接电极。
进一步，可优选采用反复进行所述布线图案及所述绝缘层的形成工序的方法。
由此，在本发明中，可以以低成本容易地制造高密度且薄型的多层基板。
另外，在形成多层基板时，优选设置：喷出含有电子元件形成材料的液滴而形成电子元件的工序。
由此，在本发明中，能够形成高功能的电子基板。
另一方面，本发明的半导体装置的制造方法，是在基板上搭载有半导体元件的半导体装置的制造方法，其特征在于，通过前面所述的电子基板的制造方法，在所述基板上搭载所述半导体元件。
从而，在本发明的半导体装置的制造方法中，不会导致成本提高及生产率的降低而能够制造小型/薄型的半导体装置。
另外，在本发明中，优选设置：喷出含有导电性材料的液滴，形成与所述半导体元件连接的外部连接端子的工序。
由此，在本发明中，可抑制材料消耗，并且在任意的位置上容易且简单地形成外部连接端子。
此时，作为所述外部连接端子，可以经由贯通所述基板的贯通电极与所述半导体元件连接。由此，可在与埋入有基板的半导体元件的侧相反一侧设置外部连接端子。
本发明的电子机器的制造方法，是具有半导体装置的电子机器的制造方法，其特征在于，所述半导体装置由前面所述的半导体装置的制造方法来制造。
从而，在本发明中，不会导致成本提高及生产率的降低而可以制造小型/薄型的电子机器。
另外，在本发明中，优选设置：在支撑所述半导体装置的框体上粘接由半硬化状态的树脂薄片材料形成的基板的工序；在所述基板上埋入半导体元件的工序；和形成与埋入在所述基板上的所述半导体元件的外部连接电极连接的布线图案的工序。
从而，在本发明中，由于在框体上直接粘接基板，因此可制造更小型/薄型且高功能的电子机器。
附图说明
图1是表示在电子基板的制造中使用的液滴喷出装置的模式图。
图2A及2B是表示液滴喷出装置中的喷头的模式图。
图3A、3B、3C、3D及3E是表示本发明的电子基板的制造方法的工序图。
图4是多层结构基板的剖面图。
图5是设有外部连接端子的多层结构基板的剖面图。
图6是设有外部连接端子的另一方式的多层结构基板的剖面图。
图7是表示粘接固定有多层结构基板的电子机器的框体的剖面图。
图8是表示电子机器的一例的立体图。
具体实施方式
以下，参照图1至图8说明本发明的电子基板的制造方法、半导体装置的制造方法、及电子机器的制造方法的实施方式。
(液滴喷出装置)
首先，参照图1、2A及2B说明在电子基板、半导体装置及电子机器的制造中使用的液滴喷出装置。
图1所示的液滴喷出装置100，基本上是喷墨装置。详细而言，液滴喷出装置100，具备：保持液状材料111的容器101、管110、地面载置台(グランドステ一ジ、ground stage)GS、喷头部103、载置台106、第1位置控制装置104、第2位置控制装置108、控制部112、光照射装置140、和支撑部104a。
喷头部103保持有喷头114(参照图2A及2B)。喷头114，根据来自控制部112的信号喷出液状材料111的液滴。喷头部103中的喷头114，经由管110与容器101流体式连接。从容器101向喷头114供给液状材料111。
载置台106提供用于固定基板(后述的树脂基板5)的平面。并且，载置台106具有利用吸引力固定基板的位置的功能。
第1位置控制装置104，通过支撑部104a固定在距离地面载置台GS规定高度的位置上。第1位置控制装置104，具有根据来自控制部112的信号使喷头部103沿着X轴方向、和与X轴方向正交的Z轴方向移动的功能。进一步，第1位置控制装置104，也具有以与Z轴平行的轴的旋转方向使喷头部103旋转的功能。在本实施例中，Z轴方向是与垂直方向(即重力加速度的方向)平行的方向。
第2位置控制装置108，根据来自控制部112的信号在地面载置台GS上使载置台106向Y轴方向移动。Y轴方向是与X轴方向及Z轴方向两者正交的方向。
具有上述那样的功能的第1位置控制装置104的结构和第2位置控制装置108的结构，可通过利用线性电机或伺服电机的周知的XY机器人来实现。在此，省略它们的详细的结构的说明。在本说明书中，将第1位置控制装置104及第2位置控制装置108根据需要标记为“机器人”或“扫描部”。
如上所述，通过第1位置控制装置104，喷头部103向X轴方向移动。通过第2位置控制装置108，基板与载置台106都向Y轴方向移动。其结果，喷头114相对基板的相对位置会变化。即，喷头部103、喷头114、或喷嘴118(参照图2A及2B)，相对基板在Z轴方向保持规定的距离，同时向X轴方向及Y轴方向相对移动，即，相对地进行扫描。“相对移动”或“相对扫描”意味着喷出液状材料111的物体、和喷出物滴落的物体(被喷出部)的至少一个对另一个进行相对移动。
控制部112，构成为从外部信息处理装置接收表示应喷出液状材料111的液滴的相对位置的喷出数据。控制部112，将接收后的喷出数据储存到内部的存储装置中，同时根据储存的喷出数据，控制第1位置控制装置104、第2位置控制装置108、和喷头114。喷出数据，是指用于在基板上以规定图案付与液状材料111的数据。在本实施例中，喷出数据具有位图数据的形式。
具有上述结构的液滴喷出装置100，根据喷出数据使喷头114的喷嘴118(参照图2A及2B)相对基板进行相对移动，同时从喷嘴118向被喷出部喷出液状材料111。将由液滴喷出装置100产生的喷头114的相对移动、和从喷头114的液状材料111的喷出统一标记为“涂敷扫描”或“喷出扫描”。
光照射装置140，向付与基板上的液状材料111照射紫外线。光照射装置140的紫外线照射的开/关(ON/OFF)由控制部112来控制。
如图2A及2B所示，液滴喷出装置100中的喷头114是具有多个喷嘴118的喷墨头。具体而言，喷头114具备振动板126、多个喷嘴118、规定多个喷嘴118的各个开口的喷嘴板128、液体储存部129、多个隔壁122、多个空腔120、和多个振动子124。
液体储存部129位于振动板126和喷嘴板128之间。在液体储存部129中通常填充有从未图示的外部容器经由孔131供给的液状材料111。多个隔壁122位于振动板126和喷嘴板128之间。
空腔120是由振动板126、喷嘴板128、和一对隔壁122所包围的部分。由于空腔120与喷嘴118对应设置，因此空腔120的数目和喷嘴118的数目相等。在空腔120内，经由位于一对隔壁122之间的供给口130，从液体储存部129供给液状材料111。在本实施例中，喷嘴118的直径大约为27μm。
多个振动子124分别以与各个空腔120对应的方式位于振动板126上。多个振动子124分别包括压电元件124C、和夹持压电元件124C的一对电极124A、124B。控制部112，通过在一对电极124A、124B之间施加驱动电压，而从相对应的喷嘴118喷出液状材料111的液滴D。从喷嘴118喷出的材料的体积可在0p1以上42p1(皮升，pico litre)以下之间变化。调整喷嘴118的形状，以便从喷嘴118向Z轴方向喷出液状材料111的液滴。
喷出部127，也可以具有电热转换元件来代替压电元件。即，喷出部127，也可以具有利用由电热转换元件引起的材料的热膨胀，喷出材料的结构。
(电子基板的制造方法)
接着，使用上述的液滴喷出装置100说明制造电子基板的工序。
图3A～3E是表示电子基板的制造方法的工序图。在图3A～3E中，符号5表示由树脂薄片形成的基板，符号40表示半导体元件(电子部件)，符号41、42表示片式部件(电子部件)。
作为树脂基板5，以半硬化状态使用聚酰亚胺或环氧系的树脂。本发明中的半硬化状态是表示对利用由加热或UV等的光照射产生的能量付与而硬化的树脂，付与能量之前的状态。
作为片式(chip)部件41、42，可以使用片式电感器(chip inductor)、片式电阻器、片式热敏电阻、二极管、变阻器、LSI裸片、和LSI封装等。各个片式部件41、42分别具有作为外部连接电极的电极41a、42a。
同样，半导体元件40具有作为外部连接电极的电极40a。电极40a相对AI电极部40b被设置成由无电解Ni/Au电镀等形成的金属凸块。
在树脂基板5上搭载上述的半导体元件40、片式部件41、42之时，首先，如图3A所示，利用支架(マウンタ、mounter)等将片式部件41、42配置在树脂基板5的上方的规定位置上。此时，半导体元件40、片式部件41、42被配置成电极40a～42a朝向上侧。树脂基板5，设置为半硬化状态。半导体元件40、片式部件41、42预先被加热成树脂基板5的硬化温度以下。在本实施方式中，对于在大约160℃下开始硬化的树脂基板5，将半导体元件40、片式部件41、42加热到大约100℃。
接着，将加热后的半导体元件40、片式部件41、42抵接在树脂基板5的上面。由此，树脂基板5不会硬化而会软化。通过压入半导体元件40、片式部件41、42，如图3B所示，埋入到树脂基板5中。此时，以电极40a～42a从树脂基板5的上面突出的深度分别埋入半导体元件40、片式部件41、42。
接着，如图3C所示，利用上述的液滴喷出装置100，在电极40a～42a上分别喷出含有导电性材料的液滴。通过将这些液滴干燥/烧制，而分别形成导电柱40P～42P。此时，以顶部的高度大致相同的方式形成导电柱40P～42P。
作为本实施方式的导电性材料，含有平均粒径为10nm左右的银粒子、和分散介质。并且在导电性材料中，银粒子稳定地分散在分散介质中。银粒子也可以被涂敷剂所覆盖。涂敷剂是可与银原子进行配位的化合物。
平均粒径为从1nm左右到数100nm为止的粒子，也标记为“纳米(nano)粒子”。根据该标记，导电性材料含有银的纳米粒子。
作为分散介质(或溶剂)，只要可分散银粒子等的导电性微粒子而不产生凝集便没有特别限定。例如，除了水之外，还能例举甲醇、乙醇、丙醇、丁醇等醇类、n-庚烷、n-辛烷、癸烷、十二烷、十四烷、甲苯、二甲苯、异丙基甲苯、杜烯、茚、二戊烯、四氢化萘、十氢化萘、环己基苯等烃系化合物、或乙二醇二甲醚、乙二醇二乙醚、乙二醇甲乙醚、二甘醇二甲醚、二甘醇二乙醚、二甘醇甲乙醚、1、2-二甲氧基乙烷、双(2-甲氧基乙基)醚、p-二噁烷等醚系列化合物，还有碳酸丙烯酯、γ-丁内酯、N-甲基-2-吡咯烷酮、二甲基甲酰胺、二甲亚砜、环己酮等极性化合物。其中，从导电性微粒子的分散性和分散液的稳定性、或向液滴喷出法的适用的容易度这一点上，优选采用水、醇类、烃系化合物、醚系化合物，作为更优选的分散介质，可列举水、烃系化合物。
接着，如图3D所示，利用液滴喷出装置100，以露出导电柱40P～42P的顶部的方式在树脂基板5上喷出含有绝缘层形成材料的液滴，而形成绝缘层10。
在通过绝缘层形成工序形成绝缘层10之时，以绝缘层10的表面大致成为平坦面，同时绝缘层10包围电极40a～42a的侧面的方式，调整向树脂基板5喷出的液滴的总数、使液滴滴落的位置、和使液滴滴落的位置的间隔。进一步，在本实施方式中，以绝缘层10的厚度不超过电极40a～42a的厚度的方式，调整喷出的液滴的总数或使液滴滴落的位置的间隔。
作为本实施方式的绝缘层形成材料，例如含有感光性的树脂材料。具体而言，绝缘层形成材料含有光致聚合开始剂、丙烯酸的单体和/或低聚物。
接着，如图3E所示，利用液滴喷出装置100在绝缘层10上的规定位置上喷出含有导电性材料的液滴，而形成与导电柱40P～42P连接的布线图案23。作为用于形成布线图案23的导电性材料，可以采用与导电柱40P～42P相同的材料。
此外，在喷出含有导电性材料的液滴而形成布线图案23之前，也可以设置在绝缘层10的表面上付与疏液性的工序。
具体而言，将原料化合物(例如FAS)的溶液和具有绝缘层10的树脂基板5放入到同一个密闭容器中，并在室温下放置2～3日左右。由此，在表面上形成由有机分子膜构成的自体组织化膜(即FAS膜)。由此，通过向绝缘膜10付与疏液性，使喷出在绝缘层10上的液滴的润湿扩散的程度变小，因此能够形成微细线宽度的布线图案23。
其后，通过将半硬化状态的树脂基板5与绝缘层10及布线图案23一起加热到硬化温度以上的温度，在树脂基板5上可制造搭载了半导体元件40、片式部件41、42的电子基板11。
如上所述，在本实施方式中，由于在树脂基板5上埋入半导体元件40、片式部件41、42，因此与在树脂基板5上装载半导体元件40、片式部件41、42的情况相比，能够得到可实现薄型化/高密度化的电子基板11。另外，在本实施方式中，以液滴喷出方式形成布线图案23及导电柱40P～42P，因此对材料消耗的浪费较少。另外，由于不利用光刻法等方法而能够容易且高精度地描绘任意的图案，因此可有助于成本降低及生产率提高。
另外，在本实施方式中，由于通过在比树脂基板5的硬化温度更低的温度下加热半导体元件40、片式部件41、42而使树脂基板5软化，因此半导体元件40、片式部件41、42的埋入作业变得容易，可有助于生产率的提高。进一步，在本实施方式中，由于同时加热树脂基板5及绝缘层10及布线图案23并使其硬化，因此可提高树脂基板5和绝缘层10之间的密接性、及绝缘层10和布线图案23之间的密接性，从而得到高品质的电子基板11。
此外，在上述实施方式中，为了容易进行埋入作业，而设置了加热半导体元件40、片式部件41、42的工序，但是并不局限于此，也可以在不加热的状态下进行压入并埋入的工序。
另外，在上述实施方式中，虽然以形成导电柱40P～42P之后形成绝缘层10的顺序进行，但是也可以通过相反的顺序在形成绝缘层10之后形成导电柱40P～42P。
(多层结构基板)
接着，说明具有上述的电子基板11的多层结构基板。
本实施方式的多层结构基板，通过对由图3A～3E所示的工序制造出的电子基板11反复进行绝缘层形成、导电柱形成及布线图案形成等、与上述实施方式相同的工序而制造图4所示的结构的多层结构基板(半导体装置)1。
具体而言，在图4的多层结构基板1中的绝缘层10上以绝缘层12～16的顺序层叠有绝缘层12～16。半导体元件43被绝缘层13、14埋入到多层结构基板1上，同时在最上部配置/搭载有半导体元件44及片式部件45。在各个绝缘层12～16中，与上述的第1实施方式相同地形成布线图案，同时以贯通各个绝缘层的方式在规定位置上形成导电柱。
在该多层结构基板1中，也可以使用含有电阻体形成材料的液滴(电阻体印墨)、含有高电介质形成材料的液滴(高电介质印墨)等，而形成电阻、电容器、电感器等电子元件。
例如，在形成在图4所示的绝缘层12上的作为布线图案的电极20A上通过液滴喷出方式形成电介质层DI。在形成绝缘层13之后，通过液滴喷出方式，在电介质层DI上形成作为布线图案的电极20B。电介质层DI、和电极20A、20B构成作为电子元件的电容器42。此外，为了通过液滴喷出工序形成电介质层DI，而使所喷出的液状材料基本上与绝缘层形成材料相同。
另外，在多层结构基板1中，对半导体元件44等进行软钎焊时，在利用液滴喷出方式形成的布线图案23A上优选形成可锡焊的金属膜22。作为此时的金属膜22，可以由无电解Ni/Au电镀、或以液滴喷出方式涂敷含有金属粒子的液状体的方法来形成。
在本实施方式中，由于利用上述的电子基板制造方法，因此能够得到可实现薄型且高密度化的多层结构基板1。
(半导体装置)
接着，说明半导体装置的制造方法。如图5所示，本实施方式的半导体装置对具有图4所示的电子基板11的多层结构基板1，构成为：在形成在绝缘层15上的布线图案23A上设置电极24，并且在该电极24上分别设置外部连接端子25。
作为制造该半导体装置的方法，以上述的液滴喷出方式在绝缘层15上喷出含有导电性材料的液滴而形成布线图案23A，同时通过无电解Ni/Au电镀、或以液滴喷出方式涂敷含有金属微粒子的液状体的方法在布线图案23A上形成电极24。
接着，除去形成电极24及外部连接端子25的连接区域，而喷出含有绝缘层形成材料的液滴并形成绝缘层16之后，在该连接区域上喷出含有金属微粒子的液滴并形成外部连接端子25。
由此，通过使用具有电子基板11的多层结构基板1，能够得到可实现薄型且高密度化的半导体装置。
此外，在上述的半导体装置中，以依次形成电极24、绝缘层16、外部连接端子25的顺序进行，但并不局限于此，也可以在形成绝缘层16之后形成电极24及外部连接端子25的顺序、或在形成电极24及外部连接端子25之后形成绝缘层16的顺序进行。在这些工序中，最后形成绝缘层16时，优选对布线图案23A进行亲液化，以便即使在外部连接端子25的下部也润湿扩散含有绝缘性材料的液滴。
另外，除了图5所示的结构以外，如图6所示，能够制造：设置用于贯通树脂基板5的贯通电极5A，同时在树脂基板5的与绝缘层10相反侧的面(背面)上形成与贯通电极5A连接的布线图案23B(在图6中只与两端的布线图案23B的贯通电极5A连接)，在该布线图案23B上与上述的电极24及外部连接端子25相同地设置电极24A及外部连接端子25A的半导体装置。
作为制造该半导体装置的方法，在形成在树脂基板5上的贯通孔中以上述的液滴喷出方式喷出含有导电性材料的液滴并形成贯通电极5A之后，在树脂基板5的背面上喷出含有导电性材料的液滴并以与贯通电极5A连接的方式形成布线图案23B，同时以与电极24相同的方法形成电极24A。
接着，除去形成电极24A及外部连接端子25A的连接区域，而喷出含有绝缘层形成材料的液滴并形成绝缘层17之后，在该连接区域上喷出含有金属微粒子的液滴并形成外部连接端子25A。
由此，能够得到在多层结构基板1的背面侧形成外部连接端子25A的可实现薄型且高密度化的半导体装置。
(电子机器)
接着，说明电子机器的制造方法。图7是在电子机器的框体K中，具有电子基板11的多层结构基板1粘接固定在树脂基板5上的剖面图。
在制造该电子机器之时，也可以设置，在制造图4所示的多层结构基板1之后与框体K粘接的工序，或也可设置如图3A中双点划线所示，在框体K上粘接树脂基板5之后，如图3B～3E所示，埋入半导体元件40及片式部件41、42、和形成导电柱、绝缘层、布线图案等的工序。
图8是表示具有上述多层结构基板1的本发明的电子机器的一例的立体图。在该图中所示的携带电话(电子机器)1300，具备作为小尺寸的显示部1301的液晶装置，还具备多个操作按钮1302、受话口1303、及送话口1304，在框体K的内部粘接收容有上述的多层结构基板1。
本实施方式的携带电话1300，由于利用上述的电子机器的制造方法来制造，因此能够得到可实现薄型、高密度化/高功能化的电子机器。
作为上述实施方式的电子机器，并不局限于上述携带电话，能够适用于电子书、个人计算机、数码相机、液晶电视机、取景器型或显示器直视型的磁带录像机、汽车导航装置、寻呼机、电子笔记本、电子计算器、文字处理器、工作站、可视电话、POS终端、和具备触摸屏的机器等中，能够对任意的电子机器实现薄型、高密度化/高功能化。
以上，参照附图说明了本发明的最佳的实施方式，但本发明并不局限于上述例子。在上述的例子中所示的各个结构部件的诸形状或组合等为一例，在不脱离本发明的主旨的范围内基于设计要求等可以进行各种变更。
例如，在形成图3E中所示的布线图案23时，也可以进行下述工序：利用具有与布线图案相对应的凹凸的模具来模压(型押)绝缘层10，在绝缘层10上形成与布线图案相对应的沟部、和包围该沟部的隔壁部(围堰)，并在沟部涂敷含有导电性材料的液滴的工序。
根据该制造方法，可以形成具有与沟部的宽度、深度相对应的宽度、高度的布线图案，能够高精度地形成微细线宽度的图案。
另外，虽然在上述实施方式中，在导电性材料中含有银的纳米粒子的结构，但是代替银的纳米粒子，也可以使用其他金属的纳米粒子。在此，作为其他金属，例如也可以利用金、白金、铜、钯、铑、锇、钌、铱、铁、锡、锌、钴、镍、铬、钛、钽、钨、铟的任意一个，或也可以利用组合了任意两个以上的合金。但是，只要是银就可在较低的温度下进行还原，因此容易进行处理，在这一点上，利用液滴喷出装置时，优选利用含有银的纳米粒子的导电性材料。
另外，导电性材料，也可以含有有机金属化合物来代替金属的纳米粒子。在此所谓的有机金属化合物是通过由加热引起的分解而析出金属的化合物。在上述的有机金属化合物中，具有：氯三乙基膦金(I)、氯三甲基膦金(I)、氯三苯基膦金(I)、银(I)2、4-乙酰丙酮(ペンタンヂオナト)络合物、三甲基膦(六氟乙酰丙酮，ヘキサフルオロアセチルアセトナ一ト)银(I)络合物、铜(I)六氟乙酰丙酮环辛二烯(ヘキサフルオロペンタンジオナトシクロオクタジエン)络合物等。
由此，在液状的导电性材料中所含有的金属的形态也可以是以纳米粒子为代表的粒子的形态，也可以是如有机金属化合物那样的化合物的形状。
进一步，导电性材料，也可代替金属，含有聚苯胺、聚噻吩、聚亚苯基亚乙烯基等高分子系列的可溶性材料。
另外，导电性材料中的银的纳米粒子，也可以被有机物等涂敷剂所覆盖。作为这样的涂敷剂，已知胺、醇、硫醇等。具体而言，作为涂敷剂，具有2-甲氨基乙醇、二乙醇胺、二乙基甲基胺、2-二甲氨基乙醇、甲基二乙醇胺等胺化合物、烷基胺类、乙撑二胺、烷基醇、乙二醇、丙二醇、烷基硫醇类、乙二硫醇(エタンジチオ一ル)等。被涂敷剂所覆盖的银的纳米粒子可在分散介质中更稳定地分散。
还有，在上述实施方式中，绝缘材料含有光致聚合开始剂、丙烯酸的单体和/或低聚物的结构，但绝缘材料也可以含有光致聚合开始剂、具有乙烯基、环氧基等聚合性官能基的单体和/或低聚物，来代替丙烯酸的单体和/或低聚物。
另外，作为绝缘材料，也可以是溶解有具有光官能基的单体的有机溶液。在此，作为具有光官能基的单体，可以利用光硬化性亚胺单体。
另外，作为树脂材料的单体本身具有适合于从喷嘴118的喷出的流动性时，代替使用溶解单体的有机溶液，也可以将单体其本身(即单体液)作为绝缘材料。即使使用这样的绝缘材料时，也能形成绝缘层。
进一步，绝缘材料也可以是作为树脂的聚合物所溶解的有机溶液。此时，可以利用甲苯作为绝缘材料中的溶剂。

Claims (14)

1、一种电子基板的制造方法，所述电子基板在基板上搭载了电子部件，
所述制造方法具有下述工序：
在所述基板上埋入所述电子部件的工序；和
喷出含有导电性材料的液滴，形成与埋入在所述基板中的所述电子部件的外部连接电极连接的布线图案的工序。
2、根据权利要求1所述的电子基板的制造方法，其特征在于，还具有：
加热所述电子部件的工序；和
通过使已加热的所述电子部件与所述基板抵接，使所述基板软化的工序。
3、根据权利要求1所述的电子基板的制造方法，其特征在于，
所述基板由半硬化状态的树脂薄片材料形成。
4、根据权利要求3所述的电子基板的制造方法，其特征在于，还具有：
在半硬化状态的所述树脂薄片材料上形成所述布线图案之后，使所述树脂薄片材料及所述布线图案硬化的工序。
5、根据权利要求1～4中任一项所述的电子基板的制造方法，其特征在于，还具有：
喷出含有绝缘性材料的液滴，形成绝缘层的工序。
6、根据权利要求5所述的电子基板的制造方法，其特征在于，还具有：
在半硬化状态的所述基板上形成所述绝缘层之后，使所述基板及所述绝缘层硬化的工序。
7、根据权利要求5或6中所述的电子基板的制造方法，其特征在于，还具有：
通过所述液滴的喷出而形成导电柱的工序，所述导电柱贯通所述绝缘层，并与所述外部连接电极和所述布线图案连接。
8、根据权利要求5～7中任一项所述的电子基板的制造方法，其特征在于，
反复进行所述布线图案及所述绝缘层的形成工序。
9、根据权利要求8所述的电子基板的制造方法，其特征在于，还具有：
喷出含有电子元件形成材料的液滴，形成电子元件的工序。
10、一种半导体装置的制造方法，所述半导体装置在基板上搭载了半导体元件，
通过权利要求1～9中任一项所述的电子基板的制造方法，在所述基板上搭载有所述半导体元件。
11、根据权利要求10所述的半导体装置的制造方法，其特征在于，具有：
喷出含有导电性材料的液滴，形成与所述半导体元件连接的外部连接端子的工序。
12、根据权利要求11所述的半导体装置的制造方法，其特征在于，
所述外部连接端子经由贯通所述基板的贯通电极与所述半导体元件连接。
13、一种电子机器的制造方法，所述电子机器具有半导体装置，
所述半导体装置通过权利要求10～12中任一项所述的半导体装置的制造方法来制造。
14、根据权利要求13所述的电子机器的制造方法，其特征在于，具有下述工序：
在支撑所述半导体装置的框体上粘接由半硬化状态的树脂薄片材料形成的基板的工序；
在所述基板上埋入半导体元件的工序；和
形成与埋入在所述基板中的所述半导体元件的外部连接电极连接的布线图案的工序。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419261B (zh) * 2007-10-22 2011-08-24 鸿富锦精密工业（深圳）有限公司 高分辨率多媒体接口测试系统
CN101589655B (zh) * 2007-01-18 2012-11-28 琳得科株式会社 电路基板的制造方法及电路基板
CN101815401B (zh) * 2009-02-20 2012-11-28 揖斐电株式会社 线路板及其制造方法

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5164362B2 (ja) 2005-11-02 2013-03-21 キヤノン株式会社 半導体内臓基板およびその製造方法
WO2007125815A1 (ja) * 2006-04-24 2007-11-08 Nitto Denko Corporation 画像表示装置用補強シート、画像表示装置およびその補強方法
JP2008117997A (ja) * 2006-11-07 2008-05-22 Seiko Epson Corp 電子基板の製造方法
US7588951B2 (en) * 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US7696016B2 (en) * 2006-11-17 2010-04-13 Freescale Semiconductor, Inc. Method of packaging a device having a tangible element and device thereof
US7807511B2 (en) * 2006-11-17 2010-10-05 Freescale Semiconductor, Inc. Method of packaging a device having a multi-contact elastomer connector contact area and device thereof
US20080136861A1 (en) * 2006-12-11 2008-06-12 3M Innovative Properties Company Method and apparatus for printing conductive inks
JP4978883B2 (ja) * 2006-12-28 2012-07-18 Ｔｄｋ株式会社 セラミックバリスタ及び半導体内蔵モジュール並びにそれらの製造方法
US20080186690A1 (en) * 2007-02-07 2008-08-07 Nokia Corporation Electronics Package And Manufacturing Method Thereof
US20080298023A1 (en) * 2007-05-28 2008-12-04 Matsushita Electric Industrial Co., Ltd. Electronic component-containing module and manufacturing method thereof
KR100867954B1 (ko) * 2007-10-31 2008-11-11 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
US8904315B2 (en) * 2007-12-17 2014-12-02 Nokia Corporation Circuit arrangements and associated apparatus and methods
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
WO2009108136A1 (en) * 2008-02-27 2009-09-03 Agency For Science, Technology And Research Substrate cavity semiconductor package
US7772042B2 (en) * 2008-09-24 2010-08-10 Eastman Kodak Company Solvent softening to allow die placement
WO2010095208A1 (ja) * 2009-02-17 2010-08-26 株式会社 村田製作所 部品内蔵モジュール及びその製造方法
KR101060978B1 (ko) 2009-08-25 2011-08-31 전자부품연구원 능동／수동 소자 내장형 기판 제조 방법
JP5582597B2 (ja) * 2009-09-30 2014-09-03 セイコーインスツル株式会社 電子回路部品および電子機器
JP5042297B2 (ja) * 2009-12-10 2012-10-03 日東電工株式会社 半導体装置の製造方法
GB201000858D0 (en) * 2010-01-20 2010-03-10 Th Group Ltd Electronic circuit assembly
JP5724393B2 (ja) * 2011-01-11 2015-05-27 大日本印刷株式会社 通信モジュール、リーダライタ
JP6019550B2 (ja) * 2011-08-09 2016-11-02 富士通株式会社 電子装置の製造方法
US9111949B2 (en) * 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
JP5987696B2 (ja) * 2013-01-09 2016-09-07 富士通株式会社 半導体装置の製造方法
CN103200782B (zh) * 2013-04-18 2015-12-09 汕头超声印制板（二厂）有限公司 一种全喷墨印制电路板制造方法
US20160329272A1 (en) * 2014-12-19 2016-11-10 Intel IP Corporation Stacked semiconductor device package with improved interconnect bandwidth
US9818727B2 (en) 2015-03-09 2017-11-14 Mediatek Inc. Semiconductor package assembly with passive device
JP6716967B2 (ja) * 2016-03-04 2020-07-01 富士ゼロックス株式会社 半導体パッケージ及び半導体パッケージの製造方法
US11439025B2 (en) * 2016-06-08 2022-09-06 Fuji Corporation Method for forming circuit
JP6420793B2 (ja) * 2016-06-09 2018-11-07 株式会社タムラ製作所 硬化塗膜の形成方法
KR20180032985A (ko) 2016-09-23 2018-04-02 삼성전자주식회사 집적회로 패키지 및 그 제조 방법과 집적회로 패키지를 포함하는 웨어러블 디바이스
WO2018140517A1 (en) * 2017-01-26 2018-08-02 Nano-Dimension Technologies, Ltd. Chip embedded printed circuit boards and methods of fabrication
JP6987972B2 (ja) * 2018-03-28 2022-01-05 株式会社Fuji 回路形成方法、および回路形成装置
US10757813B2 (en) * 2018-10-12 2020-08-25 Advanced Semiconductor Engineering, Inc. Embedded component package structure and manufacturing method thereof
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11527627B2 (en) * 2020-01-14 2022-12-13 Diodes Incorporated Semiconductor Schottky rectifier device
CN117133518A (zh) * 2022-05-20 2023-11-28 宏启胜精密电子(秦皇岛)有限公司 内埋热敏电阻及其制造方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US73029A (en) * 1868-01-07 Improvement in velocipedes
US59987A (en) * 1866-11-27 Henry a
US82100A (en) * 1868-09-15 Improved machine foe stuffing eorse-collahs
US45379A (en) * 1864-12-06 Improved composition for coating oil-barrels
JPS5964685A (ja) * 1982-10-05 1984-04-12 Shin Etsu Polymer Co Ltd 異方導電熱接着性フイルム
CA1281114C (en) * 1985-09-25 1991-03-05 Kokichi Ito Liquid crystal electro-optical element with adhesive particles
JPS62182591A (ja) 1986-02-05 1987-08-10 石川島播磨重工業株式会社 焼結炉
JPS63138795A (ja) 1986-12-01 1988-06-10 キヤノン株式会社 プリント配線板の製造方法
JPH0369191A (ja) 1989-08-08 1991-03-25 Nec Corp 電子部品内蔵の多層プリント基板
US5290614A (en) * 1990-01-23 1994-03-01 Tomoegawa Paper Co., Ltd. Adhesive tapes for tape automated bonding
JPH04262593A (ja) * 1991-02-18 1992-09-17 Hitachi Ltd 多層配線構造体およびその製造方法とその用途
ZA941671B (en) 1993-03-11 1994-10-12 Csir Attaching an electronic circuit to a substrate.
JP3084352B2 (ja) * 1995-08-28 2000-09-04 太陽インキ製造株式会社 銅箔ラミネート方式ビルドアップ用絶縁樹脂組成物とこれを用いた多層プリント配線板の製造方法
JP2883029B2 (ja) * 1995-10-31 1999-04-19 住友ベークライト株式会社 多層プリント配線板用アンダーコート剤
TW463336B (en) * 1997-11-19 2001-11-11 Matsushita Electric Ind Co Ltd Method for planarizing circuit board and method for manufacturing semiconductor device
JP4741045B2 (ja) 1998-03-25 2011-08-03 セイコーエプソン株式会社 電気回路、その製造方法および電気回路製造装置
US6565954B2 (en) * 1998-05-14 2003-05-20 Matsushita Electric Industrial Co., Ltd. Circuit board and method of manufacturing the same
FR2780534B1 (fr) 1998-06-25 2002-08-16 Solaic Sa Procede de realisation d'objets portatifs a composants electroniques et objets portatifs tels qu'obtenus par ledit procede
TW512467B (en) * 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
JP4186756B2 (ja) 2003-08-29 2008-11-26 松下電器産業株式会社 回路基板及びその製造方法
BR0016670A (pt) 1999-12-21 2003-06-24 Plastic Logic Ltd Métodos para formar um circuito integrado e para definir um circuito eletrônico, e, dispositivo eletrônico
JP3813402B2 (ja) 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
US6844116B2 (en) * 2000-06-01 2005-01-18 Nippon Paper Industries Co., Ltd Transfer sheet for transferring protective layer for photographic emulsion face and photomask with protective layer
US6909178B2 (en) * 2000-09-06 2005-06-21 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
JP3916407B2 (ja) 2001-03-21 2007-05-16 松下電器産業株式会社 積層型電子部品実装済部品の製造方法、電子部品実装済完成品の製造方法、及び電子部品実装済完成品
JP2003101245A (ja) 2001-09-25 2003-04-04 Ind Technol Res Inst 積層回路の形成方法および形成装置
US7176055B2 (en) 2001-11-02 2007-02-13 Matsushita Electric Industrial Co., Ltd. Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
JP3925283B2 (ja) 2002-04-16 2007-06-06 セイコーエプソン株式会社 電子デバイスの製造方法、電子機器の製造方法
AU2003241784A1 (en) * 2002-05-28 2003-12-12 Matsushita Electric Works, Ltd. Material for substrate mounting optical circuit-electric circuit mixedly and substrate mounting optical circuit-electric circuit mixedly
JP4190269B2 (ja) 2002-07-09 2008-12-03 新光電気工業株式会社 素子内蔵基板製造方法およびその装置
JP2004055967A (ja) 2002-07-23 2004-02-19 Matsushita Electric Ind Co Ltd 電子部品内蔵基板の製造方法
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
CN1706040A (zh) * 2002-10-24 2005-12-07 东丽工程株式会社 非接触id卡及类似物和其制造方法
JP4489411B2 (ja) 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
US7001662B2 (en) * 2003-03-28 2006-02-21 Matsushita Electric Industrial Co., Ltd. Transfer sheet and wiring board using the same, and method of manufacturing the same
JP2005051150A (ja) * 2003-07-31 2005-02-24 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2005191027A (ja) * 2003-12-24 2005-07-14 Seiko Epson Corp 回路基板製造方法及び回路基板並びに電子機器
JP2005235964A (ja) 2004-02-19 2005-09-02 Sony Corp 部品一体型配線基板およびその製造方法
US7247529B2 (en) * 2004-08-30 2007-07-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device
JP3928638B2 (ja) * 2004-09-28 2007-06-13 セイコーエプソン株式会社 配線基板の製造方法、及び電子機器

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101589655B (zh) * 2007-01-18 2012-11-28 琳得科株式会社 电路基板的制造方法及电路基板
CN101419261B (zh) * 2007-10-22 2011-08-24 鸿富锦精密工业（深圳）有限公司 高分辨率多媒体接口测试系统
CN101815401B (zh) * 2009-02-20 2012-11-28 揖斐电株式会社 线路板及其制造方法

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