CN1841765A - 薄膜半导体器件 - Google Patents

薄膜半导体器件 Download PDF

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CN1841765A
CN1841765A CNA2006100594857A CN200610059485A CN1841765A CN 1841765 A CN1841765 A CN 1841765A CN A2006100594857 A CNA2006100594857 A CN A2006100594857A CN 200610059485 A CN200610059485 A CN 200610059485A CN 1841765 A CN1841765 A CN 1841765A
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semiconductor
thin
film
grain
film layer
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CN100468765C (zh
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松村正清
小穴保久
阿部浩之
山元良高
小关秀夫
蕨迫光纪
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Seiko Epson Corp
Advanced LCD Technologies Development Center Co Ltd
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Abstract

在本发明中，通过用辐射分布的能量束照射形成在绝缘材料基底层上的非单晶半导体薄膜层，从而使能量束的最大强度区和能量束的最小强度区以规则的方式排列，制造薄膜半导体器件的基片用作具有半导体薄膜层的基片，其中晶粒尺寸超过2μm的大尺寸单晶晶粒以规则结构的方式排列。通过调节薄膜半导体器件的每个电路单元的位置，从而对应于在基片的半导体层中的单晶晶粒的位置，形成薄膜半导体器件的每个电路单元。通过上述工艺，得到薄膜半导体器件，其中具有源电极、漏电极和栅电极的多个电路单元以对应于半导体单晶晶粒的排列以规则的结构排列。该器件能够获得高迁移率的工作，而不会受到晶粒边界处电子散射等现象的干扰。

Description

薄膜半导体器件
本申请是申请日为2002年7月10日、申请号为02802263.7、发明名称为“薄膜半导体器件及其制造方法”的发明专利申请的分案申请。
技术领域
本发明涉及薄膜半导体器件和在半导体器件中使用的半导体基片及其制造方法。
背景技术
众所周知，薄膜半导体器件或薄膜晶体管(TFT)包括替代物，其中如硅的半导体材料薄膜层形成在如无碱玻璃或石英玻璃的绝缘材料基底层上。在半导体的薄膜层中，形成由源区和漏区组成的多个沟道，每个沟道配置有栅电极。
通常，半导体的薄膜层由非晶或多晶硅组成。然而，使用包括非晶硅薄膜层的基片的TFT由于它的迁移率极低(通常，约小于1cm3/Vsec)，因此不能用于需要高速工作的器件。因此，近来，使用包括多晶硅薄膜层的基片以便增加迁移率。然而，即使使用这种基片，由于多晶薄膜由大量的极小尺寸的晶粒组成，在工作时晶粒之间界面处存在如电子散射等现象，因此迁移率提高受到限制。
由此，现已尝试通过使多晶硅的尺寸变大避免如电子散射等缺点得到具有能够增加迁移率的薄膜层的基片。例如，现已尝试通过在高温炉中退火多晶硅层得到具有约1μm尺寸并具有约100cm3/V sec迁移率的薄膜层。然而，以上工艺存在以下不足之处：不能使用如钠玻璃等的便宜玻璃，由于工艺需要如超过1000℃的极高温度退火，因此必须使用能承受高温的昂贵石英玻璃片。就成本而言，使用这种昂贵材料的基片不适合于制造大尺寸荧光屏的器件。
还提出了一些其它尝试代替使用高温退火，借助受激准分子激光器之类能量束照射非晶或多晶半导体薄膜，以便得到由大尺寸晶粒的多晶半导体组成的薄膜。通过该方法，使用便宜的玻璃片作为基底层可以增加晶粒的尺寸。
然而，即使是使用受激准分子激光器照射的方法，得到的晶粒尺寸也不超过1μm，并且不可避免地晶粒尺寸变得不均匀。例如，在JPA2001-127301的说明书中，介绍了一种得到具有大尺寸晶粒的多晶半导体薄膜层的技术，包括以下步骤；也就是，例如，利用使用受激准分子激光器通过熔化再结晶法使非晶硅薄膜多晶化，然后在再结晶层上放置非晶硅薄层，并通过固相生长法使全部层结晶，由此使原始多晶粒生长为大尺寸晶粒。然而，在以上技术中，得到的晶粒最大尺寸约1000nm(1μm)并且尺寸不均匀(参考以上说明书中的图2到5)。
此外，存在晶粒的排列方式的重要问题。在以上技术制造的多晶半导体薄膜层中，在二维方向上晶粒的排列方式完全是无规则的。现在还没有使晶粒的这种排列变成规则方式的尝试。但是，晶粒的无规则排列产生严重的不利之处。
也就是，不必说在薄膜半导体器件中形成的许多晶体管电路单元以规则的方式例如如几何排列方式排列。因此，当晶粒的尺寸不均匀并且它的排列在薄膜层中无规则(不规律)时，一个晶体管的单元电路不可避免地设置成这样的方式，即延伸到不同尺寸和位置的多个晶粒(参考图6)。这会带来每个单元电路的迁移率和电子转移方式相互不同的结果，这对器件质量带来了不良影响。由此，当每个单元电路的特性相互不同时，器件只能在低级特性的基础上整体设计。这是一个需要解决的重要问题。
发明内容
本发明的一个目的是提供一种薄膜半导体器件，其中多个电路单元根据晶粒的排列方式排列，而不是象传统工艺那样，电路单元的排列方式是延伸在晶粒尺寸和排列方式不均匀的多个晶粒上，并提供一种用于制造这种薄膜半导体器件使用的基片，此外还提供一种制造这种器件或基片的方法。
因此，在本发明的薄膜半导体器件中使用的基片中，单晶半导体晶粒以规则的排列方式例如以基本上几何排列方式排列，例如类晶格方式或矩阵阵列方式。
由此，本发明用于薄膜半导体器件的基片包括：绝缘材料的基底层和在基底层上形成的半导体薄膜层，该基片的特征在于：多个单晶半导体晶粒按照排列的方式形成在半导体薄膜层中，其中所述单晶半导体晶粒排列成二维规则结构，使得每个单晶晶粒与紧邻的单晶晶粒相邻，其间插入在晶粒之间形成的边界区，并且每个所述单晶半导体晶粒的晶粒尺寸至少为2μm。
本发明的薄膜半导体器件包括：绝缘材料的基底层和在基底层上形成的半导体薄膜层，该器件的特征在于：多个单晶半导体晶粒按照排列的方式形成在半导体薄膜层中，其中所述单晶半导体晶粒排列成二维规则结构，使得每个单晶晶粒与紧邻的单晶晶粒相邻，其间插入在晶粒之间形成的边界区，并且每个所述单晶半导体晶粒的晶粒尺寸至少为2μm并提供有具有栅电极、源电极和漏电极的电路。
本发明的薄膜半导体器件包括：绝缘材料的基底层和在基底层上形成的半导体薄膜层，该器件的特征在于：多个单晶半导体晶粒按照排列的方式形成在半导体薄膜层中，其中所述单晶半导体晶粒排列成二维规则结构，使得每个单晶晶粒与紧邻的单晶晶粒相邻，其间插入在晶粒之间形成的边界区，每个所述单晶半导体晶粒的晶粒尺寸至少为2μm，并且按照CMOS类型的方式在所述多个晶粒上设置电路。
根据本发明用于薄膜半导体器件的基片的制造方法包括以下步骤：即，(a)在绝缘材料的基底层上形成非晶或多晶半导体之类的非单晶半导体的半导体薄膜层，以及(b)通过用能量束照射使所述非单晶半导体结晶或再结晶，以制造出多个单晶半导体晶粒，进行所述照射使得给予最大照射强度的照射点和给予最小照射强度的照射点以规则的结构排列。
在本发明的薄膜半导体器件的制造方法中，根据半导体的薄膜层中单晶晶粒的排列方式，多个电路形成在上述的工艺制成的基片上。由此，本发明的薄膜半导体器件的制造方法包括：通过上述工艺制造薄膜半导体的基片的步骤，形成栅电极以使它的位置对应于在基片的半导体薄膜层中形成的单晶晶粒的排列方式的步骤，以及通过形成源电极和漏电极在每个单晶晶粒上形成多个电路单元的步骤。
由于电路单元的这种规则排列，即每个具有源电极、漏电极和栅电极的电路单元排列在半导体的薄膜中形成的每个晶粒的位置处，因此根据本发明的薄膜半导体器件能够获得高迁移率的工作，同时在工作时不会受到晶粒边界处电子散射的干扰。
由于对非单晶半导体薄膜层进行能量束的照射，使得给予最大照射强度的照射点和给予最小照射强度的照射点在空间方向上规则地排列，因此根据本发明的薄膜半导体器件的基片的制造方法可以得到多个大尺寸晶粒(例如具有大于2μm晶粒尺寸)形成在半导体薄膜层中的薄膜半导体器件基片。
由于使用多个大尺寸单晶半导体晶粒以规则的排列方式形成的基片，并且由于具有源电极、漏电极和栅电极的每个电路单元形成在每个单晶晶粒的位置，因此薄膜半导体器件的制造方法可以得到具有高迁移率并且不存在由电子散射造成缺陷的薄膜半导体器件。
附图说明
图1示出了根据本发明制造薄膜半导体器件的工艺的一个实施例的步骤图。
图2示出了根据本发明的工艺在照射步骤中在二维方向上能量束强度的分布状态的一个实施例的图形。
图3示出了根据本发明的工艺能量束强度在最大值和最小值之间变化的轮廓图。
图4示出了根据本发明的工艺中完成照射能量束之后，单晶晶粒对准状态的图形。
图5示出了在本发明的薄膜半导体器件中电极与晶粒位置关系的各实施例的图形。
图6示出了在薄膜半导体器件中电极与晶粒的位置关系的图形。
图7示出了例如图2到4中提到的最大强度照射点和最小强度照射点的结构图形的三维模型图。
具体实施方式
在本发明的薄膜半导体器件中，优选使用应变点不超过700℃的玻璃片作为基片的基底层的材料。但是，可以使用除玻璃之外的各种绝缘材料，例如具有适当热阻的陶瓷或塑料膜。
在以上基底层中，形成半导体薄膜，其中以规则排列方式例如矩阵阵列方式排列单晶半导体晶粒。通过将非单晶特性的半导体层淀积在基底层上，然后借助照射如受激准分子激光器等的能量束将淀积的层改变为包括大尺寸晶粒的多晶半导体层，进行薄膜层的形成。
对于单晶特性的半导体层，可以使用由小尺寸多晶晶粒组成的非晶半导体或多晶半导体。通过根据本发明的工艺，通过结晶或再结晶，任何类型的以上半导体可以转变为本发明的薄膜半导体。希望半导体薄膜层的厚度为10到200nm，特别是50到150nm。
通常，当以上非单晶特性的半导体层形成在基底层上时，由如氧化硅、氮化硅(SiNx)等这种材料组成用于调节热传导和结晶取向的薄控制层形成在基底层和半导体层之间。这种层具有阻止如玻璃成分等杂质从基底层扩散到半导体层并使用于控制晶体取向的半导体层的热分布有意地均匀。希望它的厚度为20到1000nm，特别是200到300nm。
也可以在以上的非单晶半导体层(第一控制层)上形成用于调节热传导和进一步结晶的第二控制层。这种第二控制层具有与第一控制层相同的功能，即，通过照射在结晶的工艺中，使热分布均匀并控制半导体层中的晶体取向。因此可以使用如氧化硅、氮化硅、氮氧化硅或碳化硅(SiC)等的材料。希望层的厚度为50到500nm，特别是100到300nm。
当形成以上两个控制层时，在两个控制层之间形成半导体薄膜层。此时，首先淀积第一控制层的材料作为绝缘材料的基底层上的薄膜，然后非单晶半导体薄膜材料淀积在第一控制层上，此外，第二控制层的材料淀积在以上半导体层上。此后，进行来自上面的能量束照射以结晶非单晶材料层。
现在参考图1a到1d，图1a到1d示出了根据本发明工艺的每个阶段的一个实施例。图1a示出了淀积层的第一阶段，其中用于调节热传导和结晶的第一控制层20淀积在基底层10上，并且非晶或多晶半导体的非单晶层30淀积在第一控制层20上。此外，第二控制层40淀积在非单晶层30上。
如图1b所示，通过能量束的照射，图1a所示的非单晶层30转变为由单晶区50和非晶区51组成的层。当然图1b示出了本发明的一个单晶区和基片由多个这种单晶半导体区组成的剖面图形。
接下来，如图1c所示，栅电极60形成在基片上，使用栅电极60作为注入掩模，注入如磷离子，在单晶半导体区50中形成源区70和漏区71。
此外，如图1d所示，如氧化硅等材料的绝缘层80淀积在第二控制层40上，穿过第二控制层40和绝缘层80形成接触孔之后，通过将铝(Al)淀积到接触孔内并构图形成源电极90和漏电极91，由此完成了薄膜半导体器件。
在以上图1b的步骤中，优选使用受激准分子激光器照射作为照射装置。然而，可以使用除受激准分子激光器之外的其它照射装置，例如脉冲调制的氩激光器或YAG激光器。
为了得到其中通过照射激光射束单晶半导体晶粒以规则的对准方式例如矩阵阵列结构方式排列的半导体薄膜层，以下面的能量强度分布方式进行照射：其中照射能量强度以预定的间隔在最大值和最小值之间在二维方向上连续地改变，最大点和最小点一个接一个地依次出现。换句话说，进行照射以便给予最大照射强度的照射点和给予了最小照射强度的照射点以规则的结构例如矩阵阵列的结构方式排列。
例如，如图2，3和7所示，在强度分布方式中进行照射，其中照射能量在5×5mm的矩形区域“(Emax)”区域中以10μm的间隔两维地(在x，y两个方向中)重复“最大值(Emax)→最小值(Emin)”的这种变化。使用相移掩模，通过照射能量强度的分布变化实现照射能量强度的以上变化。此外，希望最大值和最小值之间的变化方式为图3所示基本上连续的变化。
根据非晶半导体层的膜厚度以及第一和第二控制层的膜厚度和热导率确定最大值和最小值的级别。例如，最小能量强度可以确定为产生照射期间不会熔化薄膜半导体的温度的强度，最大值可以确定为在照射期间需要并足以熔化薄膜半导体的强度。熔化阈值级别(Emth)应存在于最大值(Emax)和最小值(Emin)之间，如图3所示。
当然照射束的面形状不限于以上提到的5×5mm的正方形，可以是各种多边形。此外，最大值点和最小值点的排列方式不限于矩形晶格方式并且可以是各种形状方式，例如三角形晶格。
通过将能量束照射到薄膜半导体，照射最小能量强度(即，小于熔化阈值的强度)的区域没有完全熔化，因此，晶核首先形成在该区域中。然后，晶体变为在朝Emax点的两维方向中生长，如图4中提到的箭头所示。另一方面，在温度变成最高的最大能量强度点的区域中，以及变为晶体生长区的区域中，由于具有不同生长方向的生长晶体的相互干扰，形成了最小尺寸或细微尺寸晶体或大尺寸晶体的边界。由此，可以得到包括多个单晶半导体的薄半导体的基片，形成在熔化阈值点附近的区域，每个单晶半导体具有超过4μm的晶体尺寸(参考图4)。
通过改变最大点照射能量之间的间隔可以调节单晶的尺寸。例如，当通过使最大强度点之间的间隔设置为12μm进行308nm波长的XeCl受激准分子激光器的照射时，可以得到其中约5μm尺寸的单晶粒规则排列的薄膜半导体的基片。希望对于本发明的薄膜半导体器件使用的基片，基片中每个单晶晶粒的尺寸不小于2μm。
然后，在通过以上提到的工艺中得到的薄膜半导体基片中的每个单晶晶粒上，淀积适当厚度(例如，300nm)的电极材料例如钼-钨合金(MoW)，由此形成栅电极。然后，使用栅电极作为注入掩模分别形成源区和漏区之后，用如氧化硅等的绝缘材料形成覆盖栅电极的层间隔离层。此外，在源区和漏区之上的位置穿透第二控制层形成接触孔之后，淀积如铝/钼等的电极材料并在接触孔中构图。
由此，如图5a和5b所示，可以得到其中每个单晶的单元电路规则排列的薄膜半导体器件。这种类型的薄膜半导体器件可以具有高迁移率(例如，超过300cm3/V sec)，超过了其中使用包括多晶半导体膜的基片的常规器件的迁移率。
可以省略设置用于一些单晶的电极或设置用于一个单晶的多个电路单元。此外，虽然以上说明基于N沟道型的薄膜晶体管的制造，然而通过进行一个接一个地部分掩模和掺杂杂质，可以将本发明的技术应用于CMOS型晶体管。也可以代替使用第二控制层作为栅绝缘体，形成单晶层之后通过腐蚀除去第二控制层，在除去的部分形成新栅极绝缘层。当在相邻的晶体管之间发生电流泄漏时，在结晶工艺之前或之后通过使用腐蚀法进行“岛分离”。
(例子)
制备由Corning Glass Works制造的无碱玻璃作为基底层，外尺寸为400×500mm，厚度为0.7mm，应变点为650℃。在基底层的表面上，用等离子体CVD法通过淀积氧化硅(SiO2)形成用于调节热传导和结晶200nm厚度的第一控制层。在第一控制层上，淀积50nm厚度的非晶硅层，此外200nm厚度氧化硅的第二控制层淀积在非晶硅层上。在不暴露到大气的条件中连续地进行材料淀积形成这些层。
接下来，退火和脱水非晶硅层之后，通过从上侧照射308nm波长的脉冲受激准分子激光器使其结晶。
通过使用受激准分子激光器的单元进行照射，其中通过使用相移掩模使束面成形以具有5×5mm的矩形并给予强度分布。强度分布的方式为25万个最大值点以正方形晶格10μm的间隔排列在5×5mm的矩形中。熔化阈值约0.5J/cm2，激光束强度的最大值和最小值分别为1.8J/cm2和0.1J/cm2。
通过以5mm的间隔逐步朝照射位置移动，朝要照射的整个表面进行以上方式的受激准分子激光器照射。
完成照射之后，通过使用SECCO腐蚀法对照射样品进行腐蚀处理并观察晶体尺寸和照射的层中晶粒边界的形状。使用电子显微镜观察的结果，可以证实得到了约4μm尺寸的单晶晶粒以矩阵晶格排列的基片。
接下来，在第二控制层上，对应于每个晶体的位置处，通过溅射法淀积300nm厚的钼-钨合金(MoW)并构图形成栅电极。然后，使用栅电极做掩模通过注入磷离子形成源区和漏区，通过等离子体CVD法通过淀积氧化硅形成层间绝缘体。此外，在第二控制层和层间绝缘体中形成接触孔，完成了薄膜半导体器件。可以证实该器件显示出496cm3/V sec的平均迁移率。

Claims (5)

1.一种用于薄膜半导体器件的基片，包括绝缘材料的基底层和在基底层上形成的半导体薄膜层，该基片的特征在于：多个单晶半导体晶粒按照排列的方式形成在半导体薄膜层中，其中所述单晶半导体晶粒排列成二维规则结构，使得每个单晶晶粒与紧邻的单晶晶粒相邻，其间插入在晶粒之间形成的边界区，并且每个所述单晶半导体晶粒的晶粒尺寸至少为2μm。
2.根据权利要求1的基片，其中在基底层和半导体薄膜层之间形成用于热传导和结晶的控制层。
3.根据权利要求1或2的基片，其中在半导体薄膜层上形成用于热传导和结晶的控制层。
4.一种薄膜半导体器件，包括绝缘材料的基底层和在基底层上形成的半导体薄膜层，该器件的特征在于：多个单晶半导体晶粒按照排列的方式形成在半导体薄膜层中，其中所述单晶半导体晶粒排列成二维规则结构，使得每个单晶晶粒与紧邻的单晶晶粒相邻，其间插入在晶粒之间形成的边界区，并且每个所述单晶半导体晶粒的晶粒尺寸至少为2μm并提供有具有栅电极、源电极和漏电极的电路。
5.一种薄膜半导体器件，包括绝缘材料的基底层和在基底层上形成的半导体薄膜层，该器件的特征在于：多个单晶半导体晶粒按照排列的方式形成在半导体薄膜层中，其中所述单晶半导体晶粒排列成二维规则结构，使得每个单晶晶粒与紧邻的单晶晶粒相邻，其间插入在晶粒之间形成的边界区，每个所述单晶半导体晶粒的晶粒尺寸至少为2μm，并且按照CMOS类型的方式在所述多个晶粒上设置电路。
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