CN1728353A - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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Publication number
CN1728353A
CN1728353A CNA2005100836419A CN200510083641A CN1728353A CN 1728353 A CN1728353 A CN 1728353A CN A2005100836419 A CNA2005100836419 A CN A2005100836419A CN 200510083641 A CN200510083641 A CN 200510083641A CN 1728353 A CN1728353 A CN 1728353A
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China
Prior art keywords
hole
wiring layer
circuit arrangement
manufacture method
insulating barrier
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CNA2005100836419A
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CN100444342C (zh
Inventor
高草木贞道
五十岚优助
根津元一
草部隆也
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种可靠性高的电路装置的制造方法，实现了电路装置的小型化、薄型化及轻量化。本发明电路装置的制造方法，在支承衬底(11)的上面形成构成电路装置的树脂密封体(31)后，使树脂密封体(31)从支承衬底(11)分离。因此，可制造没有衬底的电路装置。由此，可实现电路装置的薄型化、小型化、轻量化及散热性的提高。另外，由于可在支承衬底(11)上利用密封树脂(28)进行密封，故可防止密封树脂(28)和导电图形(20)、及密封树脂(28)和电路元件(25)的热膨胀系数之差造成的挠曲。因此，由于可抑止导电图形(20)的剥离或导电图形(20)和金属细线(27)的连接不良，故可制造可靠性高的电路装置(10A)。

Description

电路装置的制造方法
技术领域
本发明涉及电路装置的制造方法，特别是涉及实现薄型电路装置的电路装置的制造方法。
背景技术
伴随电子设备的小型化及高功能化，在其内部使用的电路装置中，也要求小型化及高密度化。参照图9说明现有的电路装置的制造方法之一例(参照专利文献1)。
首先，参照图9(A)，在由树脂等绝缘性材料构成的衬底101上利用激光等形成接触孔103。然后，在含有接触孔103内部的衬底101的两面形成镀敷膜102。
其次，参照图9(B)，通过蚀刻镀敷膜102，在衬底101的表面形成第一导电图形102A，在背面形成第二导电图形102B。
参照图9(C)，在第一导电图形102A上载置半导体元件104，通过金属细线105将第一导电图形102A和半导体元件104电连接。然后，用密封树脂107密封，使其覆盖半导体元件104、金属细线105及第一导电图形102A。最后，用抗焊剂109覆盖第二导电图形102B，在规定的位置形成外部电极108。这样，制造电路装置100。
专利文献1：特开2002-26198号公报
但是，在上述的电路装置的制造方法中，在衬底101上使用玻璃环氧树脂衬底，在制造过程中，为支承布线而使用。因此，制造成本的上升、或衬底101的厚度限制电路装置的小型化、薄型化、轻量化成为了问题。并且，还指出使用玻璃环氧树脂衬底造成散热性恶化。
在使密封树脂107固化时，由于衬底101和密封树脂107及、半导体元件104和密封树脂107的热膨胀系数差而产生了挠曲。由此，存在导电图形102从衬底101剥离、或第一导电图形102B和金属细线105的连接产生不良等问题。
在衬底101上采用玻璃环氧树脂衬底时，需要形成用于电连接两面的电极的接触孔103，存在制造工序长的问题。
另外，在形成大电流流动的导电图形时，通过增大导电图形的面积，确保该电气容量。因此，难于使电路装置小型化。
发明内容
本发明是鉴于上述问题而形成的。本发明的主要目的在于，提供一种可靠性高的电路装置的制造方法，实现电路装置的小型化、薄型化及轻量化。
本发明提供一种电路装置的制造方法，其包括：在支承衬底的表面形成由第一导电图形和形成地比所述第一导电图形厚的第二导电图形构成的布线层的工序；将所述布线层和电路元件电连接的工序；由密封树脂密封所述支承衬底的上面，使其覆盖所述电路元件的工序；从所述支承衬底分离所述布线层及所述密封树脂的背面的工序。因此，由于可制造没有衬底的电路装置，故可实现制造成本的降低、或电路装置的薄型化、轻量化及散热性的提高。另外，由于可在同一电路装置内形成厚度不同的导电图形，故可通过分别形成对应要求的电流量的导电图形使电路装置小型化。
本发明提供一种电路装置的制造方法，其包括：在支承衬底表面形成具有沿厚度方向突出的凸部的对应布线层的工序；介由绝缘层使导电膜层积所述第一布线层上的工序；形成使所述凸部和所述导电膜导通的连接部的工序；通过构图所述导电膜，形成第二布线层的工序；将所述第二布线层和电路元件电连接的工序；由密封树脂密封所述支承衬底的上面，使其覆盖所述电路元件的工序；从所述支承衬底分离所述第一布线层、绝缘层及所述密封树脂的背面的工序。因此，除上述的效果之外，可进行多层布线，从而实现电路装置的高密度化。
根据本发明电路装置的制造方法，可制造没有衬底的电路装置。因此，可实现电路装置的薄型化、轻量化及散热性的提高。
根据本发明电路装置的制造方法，由于可在支承衬底上由密封树脂进行密封，故可防止密封树脂和导电箔、及密封树脂和电路元件的热膨胀系数差造成的挠曲。因此，由于可抑制导电图形的剥离或导电图形和金属细线的连接不良，故可制造可靠性高的电路装置。
根据本发明电路装置的制造方法，由于可省去在玻璃环氧树脂衬底上形成必要的接触孔，故可大幅缩减制造工序。
根据本发明电路装置的制造方法，由于可较厚地形成大电流流动的导电图形，故可使电路装置小型化。
根据本发明电路装置的制造方法，可在通过埋入凸部而在较薄地形成的绝缘层上设置通孔。因此，可容易地在绝缘层上形成通孔。另外，由于可较浅地形成通孔，故可容易地对该通孔形成镀敷膜。另外，即使在介由混入有填充物的绝缘层层积多层布线层的情况，也可以贯通所述绝缘层，形成使布线层相互导通的连接部。
附图说明
图1(A)～图1(C)是说明本发明电路装置的制造方法的剖面图；
图2(A)～图2(C)是说明本发明电路装置的制造方法的剖面图；
图3(A)～图3(C)是说明本发明电路装置的制造方法的剖面图；
图4(A)～图4(C)是说明本发明电路装置的制造方法的剖面图；
图5(A)～图5(C)是说明本发明电路装置的制造方法的剖面图；
图6(A)～图6(C)是说明本发明电路装置的制造方法的剖面图；
图7(A)～图7(C)是说明本发明电路装置的制造方法的剖面图；
图8(A)～图8(B)是说明本发明电路装置的制造方法的剖面图；和
图9(A)～(C)是说明现有的电路装置的制造方法的剖面图。
具体实施方式
第一实施方式
参照图1及图2说明第一实施方式的电路装置的制造方法。
首先，参照图1(A)，在支承衬底11上通过粘结剂12粘贴导电箔13。导电箔13考虑焊料的附着性、键合性、镀敷性来选择其材料。作为具体材料，采用以Cu为主原料的导电箔、以Al为主原料的导电箔或由Fe-Ni等合金构成的导电箔等。另外，也可以为其它导电材料，特别优选可蚀刻的导电材料。导电箔13的厚度为10μm～300μm左右。但是，也可以采用10μm以下或300μm以上的导电箔。
粘结剂12采用热塑性树脂、UV片(通过照射紫外线而使粘接性消失的物质)等。另外，粘结剂12只要是可在溶剂中溶解、加热形成液状、通过紫外线照射而使粘接性降低的材料即可。
支承衬底11由Cu、Al等金属或树脂等材料构成，具有可平坦地支承导电箔13的强度或厚度。另外，在粘结剂12采用UV片时，最好采用玻璃、或塑料等透明衬底。
参照图1(B)在导电箔13的上面构图抗蚀剂14。然后，以该抗蚀剂14为掩模，进行湿式蚀刻，进行未形成抗蚀剂14的主面的蚀刻。通过进行该蚀刻，形成凸部18和薄的导电箔两种。在该蚀刻结束后，将抗蚀剂14除去。
参照图1(C)，通过蚀刻导电箔13，形成导电图形20A、20B。首先，构图抗蚀剂14，使其覆盖导电图形形成的予定区域的上面。此时，构图抗蚀剂14，使其覆盖较厚形成的比凸部18宽的区域。这是由于要通过一次蚀刻而构图导电箔13，只要蚀刻厚度薄的部分即可。例如考虑掩模误差，进行构图，仅稍微形成边，则可完全分离导电箔13。另外，如在薄的部分进行构图，则只进行一次蚀刻。相反，如在凸部18的厚度部分进行构图，则薄的导电膜被过蚀刻，使图形宽度变窄。
这样，通过在薄的导电箔侧一次构图厚度不同的导电图形，可一次形成厚薄的图形，可通过两次蚀刻形成例如功率类的图形和小信号类的图形。
另外，加宽导电图形的面积，不能对应大电流，可通过增加导电图形的厚度来对应，可减小电路装置的平面尺寸。
通过在较厚地形成的导电图形上配置发热量大的电路元件，可提高散热性。
参照图2(A)，在导电图形20上安装电路元件25，形成由密封树脂28密封的树脂密封体31。在此，第一电路元件25A载置于第一导电图形20A上，第二电路元件25B载置于第二导电图形20B上。如该图所示，电路元件25通过金属细线27和导电图形20电连接。当然，也可以通过倒装接合法进行。
在本方式中，对载置较小的电流流动的第一电路元件25A和大电流流动的第二电路元件25B进行说明。
作为第一电路元件25A，例示有片状电容，但也可采用晶体管、LSI芯片、片状电阻或筒形线圈等。
作为第二电路元件25B，可采用流过大电流的功率类晶体管，例如功率金属氧化物晶体管、GTBT、IGBT、闸流晶体管等。另外，也可以采用功率类IC。近年来，由于芯片的尺寸减小，且薄型、高功能化，故与以前相比，产生大量的热。因此，通过将需要进行散热的电路元件也载置于第二导电图形20B上，可提高散热性。
而且，电路元件25和导电图形的连接通过正面接合法或倒装接合法由金属细线、焊料或导电膏等进行。然后，电路元件25利用密封树脂28密封。在此，可通过传递膜模制、注入膜模制、浸渍、或涂敷进行树脂密封。树脂材料可采用环氧树脂等热硬性树脂或聚酰亚胺树脂等热塑性树脂。
在此，树脂密封体31由于直至密封树脂28固化，和表面平坦的支承衬底11成为一体，故可维持其平坦性。
参照图2(B)，将树脂密封体31从支承衬底11分离。在此，在将热塑性树脂用作粘接剂12时，可通过加热热塑性树脂使其熔融进行分离。另外，也可以由有机溶剂等药剂选择地熔融粘接剂12。
在将UV片用作粘接剂12时，可通过照射紫外线进行分离。此时，通过将玻璃等使紫外线通过的材料用作支承衬底11，可进行迅速且有效的分离。
在从支承衬底11进行分离后，有可能在树脂密封体31的背面残留粘接剂12的一部分。这将通过再次使用有机溶剂等药剂熔融除去而解决。
参照图2(C)，对树脂密封体31进行背面处理，进行切割，分别进行分离，从而完成电路装置10A。在此，在树脂密封体31的背面构图抗焊料剂29，使导电图形露出，在该位置形成外部电极30，例如焊料。但是，也可以使从树脂密封体31背面露出的导电图形20作为外部电极起作用。
通过以上的结构，可形成薄的导电图形和厚的导电图形，可将功率类/小信号类的元件收纳于一个封装中。例如在将六个功率类元件和一个控制IC封装成一个作为逆变器模块时，只要将六个功率元件的源/漏与厚的导电图形电连接，将控制栅极或功率晶体管的IC与薄的导电图形电连接，即可形成由一个封装构成的SIP。
第二实施方式
参照图3～图5说明第二实施方式的电路装置的制造方法。本方式的电路装置的制造方法和第一实施方式的基本工序相同。因此，这里以不同点为中心进行说明。
首先，参照图3(A)，在支承衬底11上通过粘接剂12粘贴的第一导电膜33上形成凸部18。第一导电膜33通过以抗蚀剂14为掩模进行半腐蚀，形成作为厚的部分的凸部18和薄的部分。在形成凸部18后，除去抗蚀剂14。
参照图3(B)，和前实施方式相同，蚀刻薄的部分，形成厚的导电图形和薄的导电图形。在此，构图抗蚀剂14，使其覆盖比凸部18的区域宽的范围。然后，通过以抗蚀剂14为掩模，进行湿式蚀刻，形成由第一导电图形40A和形成地比第一导电图形40A厚的第二导电图形40B构成的第一布线层40。
参照图3(C)，通过绝缘层41在第一布线层40的上面层积第二导电膜34。这通过将在表面设有粘接层等绝缘层41的第二导电膜34和第一布线层40密封而构成。另外，也可以在将绝缘层41涂敷于第一布线层之后，层积第二导电膜34。
在此，凸部18被埋入绝缘层41这样来密封。通过由真空加压进行该密封，可防止第一绝缘层40和绝缘层41之间的空气产生的空隙。另外，使通过各向同性蚀刻形成的凸部18的侧面形成圆滑的曲面。因此，在将第一布线层40埋入绝缘层41时，沿该曲面浸入树脂，消除未填充部。由此，可通过凸部18的侧面形状抑制空隙的产生。另外，可通过将凸部18埋入绝缘层41提高第一布线层40和绝缘层41的密封强度。
在本方式中，为提高散热性，采用将填充物混入环氧树脂等绝缘性树脂中作为绝缘层41。在此，混入的填充物为SiO2、AlO3、SiC、AlN等。当然，也可以采用不向绝缘层41中混入填充物的树脂。
参照图4(A)～图4(C)说明形成使第一布线层40和第二导电膜34导通的连接部的工序。首先，以抗蚀剂14为掩模，蚀刻形成连接部43的予定区域，形成通孔42，使绝缘层41的表面露出。然后，以第二导电膜34为掩模，通过照射激光，使凸部18从通孔42的下部露出。然后，通过在通孔42中形成镀敷层，形成连接部43。通过形成连接部43，可导通第一布线层40和第二导电膜34。
参照图6～图9详细说明该连接部43的形成工序。
参照图5(A)，通过构图第二导电膜34，形成第二布线层45。在第二布线层45上电连接电路元件25后，由密封树脂28进行密封。
在此，第一布线层40和第二布线层45可平面交叉这样地形成。而且，第一布线层40和第二布线层45通过连接部43在所希望的位置连接。因此，即使在电路元件25具有多个电极的情况，也可以通过本方式的多层布线结构进行跨接，可自由地进行布线的引导。当然，也可以根据电路元件的电极数量、元件的安装密度等增加到三层、四层、五层以上。
另外，在本方式中，第二布线层45由相同厚度的图形形成，但如参照图1说明的那样，也可以形成具有厚度不同的图形的布线层。因此，通过形成厚地形成的导电图形，可确保电气容量，同时，可具有作为散热器的功能。另外，也可以将连接部43作为热通路起作用。
参照图5(B)，从支承衬底11分离树脂密封体31。该分离的方法可利用上述的方法实施。而且，通过对树脂密封体31进行背面处理，进行切割，将其个别分离，完成图5(C)所示的电路元件10B。
参照图6～图8说明连接部43的形成方法。
在图6(A)中，在第一布线层40的上面通过绝缘层来层积第二导电膜34。在此，第二导电膜34除去形成连接部43的予定的区域。从通孔42的下部露出绝缘层41的表面。另外，在绝缘层41中考虑散热性而混入有填充物。在此，首先，图6(B)及图6(C)表示虚线包围的连接部形成区域44的放大图，详细叙述通孔42的形成方法。
参照图6(B)，在本方式中，通过埋入凸部18，使通孔42下方的绝缘层41的厚度变薄。然后，通过使用激光39除去薄的区域的绝缘层41，在通孔42的下部露出凹部18的上面。在大部分的区域，绝缘层41的厚度T2例如为50μm左右。与此相对，对应通孔42下方的区域的绝缘层41的厚度T1例如薄至10μm～25μm。
在之后的工序通过镀敷形成连接部43时，需要形成低宽高比的通孔42。这是由于，当宽高比高时，通孔42内部的镀敷液的流动性恶化、或镀敷液的供给不充分，从而难于形成连接部43。
在此，由于确认可通过镀敷形成可靠性高的连接部43的通孔42的宽高比为1以下，故形成本方式的通孔42，使宽高比为1或1以下。在此，宽高比是在通孔42的直径为D、通孔42的深度为L时由L/D表示的值。
另外，当在绝缘层41中混入用于确保散热性的填充物时，利用激光形成通孔42稍微困难。在这样的情况下，减薄形成通孔42的绝缘层41是有意义的。
图6(C)表示由上述方法形成通孔42后的剖面。从通孔42的下方露出凸部18的上面。从利用激光处理形成的通孔42的侧壁露出混入绝缘层41的填充物。在本方式的绝缘层41中为提高散热性而混入有宽度宽的直径的填充物。因此，通孔42的侧壁形成具有凹凸的形状。另外，由于上述激光处理而在通孔42的底部残留残渣时，进行用于清除该残渣的清洗。
凸部18的平面的大小形成得比形成于其上方的通孔42大。换句话说，由于通孔42及凸部18的平面的形状例如为圆形，故凸部18的直径形成地比通孔42的直径大。列举一例，在通孔42的直径W1为100μm左右时，凸部18的直径W2形成150μm～200μm左右。另外，在通孔42的直径W1为30μm～50μm左右时，凸部18的直径W2调整为50μm～70μm左右。这样，通过增大凸部18的平面的大小，使其比通孔42大，即使在通孔42的位置稍有误差的情况下形成时，也可以使通孔42位于凸部18的上方。因此，可防止上述位置误差造成的连接可靠性降低。另外，作为凸部18的平面的形状，也可以采用圆形以外的形状。
另外，图中未图示，但通过由第一树脂膜和第二树脂膜形成绝缘层41，可容易地形成通孔42。具体地说，利用第一树脂膜形成绝缘层41的下层。在此，第一树脂膜的上面和凸部18的上面为相同高度。而且，在第一树脂膜的上面形成第二树脂膜。在此，第一树脂膜为充分维持散热性，而将填充物的填充率提高，将第二树脂膜的填充率降低，以可容易地通过激光形成通孔42。由此，可抑止在通孔内部填充物的残渣或从通孔42的侧面剥离的填充物造成的通孔42的堵塞。因此，可形成可靠性高的连接部。另外，也可以减小混入第二树脂膜中的填充物的直径。另外，也可以不向第二树脂膜中混入填充物。
在上述说明中，在由第二导电膜34覆盖绝缘层41后，形成通孔42，但也可以利用其它方法形成通孔42。具体地说，在覆盖第二导电膜34之前，通过除去绝缘层41形成通孔42，可从通孔42的下部使凸部18的上面露出。在此，除去树脂的方法可采用YAG激光或湿式蚀刻。而且，也可以通过进行无电解镀敷形成连接部43和第二导电膜34。通过将由无电解镀敷形成的第二导电膜34作为阴极进行电解镀敷，可形成具有某种程度的厚度的导电膜。
其次，参照图7及图8说明通过在通孔42中形成镀敷膜，形成连接部43，使第一布线层40和第二导电膜34导通的工序。该镀敷膜的形成考虑两个方法。第一个方法是在利用无电解镀敷形成镀敷膜后，利用电解镀敷再次成膜镀敷膜的方法。第二个方法是仅进行电解镀敷处理成膜镀敷膜的方法。
参照图7说明形成镀敷膜的上述第一方法。首先，参照图7(A)，在也包括通孔42侧壁的第二导电膜34的表面通过进行无电解镀敷处理形成第一镀敷膜46。该第一镀敷膜46的厚度只要为3μm～5μm左右即可。
其次，参照图7(B)，在第一镀敷膜46的上面利用电解镀敷法形成新的第二镀敷膜47。具体地说，将形成有第一镀敷膜46的第二导电膜34作为阴极电极，利用电解镀敷法形成第二镀敷膜47。利用上述的无电解镀敷法在通孔42的内壁形成第一镀敷膜46。因此，这里形成的第二镀敷膜47也包括通孔42的内壁，形成一样的厚度。这样，由镀敷膜形成连接部43。具体地第二镀敷膜47的厚度例如为20μm左右。上述的第一镀敷膜46及第二镀敷膜47的材料可采用和第二导电膜34相同的材料即铜。另外，也可以采用除铜以外的金属作为第一镀敷膜46及第二镀敷膜47的材料。
参照图7(C)，在此，通过进行加载镀敷，由第二镀敷膜47埋入通孔42。通过进行该加载镀敷，可提高连接部43的机械强度。
其次，参照图8说明使用电解镀敷法形成连接部43的方法。
参照图8(A)，首先，使含有金属离子的溶液接触通孔42。在此，镀敷膜48的材料可采用铜、金、银、钯等。而且，当将第二导电膜34作为阴极电极流过电流时，在作为阴极电极的第二导电膜34上析出金属，形成镀敷膜。在此，48A、48B表示镀敷膜生长的样态。在电解镀敷法中，在电场强的位置优先形成镀敷膜。在本方式中，该电场在面向通孔42周边部的部分的第二导电膜34上变强。因此，如该图所示，镀敷膜从面向通孔42周边部的部分的第二导电膜34优先生长。在形成的镀敷膜与凸部接触时，第一布线层40和第二导电膜34导通。然后，在通孔42内部同样形成镀敷膜。由此，在通孔42的内部形成和第二导电膜34一体化的连接部43。
下面，参照图8(B)说明形成连接部43的其它方法。在此，通过在通孔42的周边部设置遮檐50，从而容易地通过电解镀敷法形成连接部43。在此，“遮檐”是由覆盖通孔42周边部这样地突出的第二导电膜34构成的部位。遮檐50的具体的制造方法可通过在利用激光形成通孔42时，增大该激光的输出进行。通过增大激光的输出，使激光进行的第二导电膜34的除去横方向前进，除去遮檐50下方区域的树脂。通过利用上述的条件进行以第二导电膜34为阴极电极的电解镀敷处理，从遮檐50的部分优先生长镀敷膜。通过从遮檐50生长镀敷膜，和图8(A)的情况比较，可沿下方向优先生长镀敷膜。因此，可由镀敷膜准确地进行通孔42的埋入。
如上所述，本方式的通孔42的侧壁形成具有凹凸的形状。另外，在通孔42的侧壁露出混入绝缘层41的填充物。由此，难于在通孔42的侧壁形成镀敷膜。通常，难于在作为无机填充物的填充物表面粘附镀敷膜。特别是在通孔42的侧壁露出AlN时，难于形成镀敷膜。因此，在本方式中，可通过使用上述电解镀敷法的方法形成连接部43。
另外，即使在通过进行加载镀敷埋入通孔42的情况，如上所述，由于较浅地形成通孔42，故也可以容易地进行加载镀敷。
在本方式中，使上述凸部18和连接部43接触的位置位于绝缘层41的厚度方向中间部。在此，中间部是指第一布线层40上面的上方，即第二布线层45下面的下方。因此，在纸面上，凸部18和连接部43接触的位置成为绝缘层41厚度方向的中央部附近。而且，该位置可在上述的中间部的范围内变化。在考虑通过镀敷处理形成连接部43时，凸部18和连接部43接触的部分优选配置于第一布线层40的上面和第二布线层45的下面之间的其中间位置上方。由此，具有容易地形成由镀敷膜构成的连接部43的优点。即，为形成连接部43，而形成通孔42，但可较浅地形成该通孔42的深度。另外，也可以以浅的量将通孔42的直径减小。另外，也可以以通孔42的直径小的量将通孔42的间隔减窄。因此，可在整体上实现微细的图形，可将电路装置小型化。

Claims (8)

1、一种电路装置的制造方法，其特征在于，包括：
在支承衬底的表面形成由第一导电图形和形成地比所述第一导电图形厚的第二导电图形构成的布线层的工序；
将所述布线层和电路元件电连接的工序；
由密封树脂密封所述支承衬底的上面，使其覆盖所述电路元件的工序；
以及从所述支承衬底分离所述布线层及所述密封树脂的背面的工序。
2、一种电路装置的制造方法，其特征在于，包括：
在支承衬底表面形成具有沿厚度方向突出的凸部的第一布线层的工序；
介由绝缘层使导电膜层积在所述第一布线层上的工序；
形成使所述凸部和所述导电膜导通的连接部的工序；
通过构图所述导电膜，形成第二布线层的工序；
将所述第二布线层和电路元件电连接的工序；
由密封树脂密封所述支承衬底的上面，使其覆盖所述电路元件的工序；以及
从所述支承衬底分离所述第一布线层、绝缘层及所述密封树脂的背面的工序。
3、如权利要求2所述的电路装置的制造方法，其特征在于，所述连接部如下形成，部分地除去所述导电膜，使所述绝缘层露出，通过除去露出的所述绝缘层，形成通孔，在所述通孔中形成镀敷膜。
4、如权利要求3所述的电路装置的制造方法，其特征在于，所述镀敷膜如下形成，在通过无电解镀敷处理在所述通孔的侧壁形成镀敷膜后，进行电解镀敷处理，在所述通孔中形成新的镀敷膜。
5、如权利要求3所述的电路装置的制造方法，其特征在于，所述镀敷膜通过进行将所述导电膜作为电极使用的电解镀敷处理，从位于所述通孔周边部的所述导电膜形成到所述通孔的内侧。
6、如权利要求5所述的电路装置的制造方法，其特征在于，在所述通孔的周边部形成由所述导电膜构成的遮檐，从所述遮檐到所述通孔的内侧形成镀敷膜。
7、如权利要求2所述的电路装置的制造方法，其特征在于，在所述绝缘层中混入有填充物。
8、如权利要求1或权利要求2所述的电路装置的制造方法，其特征在于，所述支承衬底和所述第一布线层利用粘接剂粘贴，在使所述粘接剂的粘接力降低后，将所述第一布线层、所述绝缘层及所述密封树脂的背面从所述支承衬底分离。
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CN109788665B (zh) * 2017-11-14 2020-07-31 何崇文 含电子元件的线路基板及其制作方法
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US7163841B2 (en) 2007-01-16
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