CN1705106A - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
- Publication number
- CN1705106A CN1705106A CNA2005100747171A CN200510074717A CN1705106A CN 1705106 A CN1705106 A CN 1705106A CN A2005100747171 A CNA2005100747171 A CN A2005100747171A CN 200510074717 A CN200510074717 A CN 200510074717A CN 1705106 A CN1705106 A CN 1705106A
- Authority
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- China
- Prior art keywords
- hole
- insulating barrier
- connecting portion
- resin molding
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
一种电路装置及其制造方法,可容易地形成将配线层相互连接的连接部。本发明混合集成电路装置(10)的制造方法中,形成第一树脂膜(17B1),使其覆盖第一配线层(18A)。然后,贯通第一树脂膜(17B1),形成使第一配线层(18A)从底部露出的第一通孔。然后,形成第二树脂膜(17B2),使其埋入第一通孔(32A)中。在填充于第一通孔(32A)的第二树脂膜(17B)上形成第二通孔(32B),形成连接部(25)。
Description
技术领域
本发明涉及电路装置及其制造方法,特别是涉及具有介由绝缘层层积的多个配线层的电路装置及其制造方法。
背景技术
参照图15说明现有的混合集成电路装置100的结构(例如参照专利文献1)。图15(A)是混合集成电路装置100的立体图,图15(B)是图15(A)的X-X’线的剖面图。
现有的混合集成电路装置100具有矩形衬底106和设于衬底106表面的绝缘层107,在该绝缘层107上对配线层108进行构图。另外,在配线层108上固定有电路元件104,电路元件104和配线层108利用金属细线105电连接。与配线层108电连接的引线101导出外部。另外,混合集成电路装置100整体被密封树脂102密封。作为利用密封树脂102密封的方法,具有使用热塑性树脂的注射成型(injection mold)和使用热硬性树脂的传递成型(transfermold)。
专利文献1:特开平6-177295号公报
但是,在上述的混合集成电路装置100中,由于形成单层的配线,故可集成的电路的规模有限。作为解决该问题的方法之一,有形成介由绝缘层层积的多层配线结构的方法。具体地说,通过介由绝缘层层积大于或等于两层的配线层,形成多层的配线结构。
为了形成上述多层的配线结构,需要形成贯通绝缘层来连接各配线层的连接部。但是,为了提高散热性,而在绝缘层中混入有大量的无机填充物。因此,当使用激光在绝缘层上形成通孔时,在该通孔的侧壁无机填充物露出而形成凹凸。由于难以在这种状态的通孔中形成镀敷膜,故不容易形成上述的连接部。
发明内容
本发明是鉴于上述的问题而形成的。本发明的主要目的在于,提供一种电路装置及其制造方法,可容易地形成将配线层相互连接的连接部。
本发明提供一种电路装置,其特征在于,包括:多个配线层,其介由含有填充物的绝缘层层积而成;连接部,其沿厚度方向贯通所述绝缘层,在所希望的位置将所述配线层相互之间电连接。将所述连接部设置在覆盖设于所述绝缘层的通孔侧壁的绝缘性树脂的内部,所述绝缘性树脂比所述绝缘层的所述填充物的含有量少。
本发明提供一种电路装置,其特征在于,具有介由含填充物的绝缘层层积的多个配线层,所述配线层相互之间介由沿厚度方向贯通所述绝缘层的连接部在所希望的位置电连接,所述绝缘层由含有填充物的第一树脂膜和层积于所述第一树脂膜,比所述第一树脂膜的填充物的含有量少的第二树脂膜构成,设置沿厚度方向贯通所述第一树脂膜的通孔,在覆盖所述通孔侧壁的所述第二树脂膜内部设置所述连接部。
本发明提供一种介由含填充物的绝缘层层积多个配线的电路装置的制造方法,其特征在于,包括:形成沿厚度方向贯通所述绝缘层的第一通孔的工序;将填充物的含有量少于所述绝缘层的绝缘性树脂埋设在所述第一通孔内的工序;在所述绝缘性树脂上形成平面大小比所述第一通孔小的第二通孔的工序;在所述第二通孔中设置使所述配线层相互之间导通的连接部的工序。
另外,本发明提供一种电路装置的制造方法,其特征在于,包括:在电路衬底表面形成第一配线层的工序;在所述电路衬底表面设置混入有填充物的第一树脂膜,以覆盖所述第一配线层的工序;通过形成沿厚度方向贯通所述第一树脂膜的第一通孔,使所述第一配线层从所述第一通孔底部露出的工序;在所述第一树脂膜的表面形成填充量少于所述第一树脂膜的第二树脂膜,使其填充在所述第一通孔中的工序;在所述第二树脂膜的表面层积第二导电膜的工序;通过除去填充于所述第一通孔的所述第二树脂膜及其上方的所述第二导电膜,形成比所述第一通孔小的第二通孔,使所述第一配线层从所述第一通孔底部露出的工序;在所述第二通孔中设置使所述第一配线层和所述第二导电膜导通的连接部的工序;通过对所述第二导电膜进行构图,形成第二配线层的工序。
根据本发明的电路装置,利用绝缘性树脂或第二树脂膜覆盖通孔侧壁,在其内部设置将多层配线层相互连接的连接部。因此,利用填充物的含有量少的绝缘性树脂或第二树脂膜缓和应力,可提高连接部的连接可靠性。
根据本发明电路装置的制造方法,在形成于绝缘层的第一通孔中埋设绝缘性树脂,在该绝缘性树脂上重新形成的第二通孔中形成连接部。因此,由于在填充物的含有量少的第二通孔中形成连接部,故可容易地进行连接部的形成。该连接部的形成可通过镀敷膜的成膜等进行。
根据本发明电路装置的制造方法,由第一树脂膜和比该第一树脂膜的填充物的填充量少的第二树脂膜形成绝缘层。在第一树脂膜上设置第一通孔,将第二树脂膜涂敷于第一树脂膜的表面,使其填充该第一通孔。另外,在填充于第一通孔的第二树脂膜上设置第二通孔,在该第二通孔中形成连接部。因此,由于第二树脂膜的填充物的含有量少,故可容易地进行通孔的形成。
附图说明
图1(A)-(C)是说明本发明的混合集成电路装置的剖面图;
图2是说明本发明的混合集成电路装置的立体图;
图3(A)-(B)是说明本发明的混合集成电路装置的剖面图;
图4(A)-(B)是说明本发明的混合集成电路装置的剖面图;
图5(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图6(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图7(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图8(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图9(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图10(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图11(A)-(B)是说明本发明的混合集成电路装置的制造方法的剖面图;
图12(A)-(C)是说明本发明的混合集成电路装置的制造方法的剖面图;
图13(A)-(B)是说明本发明的混合集成电路装置的制造方法的剖面图;
图14是说明本发明的混合集成电路装置的制造方法的剖面图;
图15(A)是说明现有的混合集成电路装置的立体图,图15(B)是剖面图。
具体实施方式
第一实施例
在本形态中,作为电路装置之一例,以图1等所示的混合集成电路装置为例进行说明。但是,下述的实施方式也可以适用于其它种类的电路装置。
参照图1说明本发明的混合集成电路装置10的结构。图1(A)是混合集成电路装置10的剖面图,图1(B)是将连接部25附近放大表示的剖面图。图1(C)是表示连接部25的其它例的剖面图。
在混合集成电路装置10中,参照图1(A),在作为支承衬底起作用的电路衬底16表面形成有由配线层18及电路元件14构成的电路。另外,形成于电路衬底16表面的电路被密封树脂12密封。在电路衬底16的周边部,引线11被固定在最上层的配线层18上,引线11的端部从密封树脂12导出外部。在本实施例中,配线层18具有多层配线结构,在此,实现由第一配线层18A及第二配线层18B构成的两层配线结构。各配线层18介由绝缘层层积。下面详细说明具有这种概略结构的混合集成电路装置10。
电路衬底16由金属或陶瓷等构成,从散热的意义上来说是理想的。另外,作为电路衬底16的材料,作为金属可采用Al、Cu或Fe等,作为陶瓷可采用Al2O3、AlN。除此之外,也可以采用机械强度和散热性优良的材料作为电路衬底16的材料。在本实施例中,在由铝构成的电路衬底16的表面形成第一绝缘层17A,并在其表面形成配线层18。另外,在本实施例中,适当采用以铜为主体的金属作为电路衬底16的材料。由于铜是热传导性优良的材料,故可提高装置整体的散热性。另外,在采用Al作为电路衬底16的材料时,也可以在电路衬底16的表面形成氧化膜。另外,在采用Al时,考虑机械强度,也可以在表面形成氧化铝。
第一绝缘层17A在电路衬底16的表面形成,覆盖电路衬底16的实际上整个区域。第一绝缘层17A可采用填充有填充物的树脂。在此,填充物例如可采用铝化合物、钙化合物、钾化合物、镁化合物或硅化合物。另外,为提高装置整体的散热性,而在第一绝缘层17A中含有比其它绝缘层量多的填充物,其重量填充率例如为60%~80%左右。另外,通过在第一绝缘层17A中混入直径大于或等于50μm的大径填充物,也可以提高散热性。第一绝缘层17A的厚度根据要求的耐压而变化,优选约50μm~数百μm程度。
第一配线层18A由铜等金属构成,在第一绝缘层17A表面进行构图。该第一配线层18A和上层的第二配线层18B电连接,主要具有引绕布置布线图案的功能。
第二绝缘层17B在电路衬底16表面形成,覆盖第一配线层18A。而且,在第二绝缘层17B上,电连接第一配线层18A和第二配线层18B的连接部25贯通形成。因此,第二绝缘层17B为了容易形成连接部25,可混入比第一绝缘层17A的填充物少的填充物。根据相同的理由,第二绝缘层17B中含有的填充物的平均粒径可以比第一绝缘层17A中含有的填充物的平均粒径小。在本实施例中,第二绝缘层17B由第一树脂膜17B1和在其上面形成的第二树脂膜17B2构成。后面详细叙述。
第二配线层18B形成于第二绝缘层17B的表面。第二配线层18B形成载置半导体元件14A等电路元件14的焊盘、连接各焊盘的配线部以及固定引线11的焊盘等。另外,第二配线层18B和第一配线层18A可平面交叉地形成。因此,即使在半导体元件14A具有多个电极的情况,也可以通过本发明的多层配线结构自由地进行布线图案的引绕布置。该第二配线层18B和上述的第一配线层18A通过连接部25连接在所希望的位置。
电路元件14固定于第二配线层18B上,由电路元件14和配线层18构成规定的电路。电路元件14采用晶体管、二极管等有源元件,或电容、电阻等无源元件。另外,功率类半导体元件等发热量大的元件可以通过金属构成的散热片固定在电路衬底16上。在此,面朝上安装的有源元件等介由金属细线15与第二配线层18B电连接。
半导体元件14A是表面具有数十个~数百个焊盘的半导体元件。另外,也可以采用所谓的系统LSI作为半导体元件14A。在此,系统LSI是指具有模拟运算电路、数字运算电路及存储部等,且由一个LSI实现系统功能的元件。因此,与现有的LSI相比,系统LSI动作时产生大量的热。
在半导体元件14A的背面与接地电位连接时,半导体元件14A的背面利用焊料或导电膏等固定。半导体元件14A的背面漂移时,使用绝缘性粘结剂固定半导体元件14A的背面。另外,在半导体元件14A利用面朝下结合法安装时,介由焊锡等构成的补片电极(バンプ電極)安装。
可采用控制大电流的功率类晶体管、例如功率金属氧化物半导体、GTBT、IGBT、闸流晶体管等作为半导体元件14A。也可以采用功率类IC作为半导体元件14A。
引线11在电路衬底16的周边部固定在第二配线层18B上,并具有例如与外部进行输入·输出的作用。在此,一边设有多个引线11。引线11与布线图案的连接通过作为焊锡等的焊料19进行。
密封树脂12通过使用热硬性树脂的传递成型或使用热塑性树脂的注射成型而形成。在此,形成密封树脂12,密封电路衬底16及形成于其表面的电路,电路衬底16的背面从密封树脂12露出。另外,除利用模制进行的密封之外的密封方法也可以适用于本实施例的混合集成电路装置中,例如可使用利用树脂接合进行的密封、箱材进行的密封等众所周知的密封方法。参照图1(A),为使从载置于电路衬底16表面的电路元件14产生的热顺畅地排出外部,电路衬底16的背面从密封树脂12露出外部。另外,为提高装置整体的耐湿性,也可以利用密封树脂12密封含有电路衬底16背面的整体。
参照图1(B),在本实施例中,第二绝缘层17B由第一树脂膜17B1及第二树脂膜17B2构成。具体地说,形成由混入有无机填充物的树脂构成的第一树脂膜17B1,使其覆盖第一配线层18A。另外,在该第一树脂膜17B1的上层层积有第二树脂膜17B2。通过该结构,具有容易形成连接部25的优点。后面详细叙述。
参照图1(B),连接部25是贯通第二绝缘层17B,将第一配线层18A与第二配线层18B电连接的部位。在此,在设于第一树脂膜17B1的第一通孔32A中填充有第二树脂膜17B2,在该填充部分的第二树脂膜17B2上穿设第二通孔32B。而且,在第二通孔32B的内壁形成有由镀敷膜构成的连接部25。
在本实施例中,利用设于第一通孔32A内壁的第二树脂膜17B2提高连接部25的连接可靠性。即,由于作为连接部25的材料的金属与第一树脂膜17B1的热膨胀系数不同,故在加热时,在两者之间产生热应力。因此,在本实施例中,通过使第二树脂膜17B2介于两者之间,使第二通孔32B作为缓和应力的区域起作用,实现热应力的降低。具体地说,在设于第一树脂膜17B1的第一通孔32A中填充第二树脂膜17B2。然后,在填充部分的第二树脂膜17B2中设置第二通孔32B,在该第二通孔32B中形成作为镀敷膜的连接部25。在此,在第一通孔32A中填充有覆盖第一树脂膜17B1的第二树脂膜17B2,但也可以仅在第一通孔32A中部分地埋入绝缘性树脂。
参照图1(C)说明其它例的连接部25的结构。在此,连接部25由从第一配线层18A延伸的第一连接部25A和从第二配线层18B延伸的第二连接部25B构成。第一连接部25A是从第一配线层18A连续,向厚度方向突出的部位。在此,第一连接部25A向上方突出,埋入第二绝缘层17B内。第二连接部25B是从第二配线层18B连续,向厚度方向突出的部位,在此,第二连接部25B向下方突出,被埋入第二绝缘层17B中。
第一连接部25A是通过蚀刻加工而向厚度方向突出形成的部位,由与构成配线层的材料即轧制铜箔等相同的材料构成。另外,第一连接部25A也可以利用蚀刻加工之外的方法形成。具体地说,可通过使电解镀敷膜或无电解镀敷膜在第一配线层18A的表面凸状成膜,形成第一连接部25A。另外,即使在第一配线层18A的表面设置焊锡等焊料或银膏等导电性材料,也可以形成第一连接部25A。
第二连接部25B是通过电解镀敷或无电解镀敷的镀敷处理形成的部位。具体地说,通过形成于第二通孔32B内壁的镀敷膜形成第二连接部25B。关于该第二连接部25B的形成方法,后文将在说明制造方法的实施例中叙述。
在本例中,使上述的第一连接部25A与第二连接部25B接触的位置位于第二绝缘层17B的厚度方向的中间部。在此,中间部是指,第一配线层18A上面的上方,第二配线层18B下面的下方。因此,在纸面上,第一连接部25A与第二连接部25B接触的位置成为第二绝缘层17B的厚度方向中央部附近,但该位置可在上述的中间部的范围内变化。在考虑通过镀敷处理形成第二连接部25B时,第一连接部25A与第二连接部25B接触的部分位于第二绝缘层17B厚度方向的中央部的上方。由此,具有容易形成由镀敷膜构成的第二连接部25B的优点。
参照图2的立体图说明形成于电路衬底16表面的第二配线层18B的具体的形状之一例。在该图中,省略密封整体的树脂。
参照图2,第二配线层18B构成安装电路元件14的接合焊盘的部分和固定引线11的焊盘26等。另外,在半导体元件14A的周边部形成多个引线接合金属细线15的焊盘。在载置具有多个接合焊盘的半导体元件14A时,在仅利用第二配线层18B得到的单层图案中,由于配线密度有限,故有可能不能充分地进行引绕布置。在本例中,通过在电路衬底16的表面构筑多层配线结构,实现复杂的图案的引绕布置。
参照图3说明其它例的混合集成电路装置的结构。图3(A)及图3(B)是其它例的混合集成电路装置的剖面图。在该图所示的混合集成电路装置中,位于各配线层相互之间的第二绝缘层17B由第一树脂膜17B1及形成于其上面的第二树脂膜17B2构成。
参照图3(A),在此,形成有热敷金属夹层27,使其贯通第二绝缘层17B。热敷金属夹层27是在贯通第二绝缘层17B的孔中填充有金属的部位,作为向外部排热的经路起作用。因此,热敷金属夹层27也可以不导通。具体地说,形成热敷金属夹层27,使其接触固定半导体元件14A的岛状的第二配线层18B下面。因此,即使在由半导体元件14A产生大量的热的情况,其热量也可以通过多个热敷金属夹层27传递到电路衬底16上。此时的排热的经路是:半导体元件14A→第二配线层18B→热敷金属夹层27→第一绝缘层17A→电路衬底16→外部。在此,热敷金属夹层27由上述的第一连接部25A和第二连接部25B构成。而且,第一连接部25A和第二连接部25B接触的部分为绝缘层厚度方向的中间部。
参照图3(B),在此,在第一绝缘层17A及第二绝缘层17B两个上设有热敷金属夹层27。如上所述,含有大量填充物的第一绝缘层17A散热性优良。因此,如图3(B)所示,通过在第一绝缘层17A上设置热敷金属夹层27,可进一步提高散热性。设于第一绝缘层17A上的热敷金属夹层27最好也设置在与产生热的半导体元件14A下方对应的区域。
如上所述,在电路衬底16和第一绝缘层17A之间形成热敷金属夹层27B时,在电路衬底16的表面形成凸状地突出的第一连接部25A。另外,在第一配线层18A的背面设置第二连接部25B。而且,使第一连接部25A和第二连接部25B在第一绝缘层17A的中间部接触。
参照图4进一步说明又一例的混合集成电路装置的结构。图4(A)及图4(B)是混合集成电路装置的剖面图。在该图所示的混合集成电路装置中,位于各配线层相互之间的各绝缘层17可由第一树脂膜17B1及形成于其上面的第二树脂膜17B2构成。
参照图4(A),在此,通过介由绝缘层17层积配线层18,构成四层配线结构。具体地说,在第一绝缘层17A的上面形成第一配线层18A。而且,介由从第二绝缘层17B到第四绝缘层17D层积从第二配线层18B到第四配线层18D。这样,可通过增加配线层18的层数提高配线密度。在第二绝缘层17B到第四绝缘层17D上为连接各层相互之间的配线层,而形成有连接部25。在此,第二绝缘层17B、第三绝缘层17C及第四绝缘层17D也由上述的第一树脂膜17B1及第二树脂膜17B2形成。由此,具有容易形成连接部25的优点。
参照图4(B),在此,在载置焊盘数量多的半导体元件14A的区域的电路衬底16表面形成有多层配线结构,在固定电路元件14B的区域的电路衬底16表面形成有单层的配线结构。
如上所述,半导体元件14A是具有数十~数百个电极的元件。因此,为引绕布置与半导体元件14的电极连接的布线图案,而在半导体元件14A的周边部形成有多层配线结构。具体地说,形成有由第一配线层18A及第二配线层18B构成的多层配线层。
另外,形成多层的部分的第二配线层18B和形成单层的部分的第一配线层18A通过金属细线15电连接。
电路元件14B例如是功率系半导体元件,是伴随大量发热的开关元件。形成由第一配线层18A构成的单层配线结构的部分的电路衬底16比其它区域的散热效果大。因此,若像电路元件14B这样发热量大的单个的晶体管最好直接固定在构成单层配线的第一配线层18A上。
第二实施例
在本实施例中,作为电路装置之一例,以混合集成电路装置为例进行说明。但是,下述的本实施例制造方法也可以适用于其它种类的电路装置的制造方法。
首先,参照图5(A),在电路衬底16的表面涂敷第一绝缘层17A,层积第一导电膜28A。作为电路衬底16,可采用厚度1.5mm左右的金属板。另外,作为第一导电膜28A,可采用以铜为主材料的材料、以Fe-Ni或Al为主材料的材料。第一导电膜28A的厚度需要大于或等于将形成预定的配线层18A的厚度和第一连接部25A的高度相加的厚度。具体地说,第一导电膜28A的厚度例如在20μm~150μm程度的范围。抗蚀剂29A覆盖第一导电膜28A预定形成第一连接部25A的区域的表面。在利用抗蚀剂29A进行覆盖的状态下进行蚀刻。另外,第一绝缘层17可采用在环氧树脂等绝缘性树脂中混入无机填充物的物质。在此,混入的无机填充物是SiO2、Al2O3、SiC、AlN等。
图5(B)表示进行蚀刻后的状态的剖面。在此,利用抗蚀剂29A覆盖的区域凸状地突出。利用该凸状突出的部位形成第一连接部25A。而且,在表面露出的状态下进行蚀刻的区域的第一导电膜28A同样使厚度变薄。在本工序结束后,将抗蚀剂29A剥离。在此,将第一连接部25A突出的高度调整为数十μm程度。图5(C)表示剥离抗蚀剂29A的状态的第一连接部25A。
通过上述工序形成向第一导电膜28A的厚度方向凸状突出的第一连接部25A,但也可以省略该工序,进行电路装置的制造。例如在形成如图1(B)所示结构的连接部25时,可省去上述工序。
然后,参照图6(A),利用抗蚀剂29B覆盖包括第一连接部25A上面的第一导电膜28A。另外,参照图6(B),在使抗蚀剂29B施加在预定形成的单元配线层18A而进行构图后,进行蚀刻。由此,对第一导电膜28A进行构图。图6(C)表示进行蚀刻后的状态。在第一配线层18A的蚀刻结束后,将抗蚀剂29B剥离。
其次,参照图7,在由第一树脂膜17B1覆盖第一配线层18A后,形成第一通孔32A。
参照图7(A)使用第一树脂膜17B1覆盖第一配线层18A。在此,形成第一树脂膜17B1,使其也覆盖向上方突出的第一连接部25A的上面。作为第一树脂膜17B1的材料,采用向环氧树脂等绝缘性树脂中混入有无机填充物的树脂。混入的无机填充物的量可在30重量%~80重量%程度之间变化。另外,为提高散热性,也可以向第一树脂膜17B1中填充粒径30μm左右的较大的填充物。
接着,参照图7(B),利用激光等除去方法部分地除去覆盖第一连接部25A的部分的第一树脂膜17B1。在本实施例中,通过埋入第一连接部25A,部分地减薄第一树脂膜17B1。然后,通过使用激光除去变薄的区域的第一树脂膜17B1,使第一连接部25A在第一通孔32A的下部露出。在大部分区域,第一树脂膜17B1的厚度T2例如为50μm左右,与此相对,在形成第一通孔32A的区域,第一树脂膜17B1的厚度T1例如薄至10μm~25μm程度。
因此,在假设利用激光形成相同长宽比的第一通孔32A时,根据本实施例,可形成直径小的第一通孔32A。在上述厚度条件的情况,由于第一通孔32A的直径可形成一半的程度,故可将第一通孔32A占有的面积减小到1/4程度。这有利于装置整体的小型化。另外,在第一树脂膜17B1中为确保散热性而混入无机填充物,由此,存在难以利用激光形成第一通孔32A的状况。由于以这种状况形成第一通孔32A,故减薄形成第一通孔32A的区域的第一树脂膜17B1有意义。
第一连接部25A的平面的大小形成得比形成于其上方的第一通孔32A大。换句话说,由于第一通孔32A及第一连接部25A的平面形状为圆形,故第一连接部25A的直径形成得比第一通孔32A的直径大。例举一例,在第一通孔32A的直径W2为100μm程度时,第一连接部25A的直径W1形成150μm~200μm。另外,在第一通孔32A的直径W2为30μm~50μm程度时,第一连接部25A的直径W1调整为50μm~70μm程度。这样,通过使第一连接部25A的平面的大小比第一通孔32A大,即使在第一通孔32A伴随多少有位置偏差而形成的情况,也可以使第一通孔32A位于第一连接部25A的上方。因此,可防止上述位置偏差造成的连接可靠性的降低。另外,作为第一连接部25A的平面形状,也可以采用除圆形之外的形状。
图7(C)表示形成第一通孔32A后的电路衬底16的状态。在此,在各第一连接部25A的上方形成有第一通孔32A。然后,从各第一通孔32A的底面露出第一连接部25A的上面。
其次,参照图8(A),在第一树脂膜17B1的表面形成第二树脂膜17B2,在第二树脂膜17B2的上面层积第二导电膜28B。具体地说,形成第二树脂膜17B2,使其覆盖第一树脂膜17B1的表面,且填充第一通孔32A。利用第一树脂膜17B1和第二树脂膜17B2形成位于各配线层18A之间的第二绝缘层17B。
第二树脂膜17B2的材料采用混入有散热用无机填充物的树脂或未混入无机填充物的树脂。通过采用未混入无机填充物的树脂作为第二树脂膜17B2,容易形成下述的第二通孔32B。另外,可使第二通孔32B的侧面较平滑,可容易利用无电场处理形成镀敷膜。另外,即使在第二树脂17B2中混入无机填充物的情况,也可以使其量比第一树脂膜17B1的少。另外,第二树脂膜17B2中含有的无机填充物的平均粒径也可以比第一树脂膜17B2中含有的无机填充物的小。由此,可容易地由之后的工序形成第二通孔32B。由于可减小第二通孔32B侧壁的凹凸,故能可靠地利用电解镀敷法形成镀敷膜。
然后,参照图8(B)及图8(C),除去对应第一连接部25A上方的位置,有选择地在第二导电膜28B的表面形成抗蚀剂29C。另外,通过进行蚀刻,除去由抗蚀剂29C覆盖的部分的第二导电膜28B。
参照图9(A),通过利用上述蚀刻有选择地除去第二导电膜28B,填充于第一通孔32A的第二树脂膜17B2的上面露出外部。在第二导电膜28B开口的宽度设为W3时,该宽度W3比第一通孔32A的宽度W2窄。另外,第二导电膜28B的开口部形成于第一通孔32A的区域的内部。由此,可将通过从上方照射激光形成的第二通孔32B形成得比第一通孔32A小。另外,可在第一通孔32A的内部形成第二通孔32B。
然后,参照图9(B),通过照射激光,除去从第二导电膜28B露出的区域的第二树脂膜17B2。第二树脂膜17B2含有的无机填充物的量比第一树脂膜17B1少。或者,第二树脂膜17B2中未混入无机填充物。因此,可容易地通过照射激光形成第二通孔32B。另外,由于第二通孔32B的侧面构成较平滑的面,故可容易地利用无电解镀敷法形成镀敷膜。
图9(C)表示利用上述工序形成第二通孔32B后的状态。在各第一连接部25A的上方形成有第一通孔32A及第二通孔32B。
另外,在上述说明中,形成有第二树脂膜17B2,使其覆盖第一树脂膜17B1表面,且填充于第一通孔32A中,但也可以仅在第一通孔32A的内部填充绝缘性树脂。在该情况下,将具有与第二树脂膜17B2相同组成的树脂材料填充于第一通孔32A中。然后,在该树脂材料上形成第二通孔32B。
另外,为由之后的工序进行镀敷处理,进行作为前处理的锌酸盐处理。在此,锌酸盐处理是指,容易通过使用含Zn离子的碱溶液进行无电解镀敷处理而进行镀敷处理的处理。在第二通孔32B的侧壁也具有无机填充物露出的情况,故考虑将无机填充物和镀敷膜的附着强度减弱。因此,通过进行该锌酸盐处理,可容易通过对露出的无机填充物进行无电解处理而形成镀敷膜。
其次,参照图10及图11,说明在第二通孔32B中通过形成镀敷膜而形成第二连接部25B,使第一配线层18A和第二导电膜28B导通的工序。在此,由第一连接部25A及第二连接部25B形成连接部25。而且,利用该连接部25将配线层相互在所希望的位置连接。成为该第二连接部25B的镀敷膜的形成考虑两个方法。第一个方法是在利用无电解镀敷形成镀敷膜后,通过电解镀敷再次形成镀敷膜的方法。第二个方法是仅通过电解镀敷处理形成镀敷膜的方法。
参照图10说明形成镀敷膜的上述第一方法。首先,参照图10(A),在也含有第二通孔32B侧壁的第二导电膜28B的表面通过无电解处理形成镀敷膜34。该镀敷膜34的厚度只要在3μm~5μm程度即可。如上所述,形成于含有的填充物的量少的第二树脂膜17B2的第二通孔32B的侧壁,构成容易通过无电解处理形成镀敷膜的状态。
其次,参照图10(B),在镀敷膜34的上面通过电解镀敷法形成新的镀敷膜35。具体地说,以形成镀敷膜34的第二导电膜28B为阴极电极,通过电解镀敷法形成镀敷膜35。利用上述的无电解镀敷法在第二通孔32B的内壁形成镀敷膜34。因此,在此形成的镀敷膜35含有第二通孔32B的内壁并形成一样的厚度。由此,形成由镀敷膜构成的第二连接部25B。镀敷膜35的具体厚度例如为20μm程度。作为上述的镀敷膜34及镀敷膜35的材料,可采用与第二导电膜28B相同的材料即铜。另外,可采用铜以外的金属作为镀敷膜34及镀敷膜35的材料。
参照图10(C),在此,通过进行填充镀敷(フイリングメッキ),利用镀敷膜35埋入第二通孔32B。通过进行该填充镀敷,可提高第二连接部25B的机械强度。
其次,参照图11说明使用电解镀敷形成第二连接部25B的方法。
参照图11(A),首先,使含金属离子的溶液与第二通孔32B接触,在此,作为镀敷膜的材料,可采用铜、金、银、钯等。而且,当以第二导电膜28B为阴极电极,流过电流时,在作为阴极电极的第二导电膜28B上析出金属,形成镀敷膜。在此,36A、36B表示镀敷膜生长的样态。在电解镀敷法中,在电场强的位置优先形成镀敷膜。在本例中,该电场在面向第二通孔32B周边部的部分的第二导电膜28B增强。因此,如该图所示,从面向第二通孔32B周边部的部分的第二导电膜28B优先生长镀敷膜。在形成的镀敷膜与第一连接部25A接触时刻,第一配线层18A和第二导电膜28B导通。然后,在第二通孔32B的内部形成与第二导电膜28B一体化的第二连接部25B。
参照图11(B),说明形成第二连接部25B的其它方法。在此,通过在第二通孔32的周边部设置遮檐部13,容易利用电解镀敷法形成第二连接部25B。在此,“遮檐部”是指,覆盖第二通孔32周边部地由突出的第二导电膜28B构成的部位。遮檐部13的具体的制造方法在利用激光形成第二通孔32时,可通过增大该激光的输出进行。通过增大激光的输出,使激光进行的对第二绝缘层17B2的除去沿横向进行,由此,遮檐部13下方区域的树脂被除去。通过利用上述条件进行以第二导电膜28B为阴极电极的电解镀敷处理,从遮檐部13的部分优先生长镀敷膜。通过从遮檐部13生长镀敷膜,与图11(A)的情况相比,可优先向下方生长镀敷膜。因此,能够可靠地由镀敷膜埋入通孔32。使用了上述的电解镀敷法的镀敷膜的形成通过使无机填充物在第二通孔32B的侧壁露出,即使在用于形成镀敷间膜的条件恶化时也可以进行。
在本例中,通过在第二通孔32B中形成镀敷膜,必然也在第二导电膜28B的表面形成镀敷膜,其厚度增厚。但是,在本例中,如上所述,由于在10μm程度的浅的第二通孔32B中形成镀敷膜,故可减薄形成的镀敷膜的总厚度。因此,由于附着镀敷膜得到的第二导电膜28B的厚度的增加量小,故可在减薄第二导电膜28B的状态下保持。因此,可微细地形成由第二导电膜28B形成的第二配线层18B。
另外,即使在通过施行填充镀敷埋入通孔32时,如上所述,也可以浅得形成通孔32,因此,可容易地进行填充镀敷。
参照图12(A),通过形成第二连接部25B,形成由第一连接部25A及第二连接部25B构成的连接部25。另外,参照图12(B),通过进行使用抗蚀剂29D的有选择的蚀刻,形成第二配线层18B。参照图12(C),在此,形成由第一配线层18A、第二配线层18B、第三配线层18C构成的三层多层配线。此时,在第二配线层18B上,在上面及下面两面形成构成连接部25的凸状部位。
参照图13(A),介由焊锡或导电膏等将电路元件14固定在第二配线层18B(岛)上。半导体元件14A利用面朝下接合法或面朝上接合法安装。另外,参照图13(B),通过金属细线15将半导体元件14与第二配线层18B电连接。
在上述工序结束后,进行各单元24的分离。各单元24的分离可通过使用冲压机的冲压、切割、折曲等进行。然后,在各单元24的电路衬底16上固定引线11。
然后,参照图14,进行各电路衬底16的树脂密封。在此,通过使用热硬性树脂的传递成型而进行。即,在由上模型30A及下模型30B构成的模型30中收纳电路衬底16,然后,通过将两模型咬合,固定引线11。然后,通过向型腔31中封入密封树脂,进行树脂密封的工序。利用以上的工序制造图1表示其结构的混合集成电路装置。
Claims (16)
1、一种电路装置,其特征在于,包括:多个配线层,其通过含有填充物的绝缘层层积而成;连接部,其沿厚度方向贯通所述绝缘层,在所希望的位置将所述配线层相互之间电连接,将所述连接部设置在覆盖设于所述绝缘层的通孔侧壁的绝缘性树脂的内部,所述绝缘性树脂比所述绝缘层的所述填充物的含有量少。
2、如权利要求1所述的电路装置,其特征在于,在所述绝缘层上设置局部向厚度方向突出的第一连接部,在通过埋入所述第一连接部而变薄的区域的所述绝缘层上设置所述通孔。
3、如权利要求1所述的电路装置,其特征在于,所述绝缘性树脂中含有的所述填充物的平均粒径比所述绝缘层中含有的所述填充物的平均粒径小。
4、一种电路装置,其特征在于,具有通过含有填充物的绝缘层层积的多个配线层,所述配线层相互之间介由在厚度方向贯通所述绝缘层的连接部在所希望的位置电连接,所述绝缘层由含有填充物的第一树脂膜和层积于所述第一树脂膜,比所述第一树脂膜的填充物的含有量少的第二树脂膜构成,设置在厚度方向贯通所述第一树脂膜的通孔,在覆盖所述通孔侧壁的所述第二树脂膜内部设置所述连接部。
5、如权利要求4所述的电路装置,其特征在于,在所述绝缘层上设置局部向厚度方向突出的第一连接部,在通过埋入所述第一连接部而变薄的区域的所述绝缘层上设置所述通孔。
6、如权利要求4所述的电路装置,其特征在于,所述第二树脂膜中含有的所述填充物的平均粒径比所述第一树脂膜中含有的所述填充物的平均粒径小。
7、一种电路装置的制造方法,该电路装置具有介由含填充物的绝缘层层积的多个配线层,其特征在于,包括:形成沿厚度方向贯通所述绝缘层的第一通孔的工序;将比所述绝缘层的填充物的含有量少的绝缘性树脂埋设在所述第一通孔内的工序;在所述绝缘性树脂上形成平面大小比所述第一通孔小的第二通孔的工序;在所述第二通孔中设置使所述配线层相互之间导通的连接部的工序。
8、如权利要求7所述的电路装置的制造方法,其特征在于,所述绝缘性树脂中含有的所述填充物的平均粒径比所述绝缘层中含有的填充物的平均粒径小。
9、如权利要求7所述的电路装置的制造方法,其特征在于,所述第一通孔及所述第二通孔通过照射激光而形成。
10、如权利要求7所述的电路装置的制造方法,其特征在于,所述连接部的形成通过在所述第二通孔中形成镀敷膜而进行。
11、如权利要求7所述的电路装置的制造方法,其特征在于,所述第一通孔及所述第二通孔设置在通过局部增厚所述配线层而变薄的区域的所述绝缘层上。
12、一种电路装置的制造方法,其特征在于,包括:在电路衬底表面形成第一配线层的工序;在所述电路衬底表面设置混入有填充物的第一树脂膜,覆盖所述第一配线层的工序;通过形成沿厚度方向贯通所述第一树脂膜的第一通孔,使所述第一配线层从所述第一通孔底部露出的工序;在所述第一树脂膜的表面形成所述填充量少于所述第一树脂膜的第二树脂膜,使其填充在所述第一通孔中的工序;在所述第二树脂膜的表面层积第二导电膜的工序;通过除去填充于所述第一通孔的所述第二树脂膜及其上方的所述第二导电膜,形成比所述第一通孔小的第二通孔,使所述第一配线层从所述第一通孔底部露出的工序;在所述第二通孔中设置使所述第一配线层和所述第二导电膜导通的连接部的工序;通过对所述第二导电膜进行构图,形成第二配线层的工序。
13、如权利要求12所述的电路装置的制造方法,其特征在于,所述第二树脂膜中含有的所述填充物的平均粒径比所述第一树脂膜中含有的填充物的平均粒径小。
14、如权利要求12所述的电路装置的制造方法,其特征在于,所述第一通孔及所述第二通孔通过照射激光而形成。
15、如权利要求12所述的电路装置的制造方法,其特征在于,所述连接部的形成通过在所述第二通孔中形成镀敷膜而进行。
16、如权利要求12所述的电路装置的制造方法,其特征在于,形成所述第一通孔及所述第二通孔,使局部较厚地形成的所述第一配线层的上面露出。
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JP2007311770A (ja) * | 2006-04-17 | 2007-11-29 | Mitsubishi Electric Corp | 半導体装置 |
JP2010153571A (ja) * | 2008-12-25 | 2010-07-08 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
JP5982760B2 (ja) * | 2011-09-07 | 2016-08-31 | 富士通株式会社 | 電子デバイス及びその製造方法 |
JP2013214550A (ja) * | 2012-03-30 | 2013-10-17 | Toshiba Corp | 高周波モジュール |
JP2014220307A (ja) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | 多層基板、これを用いた電子装置および多層基板の製造方法 |
JP6111833B2 (ja) * | 2013-05-06 | 2017-04-12 | 株式会社デンソー | 多層基板の製造方法 |
JP2015119073A (ja) * | 2013-12-19 | 2015-06-25 | 日本シイエムケイ株式会社 | 多層プリント配線板および、その製造方法 |
GB201503089D0 (en) * | 2015-02-24 | 2015-04-08 | Flight Refueling Ltd | Hybrid electronic circuit |
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NL154876B (nl) * | 1966-04-14 | 1977-10-17 | Philips Nv | Werkwijze voor het vervaardigen van elektrisch werkzame inrichtingen met monokorrellagen met actieve korrels in een isolerende vulstof, alsmede volgens deze werkwijze verkregen elektrisch werkzame inrichting. |
JP2698278B2 (ja) | 1992-01-31 | 1998-01-19 | 三洋電機株式会社 | 混成集積回路装置 |
JPH06268380A (ja) * | 1993-03-16 | 1994-09-22 | Ibiden Co Ltd | プリント配線板 |
JP3271094B2 (ja) * | 1993-07-05 | 2002-04-02 | ソニー株式会社 | 積層配線基板及びその製造方法 |
JP2848357B2 (ja) * | 1996-10-02 | 1999-01-20 | 日本電気株式会社 | 半導体装置の実装方法およびその実装構造 |
US6038133A (en) * | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP2000260912A (ja) * | 1999-03-05 | 2000-09-22 | Fujitsu Ltd | 半導体装置の実装構造及び半導体装置の実装方法 |
JP4592891B2 (ja) * | 1999-11-26 | 2010-12-08 | イビデン株式会社 | 多層回路基板および半導体装置 |
JP2002158355A (ja) * | 2000-11-20 | 2002-05-31 | Nec Kansai Ltd | 半導体装置およびその製造方法 |
JP2002353631A (ja) * | 2001-05-28 | 2002-12-06 | Matsushita Electric Ind Co Ltd | 回路基板とその製造方法 |
EP1401020A4 (en) * | 2001-06-07 | 2007-12-19 | Renesas Tech Corp | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME |
JP2003174262A (ja) * | 2001-12-07 | 2003-06-20 | Hitachi Chem Co Ltd | 多層配線板の製造方法 |
US7170062B2 (en) * | 2002-03-29 | 2007-01-30 | Oy Ajat Ltd. | Conductive adhesive bonded semiconductor substrates for radiation imaging devices |
JP2004047587A (ja) * | 2002-07-09 | 2004-02-12 | Eastern Co Ltd | 配線回路基板の製造方法および配線回路基板 |
KR100518587B1 (ko) * | 2003-07-29 | 2005-10-04 | 삼성전자주식회사 | 얕은 트렌치 소자 분리 구조의 제조 방법 및 얕은 트렌치소자 분리 구조를 포함하는 미세 전자 소자 |
US7588963B2 (en) * | 2004-06-30 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming overhang support for a stacked semiconductor device |
KR100684169B1 (ko) * | 2005-08-11 | 2007-02-20 | 삼성전자주식회사 | 이원 필러 분포를 가지는 접착 필름 및 그 제조 방법, 이를이용한 칩 적층 패키지 및 그 제조 방법 |
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2004
- 2004-05-31 JP JP2004162657A patent/JP4592333B2/ja not_active Expired - Fee Related
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2005
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US20050263895A1 (en) | 2005-12-01 |
CN100411154C (zh) | 2008-08-13 |
JP4592333B2 (ja) | 2010-12-01 |
US7339281B2 (en) | 2008-03-04 |
JP2005347358A (ja) | 2005-12-15 |
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