CN1434979A - Mosfet器件系统和方法 - Google Patents

Mosfet器件系统和方法 Download PDF

Info

Publication number
CN1434979A
CN1434979A CN00819019A CN00819019A CN1434979A CN 1434979 A CN1434979 A CN 1434979A CN 00819019 A CN00819019 A CN 00819019A CN 00819019 A CN00819019 A CN 00819019A CN 1434979 A CN1434979 A CN 1434979A
Authority
CN
China
Prior art keywords
source electrode
drain electrode
semiconductor chip
family
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN00819019A
Other languages
English (en)
Other versions
CN1222021C (zh
Inventor
J·P·辛德尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spinnaker Semiconductor Inc
Original Assignee
Spinnaker Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spinnaker Semiconductor Inc filed Critical Spinnaker Semiconductor Inc
Publication of CN1434979A publication Critical patent/CN1434979A/zh
Application granted granted Critical
Publication of CN1222021C publication Critical patent/CN1222021C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

公开了MOSFET器件系统和制造该器件系统的方法。本发明在MOSFET器件结构的范围内采用肖特基势垒接触(301，302)作为源极和/或漏极接触的制造，从而不需要控制短沟道效应的光晕/阱注入物以及浅源极/漏极的外延。另外，本发明无条件地除去了与MOSFET制造相关的寄生双极性的阱，从而减少了生产成本，更紧密地控制器件性能参数，并提供优于现有技术的器件特性。

Description

MOSFET器件系统和方法
技术领域
本发明总的来说涉及金属氧化物半导体场效应管(MOSFET)，特别适用于集成电路(IC)范围内器件的制造。
背景技术
由于十九世纪四十年代后期晶体管的发明，在微电子领域已取得了巨大的进步。现有技术允许在边长大约10mm的硅片上成本低廉地制造出超过一亿个元件的集成电路(IC)。在未来几年内将会在商业上使用十亿个晶体管的IC。在较少的成本下使得每个IC能具有更强的功能和更好的性能的要求促使了几种趋势。
第一，功能性促使IC晶体管组合起来。第二，进一步减少晶体管自身的尺寸，以获得更高的封装密度，很重要的是，可以改进它们的性能。就性能而言，金属氧化物半导体场效应管(MOSFET，当今占主导地位的晶体管技术)的关键参数为沟道长度。沟道长度(L)是电荷载流子穿过器件所必须通过的距离，该长度的减少同时也意味着提高了电流驱动、减少了寄生电阻和电容以及改善了高频性能。一般的品质因数是功率延迟乘积，且这归一化晶体管性能的测量改进是以沟道长度倒数的立方(1/L3)成比例。这便解释了IC制造商必须尽制造能力的所能来尽力减小沟道长度强烈动机。
在数字化的应用中，MOS晶体管的行为就像开关。当“开”时，它们能驱动相当大量的电流，而当变成“关”时，它们的特征就是一定量的漏电流。随着沟道长度的减小，驱动电流就会增大，这有利于以上所陈述的电路性能。然而，漏电流也会增大。漏电晶体管增加了静态功耗(空载时IC所消耗的功率)，极端情况下会影响通常操作中二进制信息的转移。因此，器件的设计者必须在沟道长度减少的同时保持低的漏电流。
控制MOS晶体管漏电流的常规方法是通过在器件的沟道区掺入的控制量的杂质(掺杂剂)，以及将源极/漏极设计成横向的或垂直的掺杂分布。虽然这些措施能有效地维持MOS晶体管内的势垒，且因此还减小了漏电流，但它们也有助于驱动电流的减小和寄生电容增加，后者正是减小沟道长度所要改进的。此外，根据沟道和制作源极/漏极的生产过程中如何被掺入掺和剂，生产成本会受到很明显的影响。在常见的MOS晶体管设计和结构中，仅有有限的方法可以在驱动电流、漏电流、寄生电阻和电容以及生产复杂性/成本之间进行权衡。
本发明在这些所权衡的要求之间提供了新的关系，并且有可能使得MOS器件具有和用常规(掺杂的杂质)MOS结构无法得到的特性。用源极和漏极的金属，以及简单且均匀掺入沟道的掺杂剂的分布提供了器件在减小寄生电容、减少这些特性中的统计变化(特别当沟道长度减少时)以及减少的生产成本和复杂性等方面的改进。
现有技术的描述
掺杂分布
前几代MOS晶体管凭借横向上均匀而垂直方向上非均匀的沟道掺杂分布来控制漏极至源极的漏电流。见由Yuan Taur所著的题为“不可思议的收缩晶体管”IEEE SPECTRUM( www.spectrum.ieee.org，ISSN 0018-9235，1999年7月，第25到29页)。图1说明了典型的长沟道常规MOS器件(100)，它包含杂质掺杂的源极(101)、杂质掺杂的漏极(102)、常规的MOS型栅极堆(103)以及有助于控制漏极至源极之间漏电流的在基片中横向均匀的沟道掺杂分布(104)。器件通过场氧化层(105)形成电学上彼此绝缘。这样的沟道掺杂分布在沟道长度减至大约200纳米(nm)的器件中很普遍。
然而，随着器件的沟道长度已被减少到100nm的范围，文献中指出，该范围需要在横向上和垂直方向上都非均匀的沟道掺杂分布。参考图2，典型的短沟道MOS器件(200)具有一些与长沟道MOS器件(100)相同的元件。其结构包含常规的杂质掺杂的源极(201)和漏极(202)以及常规的MOS栅堆(203)(沟道长度L所对应的宽度＜～100nm)。该结构还包含用于连接漏极阱掺杂(206)和源极阱掺杂(207)的源电极浅杂质外延(208)和漏电极浅杂质外延(209)，以及控制源极至漏极漏电流的常规的沟道掺杂(204)。源电极(201)和漏电极(202)以及它们各自的外延(208)和(209)(所有四种包含制作的源极/漏极掺杂分布的组合)都有相同的掺杂极性(N型或P型)，而且都与沟道(204)以及阱掺杂元件(206)和(207)的极性相反。再利用场氧化层(205)在电学上将器件彼此相互间绝缘。
在“对25nmCMOS设计的思考”(1998IDEM技术摘要，第789页)一文中，YuanTaur指出
“…an optimized，vertically and laterally non_uniform doping profile，called the super_halo，is needed to control the short channel effect.”
在IEEE光谱杂志中也有类似的叙述：
“…in the 100 to 130nm lithography generation，an optimally tailoredprofile that is both vertically and laterally non_uniform(Super-Halo)isneeded to control[short channel effect].”
见Linda Geppert所著的“一亿个晶体管的集成电路”( www.spectrum.ieee.org，IEEE SPECTRUM，ISSN 0018-9235，1999年7月，第23至24页)。
此外，几乎所有讨论沟道长度少于200nm状态的或在横向和垂直两个方向上均的为高度非均匀的沟道掺杂分布掺杂的器件设计的现有技术来充分控制漏极至源极的漏电流。举例来说，在题为“具有双栅氧化层和9.7皮秒反相延时的小于0.08um的高性能COMS”(1998年的IEDM，第627页)的论文中，Hargrove叙述到
“In order to achieve optimal device performance…strong haloscoupled with shallow junctions are required.”
现有技术在其需要横向和垂直非均匀的掺杂分布，以非均匀的沟道掺杂剂和浅源极/漏极延伸的形式来对短沟道效应进行充分控制的叙述中几乎是一致的。
阱/光晕注入物
横向非均匀的沟道掺杂分布几乎在栅电极被确定且固定后再专门地引入的。栅极起着注入膜的作用，与那些已在基片中的掺杂剂同类型的掺杂剂通过离子注入的方法引入毗邻栅电极的沟道区。正如前面所提到的，这些通常被称为“阱”或“光晕”注入。见Yuan Taur发表的的“不可思议的收缩晶体管”( www.spectrum.ieee.org，IEEE SPECTRUM，ISSN 0018-9235，1999年7月第28页)。
当在源极和漏极之间增强静电势垒有效(从而减小漏电流)时，与浅源极/漏极向外延(先前提到的制作的源极/漏极掺杂分布)一起的光晕/阱注入物就会对生产过程增加复杂性。要实现这些处理步骤。至少需要两道增加的光刻步骤，以及相关的情况，注入，测量等步骤。因为光刻是生产过程中最昂贵的处理步骤之一(若不是最昂贵的)，所以就大大提高了生产成本。光晕和阱注入物以及浅源极/漏极的外延会对器件的电性能带来也寄生电容和随机统计变化。
沟道掺杂分布或短沟道肖特基(Schottky)MOS器件在现有技术中仅受到非常有限的关注。J.R.Tucker讨论过极短沟道的SBMOS器件，并顺便提到
“…some doping of the semiconductor channel region will be requiredin order to suppress(1eakage)current…”。
见由J.R.Tucker，C.Wang，J.W.Lyding，T.C.Shen，G.C.Abeln所著的“Si上的纳米级MOSFET和STM图形化”，1994年的SSDM第322到324页；由J.R.Tucker，C.Wang，P.S.Carney，所著的“量子隧道基础上的硅场效应管”，1994年8月1日的“应用物理书函”第65卷第5号618页到620页。需要明确指出的是，Tucker并未讨论该采用怎样的方法引入沟道掺杂以抑制源极至漏极的漏电流。
O.T.Zhao是另一位明确阐述沟道掺杂以控制漏电流问题的作者。他的方法(基电的均匀掺杂在很高的级别(1017/cm3))是非常著名的短沟道器件的非优化的方法。虽然他成功地减小了漏电流，但他却是以提高源极/漏极至基片的电容为代价完成的。见由Q.T.Zhao，F.Klinkhammer，M.Dolle，L. Kappius，s.Mantl所著的“用于超短沟道肖特基势垒金属氧化物半导体场效应管的外延CoSi2/Si(100)的纳米图形化”，“应用物理快讯”1999年1月18日第74卷第3号第454页。
W.Saitoh报告了在SOI基片上建立的器件，但并未在内容中讨论基片掺杂。见由W.Saitoh，S.Yamagami，A.Itoh，M.Asada所著的“具有PtSi肖特基源极/漏极的35nm金属栅SOI-P-MOSFET”，Santa Barbara，CA，1999年6月28-30日召开的“器件研究会议”，论文II.A.6，第30页。
C.Wang提到了使用“在有源区的完全耗尽性杂质层”和“预注入完全耗尽性杂质的薄的亚表面层”以控制漏电流，但并未讨论横向作非均匀的杂质分布或在其方向上缺少杂质分布，或该怎样进行“层”的生产。见由C.Wang，JohnP.Snyder，J.R.Tucker所著的“少于40nm的PtSi肖特基源极/漏极金属氧化物半导体场效应管”，“应用物理书函”1999年2月22日第74卷第8号，第1174页上；由C.Wang，John P.Snyder，J.R.Tucker所著的“少于50nm的PtSi肖特基源极/漏极P-MOSFET”，1998年的“年度器件研究会议摘要”第72到73页上。
概述
列出了有关常规短沟道MOS晶体管的基片掺杂分布的文献并阐述了有关短沟道肖特基MOS器件的沟道掺杂分布问题上的工作的不足，申请的发明提供了具有很多优于目前现有技术点的新颖的且非明显的方法。
发明目的
因此，本发明的目的是(在其它之中)弥补现有技术的不足并对以下一个或多个目的起作用：
1.提供允许生产具有比现有生产技术更低成本，更高性能和更好容差性能制造拉沟道长度的MOSFET的系统和方法。
2.减少在集成MOSFET中的寄生双极性操作，由此减少被锁住和其它反常的行为。
3.提供适用于某些具有较高辐射强度场合的MOSFET器件。
在这些目的不应该被理解为限制本发明技术的同时，通常这些目的可通过在以下所讨论的公开发明来实现。
发明内容
综述
参考图3，本发明的典型实施例(300)由常规的MOS栅堆(303)(硅基片上二氧化硅上的栅极)、金属源极(301)和/或金属漏极(302)以及在垂直方向但非横向方向上剧烈变化的沟道杂质(304)简单组成。场氧化层(305)在电学上将器件相互绝缘。
沿着相应的金属源极/金属漏极(301，302)与硅基片(306)的界面存在的肖特基(或类似肖特基)势垒(307，308)起着内部阱或光晕注入物的作用，而且在不增加寄生电容的前体下起到这样的作用。它也排除了对浅源极/漏极外延的需要，使得金属源极/漏极为依赖于它自身的浅本质和较高的导电性。从而，通过同时去除光晕/所注入物和源极/漏极外延，可以大大降低了生产中的复杂性。这些也是优于常规构造沟道的MOS器件的优点。
由于肖特基势垒的原子级突变特性和该势垒非常一致且可重复的幅值，常规MOS器件所特有的两个统计变化源几乎全部去除。常规器件中通过离子注入引入杂质的随机统计本质，在注入杂质的位置和数量级中产生了巨大的变化。对于光晕/阱和源极/漏极杂质而言，确实是这样。引起在诸如沟道长度(L)、驱动电流和漏电流之类的器件参数中发生一定的随机变化。这些变化会增加电路设计的困难，而且经由于IC不符合性能指标而产生的损耗增加了生产成本。当由于每个器件所具有的硅的较小有效体积而减小沟道长度时，问题变得更为严重，从而平均去除统计变化的几率就变少了。
因为金属源极/金属漏极(代替常规的杂质掺杂的源极/漏极)具有自然的、非常一致的且含其位置和数量级与沟道长度无关的硅基片(306)的原子级突变的Scotty势垒(307，308)，又因为该势垒本质上起到光晕/阱注入物的作用(使这些注入物不是的必需的)，在源极/漏极和光晕/槽的注入过程中由于原子的随机代替而产生的统计变化就基本上消除了。这个事实是正确的，而且随着沟道长度减小，使得这个事实变得更加正确。
金属源极/金属漏极MOS结构的另一个益处是无条件的消除寄生双极增益。寄生双极增益是对源极/漏极和基片区使用相反的掺杂型的直接结果，而且能导致被锁住和其它有害的效应。当源电极/漏电极采用由金属构成时，便消除了该寄生增益。这使得金属源极/漏极结构成为(在其它物体中)高辐射环境的理想结构。
总体优势
本发明同现有技术相比通常提供了以下的益处：
1.降低了生产中的复杂性。不需要阱/光晕注入物和浅源极/漏极的外延。
2.由于没有阱/光晕注入物，而减小了电容。
3.由于没有阱/光晕注入物和源极/漏极的外延以及对源极和漏极使用了金属，所以减少了器件电子特性的随机/统计变化。
4.无条件地消除了寄生双极增益和相关的被锁效应
5.与常规MOS结构相比，增加了抗辐射的强度。
以上所列出的优势不应该被理解成限制了本发明的范围。然而，考虑到上列具有潜在可用的总体优势，业内的熟练人士都会意识到本发明所教授的许多应用机会。
附图说明
为了更加完整地理解本发明所提供的优点，将对以下的附图进行详细地说明，其中：
图1说明了现有技术的长沟道杂质掺杂源极/漏极器件；
图2说明了现有技术的短沟道、带阱注入物和源极/漏极延延的杂质掺杂源极/漏极器件；
图3说明了本发明适用于不带阱注入物的短沟道金属源极/漏极器件的典型实施例；
图4说明了本发明采用具有约200A屏蔽氧化层的注入的硅基片的制造工艺步骤的典型实施例；
图5说明了本发明在薄栅极氧化层上使用原位置图形化的硅掺杂膜的制造工艺步骤的典型实施例；
图6说明了本发明采用形成薄氧化侧壁以及将在栅、源极和漏极区域中的硅暴露制造工艺步骤典型实施例；
图7说明了本发明采用金属沉淀和solicidation退火的制造工艺步骤的典型
实施例；
图8说明了本发明采用从侧壁去除未反应金属的制造工艺步骤的典型实施例；
图9说明了本发明制造最终结构的工艺的典型实施例。分别对栅极、漏极/源极和沟道掺杂的N型器件使用原位掺杂磷的硅、铒化硅和铟沟道注入物。P型器件利用了原位置掺杂硼的硅、铂化硅和砷沟道注入物。沟道掺杂剂的浓度在垂直方向上变化很大但在横方向上变化不大。栅长度通常＜100nm，但也可以更长一点；
图10说明了显示生产高级MOSFET器件方法的典型的常规系统工艺流程图；
图11说明了显示生产高级MOSFET器件方法的典型的详细系统工艺流程图。
本发明较佳典型实施例的描述
典型的实施例
虽然本发明易受许多不同形式的实施例的影响，但在附图中所显示以及在此将详细描述所披露的本发明的较佳实施例都可理解为本发明原理的范例，而且不会将本发明广泛的应用范围局限于所讨论实施例。
本申请的多种创新的方法将特别参考本发明所相符的实施例来描述，其中，这些创新的方法能有利地适用于解决一些MOSFET器件系统和方法的特殊问题上。然而，应该理解的是，这些实施例仅仅是该创新方法中许多有效用途的的例子。总的来说，本申请说明书中所作的描述并不一定局限于多种要求的发明中的任一项。此外，一些描述也可以适用于本发明的一些特征，但不是全部特征。总的来说，除非特别表示以外，单个的元件可以表示多个；在不影响通用性下反之也同样。
定义
本文的所有讨论都和使用以下的定义：
不受限制的系统框/程序步骤
本发明可根据典型的系统框图和工艺流程图进行适当地描述。当这两项内容对业内熟练人士作充分的说明之后，业内熟练的人士就不会再被严格地局于本发明的范围。熟练的人士都会意识到，系统框图可在不影响通用性的条件下任意合和重新安排，而工艺步骤可以增加或删减以及重新安排以在不影响通用性的情况下获得相同的效果。从而，应该明白的是，所附的典型系统框图和程序流程图中所描绘的本发明只起到教授的目的，而且对业内的熟练人士来说，可根据预期的目标应用可再加工。
预定区域
以以下的所有讨论中，术语“预定区域”将被定义成围绕在有源器件(MOSFET)中心的中央区。因此，所有在MOSFET内容中提到的处理步骤都将产生栅、源极/漏极和/或沟道掺杂分布以及最接近预定区域或有源器件的中心的区域内的其它结构。本发明对发生在此内容之外、远离有源器件中心的内容未作任何限制。
应该指出的是，当预定区以MOSFET器件作一般性叙述时，这绝不会局限于本发明的范围。业内的熟练人士却意识到，任何能够调节电流流量的器件可认为其具有接近于有源载电流区的预定区域。
不受限制的MOSFET
本发明特别适合使用MOSFET半导体器件，但本方法的使用并不局限制于该特定的应用。其它的半导体器件，集成或非集成却可以适用于本发明的方法。因此，当本说明书根据“MOSFET”器件叙述时，此项应该被解释成广泛地包括任何调节电流流量的器件，该器件为具有两个或更多电接触节点的导电沟道。
不受限制的沟道长度
本发明特别适合在生产短沟道长度MOSFET的情况下使用，特别是在沟道长度＜100nm的范围内使用。然而，本发明的方法中并没有将本发明的方法局限于这些短沟道长度的器件上。本发明的提及的有效使用的方法可应用于任何尺寸的沟道长度。
不受限制的掺杂剂
这里的所有讨论中，将会提供采用有关MOSFET器件制造中各种不同的掺杂剂技术的例子。这些掺杂剂只是用于对本发明检索符的实施例进行说明，而不应该解释成限制了本发明中方法的范围。
然而，值得注意的是，本发明特别期望能使用本发明方法范围之内的砷、磷、锑、硼、铟和/或镓所构成的族中选出来的杂质原子。
不受限制的器件类型
业内的熟练工容易意识到，本发明并不局限于N型或P型器件的范围内，而是可以使用任一器件类型或两种器件类型。
不受限制的源极/漏极
本文的所有讨论中，将提供有关MOSFET器件制造中称为‘源极’和‘漏极’连接的例子。业内熟练人士将意识到，在任何给出的MOSFET结构，围绕这些接触点的术语可在不影响通用性的情况下交换，得‘源极’在本发明范围内在称有影响的情况下与‘漏极’的接触点互相交换。另外，业内熟练工将意识到，当本发明许多较佳实施例可被用于制造源极和漏极两种连接时，并没有要求这必须是实际操作中的例子。IC或类似电路封装中指定器件上的一个、两个源极/漏极的连接或无源极/漏极的连接却可使用本发明的方法来改进。
因此，术语‘源极’和‘漏极’应该被解释为包括各种不同的‘漏极’和‘源极’以及‘源极或漏极’和‘源极和漏极’。
不受限制的金属
本文的所有讨论中，将提供有关MOSFET器件制造中的金属的例子。本发明并不认为，关于使用何种类型金属的任何限制会影响本发明的方法。因此，特别预先考虑诸如钛、钴和类似金属之类常用的晶体管级的金属，以及稀有的金属和其它合金。在本披露中并没有限制本发明所使用的任何金属或合金。业内熟练人士将意识到，在本发明方法的实现中任何导电的互相连接的材料都可在不影响通用性的情况下使用。
然而，要注意的是，本发明特别预先考虑采用从由本发明方法的范围内的铂化硅、钯化硅、铱化硅和/或稀土硅化物中任一构成的族的材料所制成的源极/漏极。
不受限制的肖特基
本文所有讨论中，将会提供有关IC制造中涉及‘肖特基’势垒和类似连接的例子。本发明并不认为，关于使用何种类型的肖特基界面的任何限制会影响本发明的方法。因此，本发明特别预先考虑一些使用导电材料形式制成的连接类型。
此外，当常规的肖特基连接突变时，本发明特别预先考虑到杂某些情况下，界面层可用于在硅基片和实际肖特基势垒金属之间。因此，本发明特别考虑了‘类似肖特基’的连接以及在本发明实践中它们有用的等效连接。此外，界面层由具有导电性、半导电性和/或类似绝缘特性的材料构成。
不受限制的蚀刻技术
本文所有讨论中，将提供有关在IC制造工艺中用于去除氧化层和/或金属的多种蚀刻技术的例子。本发明并不限制用以获得典型的工艺流程中所描绘的效果的蚀刻技术的类型。这些蚀刻技术在该领域中已知都是大家所了解的。
工艺/方法
图4-9中说明了一种制造注入沟道、短沟道(＜100nm)金属源极/漏极MOS器件(400)的可行性工艺流程。当该典型的工艺流程正好作为本发明用途广泛的方法的范例时，将会证明，对业内熟练工来说，本发明所教授的基本概念是非常有意义的。该典型的工艺流程可如下所述：
1.参考图4，从具有将晶体管彼此电子性能绝缘的装置的硅基片(402)开始，形成屏蔽氧化层(401)(大约200A)厚，作为屏蔽氧化层。随后通过屏蔽的氧化层往硅中的预定深度(大约1000A左右)离子注入适当的沟道掺杂剂物质(403)(举例来说，砷和铟分别对应于P型器件和N型器件)。
2.参考图5，随后在氢氟酸中去除屏幕氧化层，再生长薄的栅极氧化层(501)(大约35A)形成。栅极氧化层的生长迅速被原位掺杂硅膜覆盖。硅膜是重掺杂的，例如，用于N型器件的磷和用于P型器件的硼。使用光刻技术和对氧化层高度选择的硅蚀刻技术，栅极(502)图形化，正如图5中所说明的工艺步骤(500)中所示。
3.随后，在硅栅极的端表面和侧壁热的生长薄氧化层(大约100A)。参考图6，接着采用非均质蚀刻方法去除水平表面上的氧化层(也从而暴露硅(601))，同时保存垂直平面上的氧化层。通过该方法，制成侧壁氧化层(602)，而且电激活在器件栅极和沟道区中的掺杂剂，正如图6所说明的工艺步骤(600)中所示。
4.参考图7，最后的步骤围绕在所有暴露的表面上沉淀适当的金属(适用于P型器件的铂和还用于N型器件的铒)作为覆盖膜(大约400A)。随后，薄膜在指定的时间指定的温度下退火(例如，400℃维持45分钟)，使得在所有金属与硅直接接触的地方，发生将金属转化成金属硅化物(701)的化学反应。与外硅表面(702)直接接触的金属不受影响，正如图7说明的工艺步骤(700)中所示的，
5.接下来，用用(适用于铂的王水，用于铒的硝酸)来去除不反应的金属，同时使金属硅化物不受影响。沟道注入的，短沟道肖特基势垒MOS器件现在已完成，并准备好了与栅极、源极和漏极的电接触，正如图8描绘的工艺步骤(800)中所示的。
这种工艺只是完成沟道注入的，金属源极/漏极肖特基MOS器件的一种可行性方法。业内熟练人士将意识到存在许多其它的变化和选择。
器件/系统
图9显示了本发明的较佳典型实施例。该实施例由铒化硅(904)作为源极/漏极区域的制成的N沟道器件和铂化硅(905)作为源极/漏极区域制成的P沟道器件组成的。
使用垂直变化、横向不变化的铟层(902)和砷层(903)分别作为N沟道和P沟道器件的沟道掺杂剂。使用这些掺杂剂原子是因为它们在到硅晶格中具有相对较低的扩散率(与磷和硼这另外两种沟道掺杂剂的可选的物质相比)。这样做可允许在制造器件过程中有较大的热平衡，从而在成品的特性中统计变化较小。
栅极分别由原位对应N型器件(906)的掺杂磷的多晶硅膜和对应P型器件(907)的掺杂硼的多晶膜制成。在本例中，使用磷和硼上因为它们具有较大的固溶度(相对于砷和铟)。电极通过使用原位的方法掺杂，其中，杂质原子与硅原子在同时沉淀。像这样的方法能获得非常大的掺杂浓度(大约1021/cm3)和薄膜厚度上的均匀分布。掺杂硅栅极的另外一种选择方法是离子注入。该方法受到几个实际问题的困扰，包括对薄栅极氧化层的充电损坏，以及需要重新分配高度非均匀的注入栅极掺杂剂以在栅极氧化层的界面上获取高掺杂等级。
栅极(906)和(907)在宽度(相当于沟道长度L)上小于100nm，由于其在该范围内，故胜于常规结构上的肖特基势垒结构的优势变得明显。这些优势包括：由于不需要阱注入物而简化了的工艺过程，以致于能减少生产的损耗、以及成品中的电容和统计变化。
器件通过热生长的氧化层(称为场氧化层)(901)而相互分开，该氧化层与沟道掺杂剂相连接起到将器件相互间电性能绝缘的作用。
在以上的描述包含许多详细说明的同时，这些并不应该被解释成对本发明范围上的限制，相反却是其中一个较佳实施例的典范。业内熟练的人士将意识到还有许多其它的可行性变化。例如，有很多源极/漏极金属的可行性候选物质。也同样有利于在金属和硅基片之间插入薄氧化层。硅基片本身也可用任何数量的其它半导体替代。另外，在层面或元件之间的分界面总可以被分级或插入其它材料或界面剂以提高性能。
统一化的工艺/系统制造
从上述的讨论中，本发明中实施的工艺和系统可如图10-11所示的流程图中所描绘的进一步统一化。
统一化的工艺/系统
参考图10，典型的统一化的MOSFET器件工艺制造流程(1000)从具有电性能绝缘的晶体管结构的半导体基片开始(1001)。在该基片上，沟道掺杂剂以一定的方式被引入，使掺杂剂浓度在垂直方向但不在横向上发生显著变化(1002)。一旦该步骤完成，可以在硅基片上制成栅极(1003)。最后，制成源极和/漏极电极，其中至少有一个是以肖特基或类似类似肖特基的方式与半导体基电相接触(1004)。
详细的工艺/系统
参考图11，典型的详细MOSFET器件工艺制造流程(1100)从具有电性能绝缘的晶体管的结构的半导体基片开始(1101)。在该基片上，沟道掺杂剂以一定的方式引入，使掺杂剂浓度在垂直方向而不是横向上发生显著的变化(1102)。一旦该步骤完成，就在硅基片上通过生长薄栅极绝缘层和沉淀导电膜制成了栅极绝缘体(1103)。
这时，完成了一系列的图形化和蚀刻步骤以形成栅极电极(1104)。接着，在一个或更多栅极电极的侧壁上制成一层或多层绝缘薄层以选择性地暴露器件除侧壁以外有效面积上的半导体基片(1105)。在器件所有的表面上沉淀金属薄膜(1106)，且器件进行热退火以在暴露的半导体表面上形成金属半导体合金(1107)。最后，从器件中除去不反应的金属，同时不影响金属半导体合金以制成已制成器件的局部互相连接点(1108)。
综述
实际上，本发明可总结成，基本结构是其源极和漏极之间的基片在横向上均匀掺杂，在垂直方向上非均匀掺杂，而且源极和/或漏极形成与基片接触的肖特基或类似肖特基的接触。
结论
已披露了短沟道长度、横向均匀掺杂的沟道、金属源极和漏极MOS器件结构以及制造方法。本发明提供了优于现有技术的许多优点，包括较低的生产成本、较好的器件性能和对器件参数更加紧密的控制。这些优点主要通过引入沟道掺杂分布来获得，该沟道掺杂分布是横向均匀而垂直方向非均匀，并且与金属源极/漏极区域相连，从而不需要光晕/槽注入物和浅源极/漏极的外延。寄生双极性增益也无条件地消除了。
本发明的这些特征使其成为许多应用场合的理想选择，包括高频和/或高辐射环境，但并不局限于此。

Claims (35)

  1. 虽然本发明的一个较佳实施例已在附图中描绘并在上述详细的描述中叙述过，仍然需要理解的是，本发明并不局限于被披露的实施例，而是能在不脱离以下如权利要求所陈述和定义的本发明精神的前体下作许多重新安排、修改和替代。
    权利要求
    1.一种MOSFET器件，其特征在于包括：
    (1)一种源极连接；
    (2)一种漏极连接；
    (3)一种在所述源极连接和所述漏极连接之间的基片，所述基片横向均匀掺杂而垂直方向非均匀掺杂；
    其中，所述源极和/或漏极连接形成连接所述基片的肖特基势垒。
  2. 2.如权利要求1所述的MOSFET器件，其特征在于，所述基片的长度小于或等于100nm。
  3. 3.如权利要求1所述的MOSFET器件，其特征在于，所述源极连接和/或所述漏极连接包括了在所述肖特基势垒中的界面层。
  4. 4.如权利要求3所述的MOSFET器件，其特征在于，所述基片的长度小于或等于100nm。
  5. 5.一种MOSFET器件，其特征在于包括：
    (1)一种源极连接结构；
    (2)一种漏极连接结构；
    (3)一种在所述源极连接结构和所述漏极连接结构之间的基片结构，所述基片结构在横向上均匀掺杂而垂直方向上非均匀掺杂；
    其中，所述源极连接结构和/或所述漏极连接结构形成连接所述基片结构的肖特基势垒。
  6. 6.如权利要求5所述的MOSFET器件，其特征在于，所述基片结构的长度小于或等于100nm。
  7. 7.如权利要求5所述的MOSFET器件，其特征在于，所述源极连接结构/漏极连接结构包括了在所述肖特基势垒结构中的界面层。
  8. 8.如权利要求7所述的MOSFET器件，其特征在于，所述基片结构的长度小于或等于100nm。
  9. 9.一种调节电流流量的器件，其特征在于包括：
    (1)一种半导体基片；
    (2)一种栅极；
    (3)源极和漏极，至少在某些邻近于所述栅极电极任一边的位置上形成带所述半导体基片的肖特基或类似肖特基的界面；
    (4)杂质原子，嵌入所述半导体基片内部并至少在接近所述栅极的区域内形成分布，使得所述杂质原子的浓度在平行于所述半导体基片的所述表面的方向上变化不显著，但在垂直于所述半导体基片的所述表面的方向上变化显著。
  10. 10.权利要求9的器件，其特征在于，所述源极和/或漏极包括在所述肖特基和/或类似所述肖特基的势垒中的界面层。
  11. 11.权利要求9的器件，其特征在于，所述源极和/或漏极是由铂化硅、钯化硅和铱化硅构成的族制成，而所述的杂质原子从由砷、磷和锑构成的族中选择。
  12. 12.权利要求9的器件，其特征在于，所述源极和/或漏极是由任一种稀土硅化物构成的族制成，而所述的杂质原子从由硼、铟和镓构成的族中选择。
  13. 13.权利要求9的器件，其特征在于，所述的栅极具有的宽度不超过100nm。
  14. 14.权利要求13的器件，其特征在于，所述源极和/或漏极是由铂化硅、钯化硅和铱化硅构成的族制成，而所述的杂质原子从由砷、磷和锑构成的族中挑选。
  15. 15.权利要求13的器件，其特征在于，所述源极和/或漏极从由任一种稀土硅化物构成的族制成，而所述的杂质原子从由硼、铟和镓构成的族中挑选。
  16. 16.一种MOSFET制造工艺包含：
    (a)选择具有电器分离的晶体管结构的半导体基片；
    (b)以一定的方式对所述基片引入沟道杂质，使杂质浓度在垂直方向上而不是在横向上显著变化；
    (c)在所述半导体基片上制成栅极；
    (d)在所述半导体基片上形成源极和/或漏极，至少有一电极与所述半导体基片形成肖特基或类似肖特基接触。
  17. 17.权利要求16的MOSFET制造工艺，其特征在于，所述制造的MOSFET器件具有的沟道长度小于或等于100nm。
  18. 18.权利要求16的工艺所制造的产品。
  19. 19.权利要求17的工艺所制造的产品。
  20. 20.一种MOSFET制造工艺，其特征在于包含：
    (a)选择具有电器分离的晶体管结构的半导体基片；
    (b)以一定的方式在所述基片中引入沟道杂质，使沟道浓度在垂直方向上而不是在横向上显著变化；
    (c)在所述半导体基片上生长薄栅极绝缘层并在所述的绝缘层上沉淀导电薄膜；
    (d)图形化并蚀刻所述导电膜以形成栅极；
    (e)在所述栅极的一个或更多侧壁上形成一个或更多绝缘薄层并暴露在所述MOSFET一个或更多除所述侧壁之外有效面积上的半导体基片；
    (f)在所述MOSFET的所有表面上沉淀金属薄膜；
    (g)对所述的MOSFET进行热退火以在所述的半导体表面的暴露面上形成金属半导体；
    (h)从所述MOSFET去除不反应的金属，同时留下与所述半导体基片接触的所述金属半导体合金。
  21. 21.权利要求20的MOSFET制造工艺，其特征在于，所述制造的MOSFET器件具有的沟道长度小于或等于100nm。
  22. 22.权利要求20的工艺所制造的产品。
  23. 23.权利要求21的工艺所制造的产品。
  24. 24.一种生产可调节电流流量的器件的工艺，其特征在于包含：
    (a)提供具有表面和内部区域的半导体基片，所述的表面具有指定为预定区域的某部分；
    (b)在所述半导体基片的所述内部区域内提供杂质原子，使得至少在接近于所述预定区的区域内，所述杂质原子的浓度在平行于所述半导体基片的所述表面的方向上变化不显著，但在垂直于所述半导体基片的所述表面的方向上变化显著；
    (c)至少在接近于所述预定区域的区域内形成栅极；
    (d)至少在接近于所述预定区的区域内形成源极和漏极，它们至少在某些接近于任何所述栅极两侧边缘的位置上形成对半导体基片的肖特基或类似肖特基的界面。
  25. 25.如权利要求24的工艺，其特征在于，所述源极和/或漏极从由铂化硅、钯化硅和铱化硅构成的族制成，而所述杂质原子从由砷、磷和锑构成的族中选择。
  26. 26.如权利要求24的工艺，其特征在于，所述源极和/或漏极是任一种稀土硅化物构成的族制成，而所述的杂质原子从由硼、铟和镓构成的族中选择。
  27. 27.如权利要求24的工艺，其特征在于，所述栅极电极具有的宽度不超过100nm。
  28. 28.如权利要求27的工艺，其特征在于，所述源极和/或漏极是由铂化硅、钯化硅和铱化硅构的族制成，而所述的杂质原子从由砷、磷和锑构成的族中选择。
  29. 29.如权利要求27的工艺，其特征在于，所述源极和/或漏极是由任一种稀土硅化物构成的族制成，而所述杂质原子从由硼、铟和镓构成的族中选择。
  30. 30.如权利要求24的工艺所制造的产品。
  31. 31.如权利要求25的工艺所制造的产品。
  32. 32.如权利要求26的工艺所制造的产品。
  33. 33.如权利要求27的工艺所制造的产品。
  34. 34.如权利要求28的工艺所制造的产品。
  35. 35.如权利要求29的工艺所制造的产品。
CNB008190194A 1999-12-16 2000-12-15 Mosfet器件系统和方法 Expired - Fee Related CN1222021C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/465,357 US6303479B1 (en) 1999-12-16 1999-12-16 Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
US09/465,357 1999-12-16

Publications (2)

Publication Number Publication Date
CN1434979A true CN1434979A (zh) 2003-08-06
CN1222021C CN1222021C (zh) 2005-10-05

Family

ID=23847484

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB008190194A Expired - Fee Related CN1222021C (zh) 1999-12-16 2000-12-15 Mosfet器件系统和方法

Country Status (10)

Country Link
US (7) US6303479B1 (zh)
EP (1) EP1238420A4 (zh)
JP (2) JP2003517210A (zh)
KR (1) KR20020082469A (zh)
CN (1) CN1222021C (zh)
AU (1) AU2267301A (zh)
CA (1) CA2393443A1 (zh)
IL (3) IL150250A0 (zh)
RU (1) RU2245589C2 (zh)
WO (1) WO2001045157A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446770A (zh) * 2011-10-12 2012-05-09 上海华力微电子有限公司 一种提高浮体动态随机存储单元写入速度的方法及结构
CN102723367A (zh) * 2012-06-29 2012-10-10 昆山工研院新型平板显示技术中心有限公司 一种氧化物半导体薄膜晶体管

Families Citing this family (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
US6303479B1 (en) * 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
US6784035B2 (en) * 2002-01-23 2004-08-31 Spinnaker Semiconductor, Inc. Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate
FR2805395B1 (fr) * 2000-02-23 2002-05-10 Centre Nat Rech Scient Transistor mos pour circuits a haute densite d'integration
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
US6534388B1 (en) * 2000-09-27 2003-03-18 Chartered Semiconductor Manufacturing Ltd. Method to reduce variation in LDD series resistance
DE10052208C2 (de) * 2000-10-20 2002-11-28 Advanced Micro Devices Inc Verfahren zur Herstellung eines Feldeffekttransistors mittels einer Justiertechnologie auf der Grundlage von Seitenwandabstandselementen
US6555453B1 (en) * 2001-01-31 2003-04-29 Advanced Micro Devices, Inc. Fully nickel silicided metal gate with shallow junction formed
US6466489B1 (en) * 2001-05-18 2002-10-15 International Business Machines Corporation Use of source/drain asymmetry MOSFET devices in dynamic and analog circuits
JP2002353182A (ja) * 2001-05-25 2002-12-06 Mitsubishi Electric Corp 半導体装置の洗浄方法および洗浄装置、ならびに半導体装置の製造方法
DE10137217A1 (de) * 2001-07-30 2003-02-27 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
WO2003015181A1 (en) * 2001-08-10 2003-02-20 Spinnaker Semiconductor, Inc. Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
US20060079059A1 (en) * 2001-08-10 2006-04-13 Snyder John P Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
US6541320B2 (en) * 2001-08-10 2003-04-01 International Business Machines Corporation Method to controllably form notched polysilicon gate structures
KR100425582B1 (ko) * 2001-11-22 2004-04-06 한국전자통신연구원 얕은 소오스/드레인 접합 영역을 갖는 모스 트랜지스터의제조방법
US6894355B1 (en) * 2002-01-11 2005-05-17 Advanced Micro Devices, Inc. Semiconductor device with silicide source/drain and high-K dielectric
DE10208728B4 (de) * 2002-02-28 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zur Herstellung eines Halbleiterelements mit unterschiedlichen Metallsilizidbereichen
EP1506579A2 (en) * 2002-05-16 2005-02-16 Spinnaker Semiconductor, Inc. Schottky barrier cmos device and method
US6974737B2 (en) * 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
SG125143A1 (en) * 2002-06-21 2006-09-29 Micron Technology Inc Nrom memory cell, memory array, related devices and methods
US7750389B2 (en) * 2003-12-16 2010-07-06 Micron Technology, Inc. NROM memory cell, memory array, related devices and methods
US20040041214A1 (en) * 2002-08-29 2004-03-04 Prall Kirk D. One F2 memory cell, memory array, related devices and methods
US6835619B2 (en) * 2002-08-08 2004-12-28 Micron Technology, Inc. Method of forming a memory transistor comprising a Schottky contact
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US7902029B2 (en) * 2002-08-12 2011-03-08 Acorn Technologies, Inc. Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
US7176483B2 (en) * 2002-08-12 2007-02-13 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US7208383B1 (en) 2002-10-30 2007-04-24 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor component
US6833307B1 (en) 2002-10-30 2004-12-21 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor component having an early halo implant
US20040087094A1 (en) * 2002-10-30 2004-05-06 Advanced Micro Devices, Inc. Semiconductor component and method of manufacture
EP1435648A1 (en) * 2002-12-30 2004-07-07 STMicroelectronics S.r.l. Process of making CMOS and drain extension MOS transistors with silicided gate
KR100508548B1 (ko) * 2003-04-16 2005-08-17 한국전자통신연구원 쇼트키 장벽 트랜지스터 및 그 제조방법
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6963121B2 (en) * 2003-05-15 2005-11-08 Koucheng Wu Schottky-barrier tunneling transistor
US6744111B1 (en) 2003-05-15 2004-06-01 Koucheng Wu Schottky-barrier tunneling transistor
JP2006526893A (ja) * 2003-06-03 2006-11-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ サーマルバジェットを低減する接合およびケイ化物の形成
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US20050012087A1 (en) * 2003-07-15 2005-01-20 Yi-Ming Sheu Self-aligned MOSFET having an oxide region below the channel
US7078742B2 (en) 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US6940705B2 (en) * 2003-07-25 2005-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor with enhanced performance and method of manufacture
US6936881B2 (en) 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US7112495B2 (en) 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US20050035410A1 (en) * 2003-08-15 2005-02-17 Yee-Chia Yeo Semiconductor diode with reduced leakage
US7071052B2 (en) * 2003-08-18 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Resistor with reduced leakage
EP1676322A2 (en) * 2003-09-19 2006-07-05 Spinnaker Semiconductor, Inc. Schottky barrier integrated circuit
CN1868045A (zh) * 2003-10-03 2006-11-22 斯平内克半导体股份有限公司 使用各向同性蚀刻工艺的肖特基势垒mosfet制造方法
WO2005038901A1 (en) * 2003-10-22 2005-04-28 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture
US7888201B2 (en) 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7050330B2 (en) * 2003-12-16 2006-05-23 Micron Technology, Inc. Multi-state NROM device
JP4011024B2 (ja) * 2004-01-30 2007-11-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7504328B2 (en) * 2004-05-11 2009-03-17 National University Of Singapore Schottky barrier source/drain n-mosfet using ytterbium silicide
US7042009B2 (en) * 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
CN101019236A (zh) * 2004-07-15 2007-08-15 斯平内克半导体股份有限公司 金属源极功率晶体管及其制造方法
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060125041A1 (en) * 2004-12-14 2006-06-15 Electronics And Telecommunications Research Institute Transistor using impact ionization and method of manufacturing the same
KR100670803B1 (ko) * 2004-12-21 2007-01-19 한국전자통신연구원 쇼키 장벽 금속 산화물 반도체 전계 효과 트랜지스터의양극 전도성을 이용한 소자
JP2006196646A (ja) * 2005-01-13 2006-07-27 Renesas Technology Corp 半導体装置及びその製造方法
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
JP2008226862A (ja) * 2005-05-11 2008-09-25 Interuniv Micro Electronica Centrum Vzw シリサイド化されたゲート電極の仕事関数を調節する方法
US7504329B2 (en) * 2005-05-11 2009-03-17 Interuniversitair Microelektronica Centrum (Imec) Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET
US7176537B2 (en) 2005-05-23 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS with metal-gate and Schottky source/drain
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
JP2007036148A (ja) * 2005-07-29 2007-02-08 Toshiba Corp 半導体装置製造方法
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7737532B2 (en) * 2005-09-06 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Schottky source-drain CMOS for high mobility and low barrier
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
WO2007047429A1 (en) * 2005-10-12 2007-04-26 Spinnaker Semiconductor, Inc. A cmos device with zero soft error rate
KR100653711B1 (ko) * 2005-11-14 2006-12-05 삼성전자주식회사 쇼트키 배리어 핀 펫 소자 및 그 제조방법
US7250666B2 (en) * 2005-11-15 2007-07-31 International Business Machines Corporation Schottky barrier diode and method of forming a Schottky barrier diode
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
KR100699462B1 (ko) * 2005-12-07 2007-03-28 한국전자통신연구원 쇼트키 장벽 관통 트랜지스터 및 그 제조방법
JP2007158300A (ja) * 2005-12-07 2007-06-21 Korea Electronics Telecommun 低いショットキー障壁貫通トランジスタ及びその製造方法
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
FR2897202B1 (fr) * 2006-02-08 2008-09-12 St Microelectronics Crolles 2 Transistor mos a barriere de schottky sur film semi-conducteur entierement appauvri et procede de fabrication d'un tel transistor.
JP2007281038A (ja) * 2006-04-03 2007-10-25 Toshiba Corp 半導体装置
US7566951B2 (en) * 2006-04-21 2009-07-28 Memc Electronic Materials, Inc. Silicon structures with improved resistance to radiation events
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US20080093631A1 (en) * 2006-10-05 2008-04-24 Chi Dong Z Contact structure for semiconductor devices
KR100770012B1 (ko) * 2006-11-29 2007-10-25 한국전자통신연구원 쇼트키 장벽 관통 트랜지스터 및 그 제조방법
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
US20080191285A1 (en) * 2007-02-09 2008-08-14 Chih-Hsin Ko CMOS devices with schottky source and drain regions
US7858505B2 (en) * 2007-05-04 2010-12-28 Freescale Semiconductor, Inc. Method of forming a transistor having multiple types of Schottky junctions
KR100945508B1 (ko) * 2007-11-16 2010-03-09 주식회사 하이닉스반도체 제로 캐패시터 램 및 그의 제조방법
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
FR2930073B1 (fr) * 2008-04-11 2010-09-03 Centre Nat Rech Scient Procede de fabrication de transistors mosfet complementaires de type p et n, et dispositif electronique comprenant de tels transistors, et processeur comprenant au moins un tel dispositif.
US7863143B2 (en) * 2008-05-01 2011-01-04 International Business Machines Corporation High performance schottky-barrier-source asymmetric MOSFETs
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US7936040B2 (en) * 2008-10-26 2011-05-03 Koucheng Wu Schottky barrier quantum well resonant tunneling transistor
JP4911158B2 (ja) * 2008-10-30 2012-04-04 ソニー株式会社 半導体装置および固体撮像装置
US20120104502A1 (en) * 2009-03-31 2012-05-03 Jx Nippon Mining & Metals Corporation Method of producing semiconductor device, and semiconductor device
US9054194B2 (en) 2009-04-29 2015-06-09 Taiwan Semiconductor Manufactruing Company, Ltd. Non-planar transistors and methods of fabrication thereof
US8178939B2 (en) * 2009-06-21 2012-05-15 Sematech, Inc. Interfacial barrier for work function modification of high performance CMOS devices
WO2011055645A1 (en) 2009-11-06 2011-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8436422B2 (en) 2010-03-08 2013-05-07 Sematech, Inc. Tunneling field-effect transistor with direct tunneling for enhanced tunneling current
CN101866953B (zh) * 2010-05-26 2012-08-22 清华大学 低肖特基势垒半导体结构及其形成方法
US8513765B2 (en) 2010-07-19 2013-08-20 International Business Machines Corporation Formation method and structure for a well-controlled metallic source/drain semiconductor device
US8957462B2 (en) * 2010-12-09 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an N-type transistor with an N-type semiconductor containing nitrogen as a gate
US8610233B2 (en) 2011-03-16 2013-12-17 International Business Machines Corporation Hybrid MOSFET structure having drain side schottky junction
US9001564B2 (en) 2011-06-29 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method for driving the same
US8797512B2 (en) * 2011-09-15 2014-08-05 Advanced Scientific Concepts, Inc. Automatic range corrected flash ladar camera
US8803242B2 (en) * 2011-09-19 2014-08-12 Eta Semiconductor Inc. High mobility enhancement mode FET
US9576949B2 (en) * 2012-09-05 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Diode formed of PMOSFET and schottky diodes
DE102012215846A1 (de) * 2012-09-06 2014-03-06 Continental Automotive Gmbh Batterieanordnung zum Betrieb elektrischer Verbraucher in einem Fahrzeug zur Gefahrgutbeförderung
US8796098B1 (en) * 2013-02-26 2014-08-05 Cypress Semiconductor Corporation Embedded SONOS based memory cells
US9059156B2 (en) * 2013-09-30 2015-06-16 Intermolecular, Inc. Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach
KR102236555B1 (ko) 2014-11-11 2021-04-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10510869B2 (en) 2016-05-06 2019-12-17 Silicet, LLC Devices and methods for a power transistor having a Schottky or Schottky-like contact
US9947787B2 (en) 2016-05-06 2018-04-17 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
US10170627B2 (en) 2016-11-18 2019-01-01 Acorn Technologies, Inc. Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height
US10483380B2 (en) * 2017-04-20 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
RU2752291C2 (ru) * 2018-01-17 2021-07-26 Интел Корпорейшн Устройства, основанные на избирательно эпитаксиально выращенных материалах iii-v групп
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US11417762B2 (en) 2019-06-26 2022-08-16 Skyworks Solutions, Inc. Switch with integrated Schottky barrier contact
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
RU2743225C1 (ru) * 2020-09-14 2021-02-16 Акционерное общество "Научно-производственное предприятие "Исток" имени А.И. Шокина" (АО "НПП "Исток" им. Шокина") Полевой транзистор с барьером шотки
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053924A (en) 1975-02-07 1977-10-11 California Linear Circuits, Inc. Ion-implanted semiconductor abrupt junction
US4300158A (en) 1977-07-18 1981-11-10 Hazeltine Corporation Process control apparatus
US4300152A (en) * 1980-04-07 1981-11-10 Bell Telephone Laboratories, Incorporated Complementary field-effect transistor integrated circuit device
USRE32613E (en) * 1980-04-17 1988-02-23 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
SE8101994L (sv) * 1981-03-27 1982-09-28 Tove Per Arne Elektronisk krets med schottky-felttransistor med kontaktelement med olika schottky-barrierhojd
US4485550A (en) * 1982-07-23 1984-12-04 At&T Bell Laboratories Fabrication of schottky-barrier MOS FETs
JPS5947767A (ja) * 1982-09-10 1984-03-17 Nippon Telegr & Teleph Corp <Ntt> Ｍｉｓ形半導体素子
US4513309A (en) * 1982-11-03 1985-04-23 Westinghouse Electric Corp. Prevention of latch-up in CMOS integrated circuits using Schottky diodes
JPH0810763B2 (ja) * 1983-12-28 1996-01-31 株式会社日立製作所 半導体装置
JPS62500061A (ja) * 1984-08-24 1987-01-08 アメリカン テレフオン アンド テレグラフ カムパニ− ショットキ−層電極を持つｍｏｓトランジスタ
JPS6099553U (ja) * 1984-10-25 1985-07-06 富士通株式会社 半導体装置
FR2582445B1 (fr) * 1985-05-21 1988-04-08 Efcis Procede de fabrication de transistors mos a electrodes de siliciure metallique
US5834793A (en) * 1985-12-27 1998-11-10 Kabushiki Kaisha Toshiba Semiconductor devices
JPS62229873A (ja) * 1986-03-29 1987-10-08 Hitachi Ltd 薄膜半導体装置の製造方法
DE4001350C2 (de) * 1989-01-18 1993-10-07 Nissan Motor Halbleitereinrichtung
JPH02188967A (ja) * 1989-01-18 1990-07-25 Nissan Motor Co Ltd 半導体装置
US5079182A (en) 1990-04-02 1992-01-07 National Semiconductor Corporation Bicmos device having self-aligned well tap and method of fabrication
JP2606404B2 (ja) * 1990-04-06 1997-05-07 日産自動車株式会社 半導体装置
KR960001611B1 (ko) 1991-03-06 1996-02-02 가부시끼가이샤 한도다이 에네르기 겐뀨쇼 절연 게이트형 전계 효과 반도체 장치 및 그 제작방법
US5250834A (en) * 1991-09-19 1993-10-05 International Business Machines Corporation Silicide interconnection with schottky barrier diode isolation
JP3118063B2 (ja) * 1992-03-23 2000-12-18 ローム株式会社 不揮発性記憶素子およびこれを利用した不揮発性記憶装置、ならびに不揮発性記憶素子の製造方法
US5323053A (en) * 1992-05-28 1994-06-21 At&T Bell Laboratories Semiconductor devices using epitaxial silicides on (111) surfaces etched in (100) silicon substrates
US5294814A (en) * 1992-06-09 1994-03-15 Kobe Steel Usa Vertical diamond field effect transistor
JPH0697109A (ja) 1992-09-16 1994-04-08 Fujitsu Ltd 半導体装置
US5338698A (en) * 1992-12-18 1994-08-16 International Business Machines Corporation Method of fabricating an ultra-short channel field effect transistor
US5444302A (en) 1992-12-25 1995-08-22 Hitachi, Ltd. Semiconductor device including multi-layer conductive thin film of polycrystalline material
US5323528A (en) * 1993-06-14 1994-06-28 Amistar Corporation Surface mount placement system
US5663584A (en) * 1994-05-31 1997-09-02 Welch; James D. Schottky barrier MOSFET systems and fabrication thereof
US6268636B1 (en) * 1994-05-31 2001-07-31 James D. Welch Operation and biasing for single device equivalent to CMOS
US5760449A (en) * 1994-05-31 1998-06-02 Welch; James D. Regenerative switching CMOS system
US5665993A (en) * 1994-09-29 1997-09-09 Texas Instruments Incorporated Integrated circuit including a FET device and Schottky diode
JP2938351B2 (ja) 1994-10-18 1999-08-23 株式会社フロンテック 電界効果トランジスタ
TW304301B (zh) 1994-12-01 1997-05-01 At & T Corp
US5555993A (en) * 1995-02-24 1996-09-17 Borkowski; James T. Beverage can and pivotal, screen guard opener system
FR2749977B1 (fr) * 1996-06-14 1998-10-09 Commissariat Energie Atomique Transistor mos a puits quantique et procedes de fabrication de celui-ci
US5882993A (en) * 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same
TW333713B (en) 1996-08-20 1998-06-11 Toshiba Co Ltd The semiconductor device and its producing method
JP3262752B2 (ja) * 1997-03-28 2002-03-04 松下電器産業株式会社 半導体装置の製造方法
US5883010A (en) * 1997-08-07 1999-03-16 National Semiconductor Corporation Method for protecting nonsilicided surfaces from silicide formation using spacer oxide mask
US5952701A (en) * 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
JP4213776B2 (ja) * 1997-11-28 2009-01-21 光照 木村 Ｍｏｓゲートショットキートンネルトランジスタおよびこれを用いた集積回路
US6160282A (en) * 1998-04-21 2000-12-12 Foveon, Inc. CMOS image sensor employing silicide exclusion mask to reduce leakage and improve performance
JP3378512B2 (ja) 1998-10-16 2003-02-17 株式会社東芝 半導体装置
JP3408762B2 (ja) * 1998-12-03 2003-05-19 シャープ株式会社 Ｓｏｉ構造の半導体装置及びその製造方法
US6303479B1 (en) * 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
US6784035B2 (en) * 2002-01-23 2004-08-31 Spinnaker Semiconductor, Inc. Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate
US20030032270A1 (en) * 2001-08-10 2003-02-13 John Snyder Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate
JP3675303B2 (ja) * 2000-05-31 2005-07-27 セイコーエプソン株式会社 静電気保護回路が内蔵された半導体装置及びその製造方法
KR100439398B1 (ko) * 2001-05-22 2004-07-09 주식회사 멀티채널랩스 압전트랜스를 이용한 디지탈 콘트롤 전자식 안정기
US6509609B1 (en) * 2001-06-18 2003-01-21 Motorola, Inc. Grooved channel schottky MOSFET
WO2003015181A1 (en) * 2001-08-10 2003-02-20 Spinnaker Semiconductor, Inc. Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
US6974737B2 (en) * 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
US6833556B2 (en) * 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
JP4439358B2 (ja) * 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
CN1868045A (zh) * 2003-10-03 2006-11-22 斯平内克半导体股份有限公司 使用各向同性蚀刻工艺的肖特基势垒mosfet制造方法
WO2005038901A1 (en) * 2003-10-22 2005-04-28 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446770A (zh) * 2011-10-12 2012-05-09 上海华力微电子有限公司 一种提高浮体动态随机存储单元写入速度的方法及结构
CN102723367A (zh) * 2012-06-29 2012-10-10 昆山工研院新型平板显示技术中心有限公司 一种氧化物半导体薄膜晶体管

Also Published As

Publication number Publication date
EP1238420A1 (en) 2002-09-11
KR20020082469A (ko) 2002-10-31
CN1222021C (zh) 2005-10-05
US20010024847A1 (en) 2001-09-27
US6303479B1 (en) 2001-10-16
US20030008444A1 (en) 2003-01-09
WO2001045157A1 (en) 2001-06-21
US20100032771A1 (en) 2010-02-11
RU2002118823A (ru) 2004-03-10
EP1238420A4 (en) 2004-08-18
US6495882B2 (en) 2002-12-17
US7052945B2 (en) 2006-05-30
IL150250A (en) 2006-09-05
US20030139002A1 (en) 2003-07-24
US20050051815A1 (en) 2005-03-10
JP2003517210A (ja) 2003-05-20
IL176106A0 (en) 2006-10-05
US6744103B2 (en) 2004-06-01
IL150250A0 (en) 2002-12-01
IL176106A (en) 2009-11-18
JP2007049182A (ja) 2007-02-22
AU2267301A (en) 2001-06-25
RU2245589C2 (ru) 2005-01-27
US20110175160A1 (en) 2011-07-21
CA2393443A1 (en) 2001-06-21

Similar Documents

Publication Publication Date Title
CN1222021C (zh) Mosfet器件系统和方法
CN1317772C (zh) 半导体器件及其制造方法
CN1222986C (zh) 半导体装置的制造方法和半导体装置
CN1309033C (zh) 具有鳍片结构的半导体元件及其制造方法
CN1282253C (zh) 具有小袋的半导体器件及其制造
CN1280918C (zh) 参考电压半导体
CN1501461A (zh) 半导体器件及其制造方法
CN1855545A (zh) Mos晶体管、cmos集成电路器件及相关制造方法
CN1967871A (zh) 半导体装置及其制造方法
CN1240131C (zh) 半导体装置及其制造方法
CN1459837A (zh) 半导体器件中晶体管的形成方法
CN1257554C (zh) 金属氧化物半导体晶体管及其制造方法
CN1976033A (zh) 半导体器件及其制造方法
CN1620729A (zh) 具有与应变半导体基片形成肖特基或肖特基类接触的源极和/或漏极的场效应晶体管
CN1825551A (zh) 横向双扩散金氧半导体元件及其制造方法
CN1761071A (zh) 半导体器件及其制造方法
CN1081832C (zh) 制造金属氧化物半导体场效应晶体管的方法
CN1941418A (zh) 存储单元以及具有该存储单元的半导体非易失性存储器的结构
WO2023221552A1 (zh) 肖特基晶体管、二极管、冷源半导体结构及其制备方法
CN1144273C (zh) 半导体器件及其制造方法
CN1291484C (zh) 半导体装置及其制造方法
CN1499577A (zh) 制造半导体器件的方法
CN1574293A (zh) 半导体集成电路器件的制造方法和半导体集成电路器件
CN1469478A (zh) 半导体集成电路及其制造方法
US20060244052A1 (en) Short-channel schottky-barrier MOSFET device and manufacturing method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20051005

Termination date: 20121215