CN1416593A - 电子器件封装 - Google Patents

电子器件封装 Download PDF

Info

Publication number
CN1416593A
CN1416593A CN01806244A CN01806244A CN1416593A CN 1416593 A CN1416593 A CN 1416593A CN 01806244 A CN01806244 A CN 01806244A CN 01806244 A CN01806244 A CN 01806244A CN 1416593 A CN1416593 A CN 1416593A
Authority
CN
China
Prior art keywords
wire
lead
integrated circuit
semiconductor integrated
circuit die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN01806244A
Other languages
English (en)
Inventor
M·费瑟白
J·L·德哈文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxwell Electronic Components Group Inc
Original Assignee
Maxwell Electronic Components Group Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Maxwell Electronic Components Group Inc filed Critical Maxwell Electronic Components Group Inc
Publication of CN1416593A publication Critical patent/CN1416593A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)

Abstract

一种密封涂敷的器件(10)，它包括一半导体集成电路印模(16)；包含无机材料的第一层，该第一层(300)包裹集成电路印模(16)，第二层(400)，该第二层也包裹集成电路印模(16)。这种器件的形成包括下述步骤：配制半导体集成电路印模(16)；施加包含无机材料的第一层(300)，所述第一层(300)包裹半导体集成电路印模(16)；施加第二层(400)，所述第二层(400)包裹集成电路印模(16)。

Description

电子器件封装
发明背景
本发明涉及电子器件封装，特别是涉及电子器件的密封封装。更特别的是本发明涉及电子器件封装中的多层密封涂敷。
半导体集成电路是当今大多数电子系统中的关键器件。这些半导体集成电路已经在各种领域广泛使用。历史上，制造商设计了二种形式的半导体集成电路。一种是以非密封的塑料封装形式封装的器件(塑性封装微电子(PEM)器件)，如模制环氧、硅酮或者苯酚类，另一种是密封陶瓷封装的器件。密封陶瓷封装常常用在很灵敏的、环境恶劣的场合和/或要求高可靠性的应用上，诸如军事应用，包括武器系统；空间应用，像用在地球轨道卫星上；宇航应用；耐用的商业和医疗应用以及运输应用，像汽车和航空电子应用等。
至今，所述的密封陶瓷封装所解决的一个问题是避免湿气、离子和其它杂质(包括氧气)侵入封装的关键部位，例如引线接合位置，以及侵入半导体集成电路印模(die)中。这种杂质的入侵能引起氧化和其它对受影响的结构完整性的破坏，从而导致器件失效。在塑料封装器件中，通过在冲模时产生的裂缝和空隙以及通过塑料自身的扩散的情况中，很容易发生这种入侵，这二种情况均形成从外界环境到封装内部的通道。
问题是，近来器件制造商为了经济的原因，已经停止生产陶瓷封装器件，因此，遗留下了对于敏感的应用领域需要高可靠性器件的机构而言却没有合适的器件可用的问题。微电子电路极易受入侵塑料封装器件的气体、化学品和粒子的影响。与该敏感性相关的缺陷包括：湿气引起的腐蚀，化学物质破坏引线接合、电路内部和器件其它相关的方面。再则，在器件封装以前，在注模或其它方式制造出的封装中存在的粒子会划伤半导体集成电路印模表面，可能会切断引线接合并引起器件内部的短路/开路，也会与引线接合、导线或集成电路印模起反应或对它们进行侵蚀。
因此，密封封装对杂质会危及器件的整体功能的应用场合，或者在极端环境中的长期可靠和/或工作的应用场合来说是需要。
如上面所说，现在要解决这些问题的方案是使用陶瓷封装器件。陶瓷封装技术提供了很多实体所需要的密封封装和长期可靠性。但是，这些封装的缺陷是比类似的塑料封装要昂贵，重量更重并要求专门的制造设备来生产。尽管陶瓷封装器件的确有效地解决了密封问题，但它提供的器件的可靠性和耐用性常常超出了大多数应用的实际需要。
相反，塑料封装器件的主要优点在于它们与其它现在所采用的工艺相比，具有更便宜和更容易进行大规模生产的优点。但是，与陶瓷封装器件不同，塑料封装器件最大的失效百分率直接或间接地与其内在密封性不足及与所用的制造技术相关。在高可靠性应用中的塑料封装器件现在的使用者既要为了劣质产品的保养而负担较高的成本，还要承受长期可靠性不足的损害。
塑料封装器件的另一个优点在于与陶瓷相比，由于其较低的塑料介电常数，它们可在较高频率下工作。另外，塑料封装器件可有较小的尺寸，使元件更紧凑地排列在一起从而降低传播延迟。而且，塑料封装器件使用的铜引线比在陶瓷封装器件引线中使用的科伐合金的导电率和热导率更好。
因为塑料中的湿气会变化，从而改变封装的介电常数并使半导体集成电路印模的工作速度改变，因此，陶瓷封装器件比塑料封装器件更稳定地在高频工作。
由于添加了增塑剂，依靠所提高的渗透性，增加了在低应力塑料配方方面的灵活性。
一种代替陶瓷封装器件的方式是使用半导体集成电路印模自身的“圆片—级”涂层，这使制造工艺更复杂，也带来了工程技术上的挑战。涂层的印模级应用提高了半导体集成电路印模的密封性和器件结构可靠性，而且成本低，能与现在的生产设施相结合。不幸的是，这种处理必须在半导体集成电路印模从圆片上切下来以前作为制造步骤执行，因此要求改变“制造”工艺。问题是，一旦半导体集成电路印模从圆片上切下，半导体集成电路印模的边缘曝露出来并易受杂质影响。而且，半导体集成电路印模表面上的焊接区必须曝露(例如为了引线接合)，因此进一步产生易受杂质影响的区域。因此，缺点在于这种方式对保护引线和引线接合没有帮助，一个节点的杂质就会导致故障。美国专利No 5,780,163，颁发给Camilletti等人，提供了“圆片—级”涂敷的例子。
密封涂层也已用到半导体集成电路印模和引线接合上，这是在印模粘合到其附属基片上，并且引线经引线接合到半导体集成电路印模和导线上以后进行的。这些密封涂层使用氮化硅等离子化学气相淀积以避免湿气污染器件。这种处理也可以用于淀积金刚石(如碳)、氧化硅和其它绝缘材料。这种密封涂层类型的一个例子出现在颁发给Yamazaki等人的美国专利No.5,096,851中。
为了允许引线接合变形而不短路和减少与相对长度短的引线相关的高坚韧性的要求，在封装前，单层聚对苯二甲基涂层(聚对-苯二甲基)已用于半导体集成电路印模和引线接合上。颁发给Zechmans的美国专利No.5,824,568描述了单层聚对苯二甲基涂层。
双层和三层涂层技术也已经开发出来以使用包括聚对苯二甲基/BCB/二氧化硅、聚对苯二甲基/Al2O3和聚对苯二甲基/SiO2来提供湿气和氧气的阻挡层。在这个方法中，先涂上聚对苯二甲基层，然后施加一层或多层后续陶瓷层。
发明内容
本发明优势是提供一种密封封装半导体集成电路的方法。
本发明可以在一个实施例中表征为一种密封涂敷器件，它包括半导体集成电路印模；包含无机材料的第一层，该第一层包裹半导体集成电路印模；以及第二层，该第二层也包裹半导体集成电路印模。
在另一实施例中，本发明可表征为一种制造密封涂层器件的方法。该方法包括：配制半导体集成电路印模；施加包含一无机材料的第一层，该第一层包裹半导体集成电路印模；并且施加第二层，该第二层也包裹半导体集成电路印模。
附图说明
关于本发明的上述的和其它方面的一些特点和优点通过下面结合附图所作的描述会变得更清楚。
图1A是示意出典型的塑料封装器件的截面图，该器件包括塑料封装、印模附属基片、半导体集成电路印模、引线、引线接合和导线。
图1B是例如图1中塑料封装器件的局部截面图，表明由于缺乏密封性而影响这种塑料封装器件的失效模型。
图2是印模/引线/导线结构的示意截面图，这种结构可以在根据本发明的第一个实施例应用双重涂敷前先行装配。
图3表示具有无机涂层施加在其上的印模/引线/导线结构的横截面图。
图4表示具有在无机涂层上施加的印模/引线/导线结构上再施加无机涂层的印模/引线/导线结构的横截面图。
图5是表明具有双重涂层的印模/引线/导线结构的横截面图，即其上的无机涂层和有机涂层包裹在塑料包裹层中。
图6是描述在图2至图5中所用的方法的流程图。
图7是表示塑料封装器件的截面图，包括有塑料封装，半导体集成电路印模、塑料封装中的引线和导线的印模附属基片由无机涂层封装。
图8是表示具有无机涂层和有机涂层的印模/基片/引线/导线/封装结构的横截面图，无机涂层将该结构封装，而有机涂层涂敷在无机涂层上。
图9是描述在图7到图9中所用的步骤的流程图。和
图10是塑料封装实例一种变化的透视装配图，该实例得益于图2到图8的实施例。
图11是图10的塑料封装实例的另一种变化的透视装配图；
图12是一种塑料封装器件变化的局部截面上的透视图，示出该器件如图4所示有印模/引线/导线结构，该结构具有无机涂层和有机涂层，无机涂层将该结构封装，而在其上面再涂以有机涂层；进一步还表示了如图5所述的封装在塑料封装内的印模/引线/导线结构，形成印模/基片/引线/导线/封装结构，该结构用另一种无机涂层对其进行封装，而另一有机涂层涂在其它无机涂层上，如图8所示。
相应的参考符号指出了所有几个附图中的相应的组成部分。
具体实施方式
下面所描述的目前实施本发明的最好模式并没有限制的意思，其目的只是为了描述本发明的原理，本发明的范围应参照权利要求书确定。
首先参见图1A，它表示一塑料封装结构(或塑料包裹微电子(PEM)器件)的横截面，它包括塑料封装、印模附属基片、半导体集成电路、引线、引线接合和导线。实际上，本领域的技术人员熟知，在塑料封装结构装配之前，导线已构成导线框部分。导线框固定导线并使导线排成行，直到在导线的各个内部端点通过塑料封装对导线进行包裹。
在包裹之前，印模和印模附属基片位于导线框的中心附近，接近导线的内端点，而引线接合用普通方法形成，例如在集成电路印模上的焊接点和导线的内端点之间用超声焊接。这些引线接合是通过将每根引线的第一端点与印模上的各个焊接点焊接，并通过每根引线的第二端点与导线各个内端点的焊接来形成。
一旦所有的引线焊接到相应的焊接点和导线的内端点，最终结构(象图2所示)就包裹在塑料封装中，例如通过注模。这种最终结构的包裹包括保留从塑料封装中曝露和伸出在外的导线外端，以便可用于通过诸如将导线外端与印刷电路板焊接的方法连接一电子路系统。在这注模处理中，引线自由部分(即中间段)的移动是代表性的。
正如本领域熟练技术人员所能了解的，对塑料封装系统或者塑料封装集成电路器件来说，上面描述的装配处理仅代表本领域已知的一种塑料封装器件，一种双列直插式管脚器件(dual inline pin device)。许多其它例子，诸如倒装晶片器件、球面格栅阵列器件、针栅阵列器件、底部芯片底座器件、有引线芯片底座器件、无引线芯片底座器件、四芯扁平(quad-flat)封装器件、薄四芯扁平封装器件、晶片承载J接头(J-bend)器件、单列直插式管脚器件、DIL-接头-SIL器件、很小圆周阵列器件、晶片尺度(chip scale)封装器件和许多类似的器件，都得益于下面描述的先进技术。因此，下面描述的图中以及例子中的塑料封装半导体集成电路应该仅理解为示例。
上面描述的塑料封装半导体集成电路存在的问题是易受浸剂和湿气及其它杂质，诸如氧气的影响，这可能腐蚀引线、引线接合和半导体集成电路印模。这些杂质通过裂纹进入塑料封装中，这些裂纹可能出现在塑料封装和导线的外端之间，在引线的外端点引出塑料封装的地方；在某些情况，可以通过塑料封装本身的扩散侵入。
参见图1B，这一局部横截面图说明了这里描述的实施例所解决的各种失效方式。这些模式包括湿气和离子通过塑料封装、封装分层的渗透，塑料封装、球压焊断裂、封装裂纹等中的试剂化学污染。
在所有塑料封装器件中，湿气进入的主要途径之一是从导线引出塑料封装的地方进入。金属和塑料之间的粘附力不很好，部分是因为加到树脂中的脱模剂，该脱模剂能较容易得从模具中移去经处理的部分。由该金属/塑料分隔引起的狭窄空隙导致很高的毛细力，能使湿气沿引线接合进入封装，最终到达印模。想要有效地封住该空隙是非常困难的，因为弯曲导线或在焊接期间加热导线会破坏这脆弱的密封。
图2到图6表示根据这里所阐述密封半导体集成电路印模、引线和引线接合的一种方法以避免杂质的入侵，并且因此防止塑料封装系统的污染和最终的失效。
接下来参见图2(在图6的步骤)，它表示的是由印模、引线、引线接合和导线(如上面所述，导线在这里是导线框部分)组成的组件。该组件(例如可以用在图1的塑料封装系统中)也是本实施例的一个可能的起点。
正如可见到的，引线将在集成电路印模上表而的各焊接点和导线框的各导线之间电学连接起来。
引线焊接到焊接点以及导线可以以普通的方法实现，例如本领域熟知的超声波焊接。
然后参考图3(图6中步骤)，它表示的是由集成电路印模、引线、引线接合和导线组成的组件。也表示了双重涂层的第一层。双重涂层的第一层是像陶瓷一类的无机材料层以包裹半导体集成电路印模、引线接合、引线和导线的内端点。
用双重涂层的第一层包裹集成电路印模、引线、引线接合和导线(即使用像陶瓷一类的无机材料)最好通过非视线处理，诸如CVD、PECVD、金属有机化学汽相沉积和在约300℃之下温度进行喷镀来实现。也可使用溶胶凝胶技术，但这是低等的方法，这种方法中，材料的应用可能破坏某些元件。较好的技术是使用具有汽态化学物质的低压容器，尽管其它方法，诸如大气压处理也可考虑。
能用来包裹半导体集成电路印模(或塑料封装器件，或二者皆有，如下进一步所述)的一种处理是原子层沉积(ALD)。这种技术在低温下不用等离子体就能实现不可渗透的陶瓷涂层，而等离子体的使用可能损坏或破坏半导体集成电路印模。使用磷或无卤素初级粒子(halogen-free precursor)来处理腐蚀。其它一些化学气相沉积方法所出现的针孔问题用这种技术就可以防止其扩散。原子层沉积的处理温度在150～250℃范围内，而固有的精确层厚度控制在原子标度。
原子层沉积(ALD)和原子层外延(ALE)以及它们配对技术金属有机化学气相沉积(MDCVD)，很适合于制造分层结构，既可以是外延还是非外延。金属有机化学汽相沉积也能淀积较厚的单层。许多材料能用这些技术沉积。通过原子层外延(ALE)以多晶体或无定形式淀积的电介质是氮化铝、氮化硅、碳化硅、氧化铝、氧化钛、氧化锆、氧化铪、二氧化硅、氧化镁、氧化钇、氧化铈、氧化铌、氧化钽、氧化镧、钛酸锶和钛酸钡。
薄膜技术使得在基片或表面上沉积很薄的材料层(厚度可小至几个原子)成为可能。采用合适的系统设计，在同一淀积系统中都能实现金属有机化学汽相沉积和原子层外延模式。用金属有机化学汽相沉积技术生成的薄膜既可是构造的多晶体，也可以是外延单晶，这依赖于所用的基片。
原子层外延(ALE)是对淀积薄膜的化学汽相沉积技术和相关的表面结构的一种特定改进。原子层外延的独特特征是自我限定薄膜生成机制，这一机制给出了许多有吸引力的优点，像可精密且简单地控制薄膜厚度、窄的界面、大面积上的均匀性、优异的保形性、良好的重现性、多层处理的能力以及在相对低的温度下的高薄膜质量。除了能淀积特定用于阻挡层的较佳材料外，这种处理的其它方面能对其选择性进行调整。具体说，这种处理能以优异的保形性和良好的重现性在大面积上均匀淀积涂层。由于淀积是“脉冲式”的且每次脉冲淀积同样的厚度增量，因此，厚度控制既简单、又精确。高质量薄膜能在低温下沉积。但存在一种下降趋势，就是淀积速度低(低于5000/小时)，但薄膜质量可以高得使得较薄的薄膜层与用“较原始的”处理得到的厚层一样有效。然而，由于这是一种基于气体的处理，大量材料能均匀地一次涂层，因此，以涂层部分数目/小时表示的生产量与其他很难提高生产率的方法相比具有竞争力甚至更好。
金属有机化学汽相沉积技术使用液态金属有机初级粒子，它们在到达基片表面之前汽化成载气流。载气流即可以是氧化性的，像空气、氧气，也可以非氧化性的，如氢、氮、氩气。通过金属有机物高温分解，以及在加热的基片上或基片附近以原子或分子形式重新结合，就形成所希望的化合物。具有相对较高蒸汽压的液态金属有机初级粒子，如果它们是安全的，特别是没有毒副产品产生，则它们是较好的材料。金属有机化学汽相沉积中，沉积速度可高到10μm/h。金属有机化学汽相沉积室可最优化进行大面积沉积。
作为一种替代，也可使用开放空气燃烧化学汽相沉积技术(CCVD)。其优点是可大幅度降低运行成本和资金成本，改进材料质量和特性以及对特殊应用(包括多层结构)进行定制材料的能力。此外，燃烧化学汽相沉积相对简单的使用允许迅速开发新的涂层/基片组合。
已经论证了燃烧化学汽相沉积(CCVD)处理解决上述要求所具有的潜力。燃烧化学汽相沉积技术在克服传统汽相沉积技术的许多缺点而同时以低成本得到相同和/或更高质量的涂层方面具有广阔的前景。
CCVD技术的一个优点是它能使用并不贵的溶解状态下的初级粒子化合物在开放大气环境下沉积薄膜。这不需要昂贵的炉子、真空设备、反应室和后期淀积处理(如退火)。因此，当与相竞争的基于真空的技术(例如溅射和金属有机化学汽相沉积)相比，其资金要求和运行成本至少减少十倍。在开放的大气中淀积薄膜的能力使得可以连续地以生产线方式生产。因而，生产率的潜力远远超过普通的薄膜技术，大多数这类普通技术通常受制于这种批量处理。
实际上，初级粒子溶解在溶剂中，通常起可燃烧的燃料作用。借助于MCT拥有的纳米(NANOMISER)技术使溶液原子化形成亚微细粒。该亚微细粒随后被氧气流对流循环到火焰上，在那它们一起燃烧。通过简单地拉动基片到火焰等离子体上来涂敷基片。火焰的热量提供了使亚微细粒汽化的能量，以及使初级粒子在基片上反应。尽管火焰温度可能超过800℃，但基片只能短暂地留在火焰区中，从而得以保持较低温度(＜100℃)。或者，基片能有效冷却。因此，基片温度是独立的处理参数，能改变温度以有效控制薄膜的微结构。从开始到后期淀积的清洗过程不超过二小时。使用同样的溶液进行多回实验每回合需要额外的30分钟。因此，涂层和它们的性质能很快以重复的方式优化。燃烧化学汽相积技术大大不同于喷雾热分解：在喷雾热分解中，液—汽混合物喷在加热基片上，而燃烧化学汽相沉积是通过将初级粒子溶液原子化成为亚微细粒，并随后使亚微细粒汽化。因此CCVD可称为真正的汽相沉积处理。
通过调节溶液浓度和组成，能实现宽范围的涂层化学计算法和组分。这对要达到所希望的组合和薄膜性质特别有价值。传统的化学汽相沉积要求初级粒子有足够高的蒸汽压。这常常要使用昂贵的材料并常会产生必须仔细处理的有毒烟气(“洗气”)。相反，燃烧化学汽相沉积技术使用便宜的、可溶解的初级粒子，它不需要有高的蒸气压。因此，燃烧化学汽相沉积处理使用的初级粒子比在传统化学气相沉积处理中所使用的初级粒子要便宜10到100倍。淀积薄膜的物理结构和化学祖分能够针对特殊的使用要求加以定制。
燃烧化学汽相沉积处理最适合于像SiO2这样的绝缘体的高速沉积(上至1μm/min.)。
还有一种替代的方法，金刚石类的碳(DLC)显示出广阔的前途。它能沉积对“外部世界”显现疏水或亲水的表面。
以后要制备电接触的导线外端点被掩模(mask)以防止涂敷，或者以后能从这些区域以机械方式除去涂层。
掩模可能是冗长乏味的和消耗时间的，且必须准确完成，这是因为提出的涂层方法能在微小的没有掩模的区域上沉积。当压缩时，通过紧贴着不规则表面(例如半导体集成电路印模器件上的矩形截面导线)周围流动方式形成的氟碳泡沫带中的GDRE-TEX可用作掩膜材料。但这种材料可能太贵，除非能充分重复使用。可重复使用的铸造橡胶模(商业上可用于在焊接期间保护连接点)能提供更经济的替代物，如聚酰胺带、Laytex带、有机保护层、金属掩膜、橡胶掩膜和塑料掩膜等。
机械方法或者化学方法剥去接触点上的涂层也是一种选择。通过用紫外激光从导线烧蚀除去涂层，就可以将紫外激光器作为一种剥除涂层的方法。
任意陶瓷和玻璃质材料适用于作为双层涂层的第一层。材料最好是电绝缘的，即大于108ohm-meters；材料能够在器件的所有组成装配部分周围淀积保形的薄膜；材料能够淀积作为基本上没有针孔的涂层，例如具有湿气渗透性小于10-10g/cm-sec-torr；材料能以足够低的温度淀积以避免对器件和组成部件产生有害影响，例如，要在低于300℃温度下经过0.1小时或者等效的能量输入；材料粘附在器件的组成部件上从而在存在湿气、离子和热循环时使用塑料封装器件期间，防止或避免分层或起泡；材料不被湿气、碱金属离子和卤化离子渗透；材料与器件的构成部件和后期处理没有互反应而且在电、物理和机械上是相容的。
较好的陶瓷材料是氧化物陶瓷(包括氧化铝、氧化钛和氧化锆)、硅基陶瓷(包括氮化硅、二氧化硅和氧氮化硅)以及无定形和结晶形形式的类金刚石碳。
任何能可靠地生产粘着而基本上没有针孔的薄膜厚度(典型地是超过500-1000)。较厚的薄膜改善密封度(除非它们因内应力而自毁)。处于经济原因，5000-10000是实际的上限。
接下来参考图4(图6中步骤)，表示由半导体集成电路印模、引线、引线接合、导线和双重涂层的第一层所构成的组件。也表示了双重涂层的第二层。双重涂层的第二层是施加的有机覆盖层，以便包裹半导体集成电路印模、引线接合、引线、导线的内端点和双重涂层的第一层。
用双重涂层的第二层对半导体集成电路印模、引线、引线接合、导线和双重涂层的第一层的包裹，即有机覆盖层最好通过施加一聚对苯二甲基C层、一种聚对-苯二甲基形式，来实现。
对这部分双重涂层来说，聚对苯二甲基C有很多理想的性质。在各实施例中，其它聚对苯二甲基配方也可能是合适的。涂层厚度最好是最优化的。较厚的涂层会增加接合引线的刚性，并是防止模制化合物的腐蚀和应力影响的较好的垫层，还为陶瓷层提供了较好的物理保护。但是，较厚的涂层对应用来说要更加贵，而且当在内部施加时会减小印模通过封装层的热扩散。
作为一种替代方式，可以使用一类新材料作为替代品，溶胶凝胶混合物(或者溶胶凝胶衍生材料，或者氟聚合物-二氧化硅混合物)，它们明显同于普通的溶胶凝胶。由于这些材料比聚对苯二甲基应具有更低的渗透性而且更硬，因此这些材料可以加到很厚，足以作为依附层或者外部划伤的阻挡层，从而作为聚对苯二甲基的替代物。溶胶凝胶混合物涂层也能作为一坚硬的薄层，甚至有资格作为屏障层，也可作为整平层；该层在第一层应用以前应成为必需或期望的层。作为一整平层，因为它能在空气中40-80℃的温度下在几分钟内凝固，因此，相对于FOx(可流动氧化物)涂层在250～450℃或更高的温度下(在氮气层中)的几小时内凝固来说，该平整层远优于FOx层。
氟聚合物-二氧化硅混合物是新一代超级粘合涂层，它具有组成涂层材料的综合特性：良好的化学特性和优异的抗水性、聚合物的灵活性、疏水性(拒水性)、低表面能量、低介电常数和热稳定性(200℃以上)，还结合了二氧化硅网络的高透明性、硬度和机械强度。
注意在这儿表示的图中，第二层延伸超出第一层，这些层实际上没有重叠，因此能实现有效掩模，也就是说没有必要除去掩膜和在涂层之间重新配置。
在随后要进行电气接触的导线的外端点经掩模以防止涂敷或以后能在这些区域机械地除去涂层。掩膜技术可参照上面对第一层的描述，对于第二层来说，基本上是一样的。
注意在这儿表示的图中，第二层延伸超出第一层，这些层实际上没有重叠，因此能实现有效掩模，也就是说没有必要除去掩膜和在涂层之间重新配置。
双重涂层的第一层的类陶瓷无机材料用作对湿气和离子杂质的主要阻挡层。双重涂层的第二层的有机覆盖层虽也有一些阻挡特性，但还为较薄的、更易碎的双重涂层第一层类陶瓷无机材料提供物理保护层。这二层都是电绝缘的。
任何有机材料都适合作为双重涂层第二层的有机覆盖层。最好，该材料就是电绝缘的，即电阻率大于108Ω-m；能在不破坏第一层的前提下在器件所有组成部件的周围沉积作为均匀薄膜；能够淀积作为基本上无针孔的涂层，即阻挡湿气传输速度小于0.5gmil/100in2；能在低到足以避免器件和组成部件损伤的温度下淀积；能容易地达到至少0.5mil厚度，例如，最好在1和3mil之间；能在存在湿气和离子的情况下粘附到第一层而没有分层或气泡；能依附和抗撕裂，例如，有10％或更高的延伸率；有对湿气、碱金属离子和卤族离子的不可渗透性；对器件的组成部件和后续处理无电抗而且是相容的(电、物理和机械上)。
双重涂层的第二层是直接加到第一层上，如上所述，该第二层最好是聚对苯二甲基C，其它类别的聚对苯二甲基、溶胶凝胶混合物或其它凝聚或等离子聚合物化的有机薄膜。聚对苯二甲基C是可用于行机材料的极好的湿气和离子的阻挡层材料，是电绝缘的，在亚微米厚度薄膜中没有针孔，也能容易淀积成25-75微米厚度的层。超过25微米厚的厚膜在浇模期间为脆弱的接合引线提供了刚性，它的延展性提供了避免在模塑树脂中存在磨损粒子和消除在部件和模塑化合物之间的应力。
当描述了第一层和第二层的材料的特定例子后，熟练的技术人员会理解每一层适合于不同的和重要的目的。第一层是阻挡层，它的主要功能是阻止湿气或离子通过。第二层是依附层或保护层，它的主要功能是在处理和制造期间(例如注模期间)保护较为脆弱的第一层。
正如所表明的，双重涂层最好加到包含粘附的印模和引线接合的部分装配的导线框上，即恰好在以标准的商业习惯做法递压模塑部件之前的阶段。
接下来参考图5(图6中步骤)，它表示出完整的由半导体集成电路印模、引线、引线接合、导线，双重涂层的第一和第二层以及印模粘合基片所构成的塑料封装器件。也示出了一种塑料封装，它以传统方法在集成电路印模、引线、引线接合、导线、双重涂层的第一和第二层以及印模附属基片上进行注模。
当塑料封装以传统方法使用时，可注意到普通的抵抗湿气和离子的添加物在使用这里描述的实施例或其它实施例的塑料封装中并不需要。
因此，可以看到，本实施例的双重涂层提供了密封的阻挡层以保护半导体集成电路印模、引线和引线接合不受杂质污染(例如进入塑料封装的水和氧)。正如所理解的，本实施例，因此提供一塑料封装，还有密封的半导体集成电路器件，因而实现了与塑料封装器件相关的所有经济优点，也达到了陶瓷封装器件的高可靠、长寿命的优点。
而且，这里描述的实施例提供了比普通陶瓷封装设计更大的封装灵活性，从而允许在化学隔绝环境中操作。
接下来参照图1以及图7到图9，在另一实施例中，像上面描述的这种相同双重涂层也能涂复在普通塑料封装系统的塑料封装上，以便提供像将双重涂层用到暴露的半导体集成电路印模、引线接合、引线和导线框的导线的组件上所提供的同样的保护。
参照图7(和图9中步骤、和)，表示例如图1的塑料封装结构的截面图，包括塑料封装、印模附属基片、半导体集成电路印模、引线、引线接合和导线。也表示了双重涂层的第一层。如上所述，双重涂层的第一层是类陶瓷的无机材料层，以便包裹塑料封装和导线外端点的邻近部分。双重涂层第一层的使用和组成基本上如上面参照图3描述的一样，除了在本实施例中的流程有所不同，施加第一层以包裹塑料封装和其内部的部件，这与仅包裹半导体集成电路印模、引线接合、引线和导线的内端成对比。
因此，首先以上面所描述的普通方法形成包括有半导体集成电路印模、引线接合、引线和导线的组件。接着，将该组件(除了导线的外端以外)包裹在塑料封装中，也如上面所描述。随后，基本上也如上所述施加双重涂层的第一层，但是对塑料封装及其内部部件进行包裹，这与仅包裹半导体集成电路印模、引线接合、引线和导线的内端成对比。在本实施例中的第二层厚度也更大，因此，与已有实施例相比需要对该第二涂层进行更多处理。
接下来参考图8(图9中步骤)，这是如图1的塑料封装结构的横截面图，该结构包括塑料封装、印模附属基片、半导体集成电路印模、引线、引线接合和导线。也示出了如图7的双重涂层的第一层，还示出双重涂层的第二层。如上所述，双重涂层的第二层是有机覆盖层，但包裹了塑料封装和导线外端邻近部分以及双重涂层的第一层。双重涂层第二层的使用和组成基本上与上面参照图4的描述一样，不同之处在于本实施例的流程，施加该第二层以把塑料封装和其内部的部件以及双重涂层的第一层包裹起来，与仅包裹半导体集成电路印模、引线接合、引线，导线的内端和双重涂层的第一层成对比。
参照图10，表示的是塑料外壳结构的装配图，在这个图里，可结合这里描述的原理。其中示出塑料帽、第一环氧密封、导线框、半导体集成电路印模、引线和引线接合、第二环氧密封和塑料基体。除了在装配之前，将上面描述的双重涂层施加到半导体集成电路印模、引线接合、引线和导线框的导线内端上外，所描述的组件在结构和制造的所有方面都是常规的。如上所述有效地掩模或从导线框导线的外端上除去双重涂层，以便维持导线外端的电连接性。
接下来参照图11，表示的是另一种塑料外壳结构的装配图，在该结构中可结合这里描述的原理。其中示出了塑料帽、第一环氧密封、塑料侧壁、第二环氧密封、导线框、半导体集成电路印模、引线和引线结合，第三环氧密封和塑料基体，除了如图10的实施例，在装配之前，上面描述的双重涂层施加到半导体集成电路印模、引线接合、引线和导线框导线内端上外，所描述的组件在结构和制造上的所有方面都是常规的。如图10，如上所述有效地掩模或从导线框外端上除去双重涂层，以维持导体的外端的电连接。
参照图12，表示的是一器件截面上的局部透视图，该器件既可以具有图2到图6的涂敷方法，也可以具有图7到图9的涂敷方法。因为除了这两种方法用在同一器件上以外，所描述的实施例的方法与参考图组中描述的各个方法是等同的，因而不需要在这里对这些方法做进一步解释。但熟练的技术人员会理解，对于特别灵敏的应用，所描述的实施例能在它们许多变化中提供比上面描述的方法中的任何一个更好的密封性。
尽管这里公开的本发明通过各种具体的实施例和应用加以描述了，但本领域的熟练技术人员仍能在不背离在权利要求书中提出的本发明的范围的情况下，作出许多调整和变化。

Claims (16)

1.一种密封涂敷器件，其特征在于，包括：
半导体集成电路印模；
包含无机材料的第一层，所述第一层包裹半导体集成电路印模；以及
第二层，所述第二层包裹半导体集成电路印模。
2.如权利要求1所述的密封涂敷器件，其特征在于，所述第一层与所述半导体集成电路印模相接触。
3.如权利要求1所述的密封涂敷器件，其特征在于，还包括：
包裹在半导体集成电路印模上的塑料封装。
4.如权利要求3所述的密封涂敷器件，其特征在于，所述塑料涂层与第二层相接触。
5.如权利要求3所述的密封涂敷器件，其特征在于，所述的塑料封装包括塑料帽。
6.如权利要求1所述的密封涂敷器件，其特征在于，还包括：
具有内端和外端的导线；
引线；
在半导体集成电路印模表面上的焊接区；
在引线的第一端和焊接区之间的第一引线接合；和
在引线第二端和导线内端之间的第二引线接合；
其中引线、焊接区、第一引线接合和第二引线接合与第一层接触并被第一层包裹。
7.如权利要求1所述的密封涂敷器件，其特征在于，还包括：
包裹半导体集成电路印模的塑料封装；
其中第一层与塑料封装接触并包裹塑料封装。
8.如权利要求1所述的密封涂敷器件，其特征在于，所述第一层包含从无机材料组中所选择的材料。
9.如权利要求1所述的密封涂敷器件，其特征在于，所述第二层包括从有机材料组中所选择的材料。
10.一种制造密封涂敷器件的方法，其特征在于，包括：
配制半导体集成电路印模；
施加包含无机材料的第一层，所述第一层包裹半导体集成电路印模；
施加第二层，所述第二层包裹半导体集成电路印模。
11.如权利要求10所述的方法，其特征在于，第一层的施加包括半导体集成电路印模与第一层接触。
12.如权利要求10所述的方法，其特征在于，还包括：
将半导体集成电路印模包裹在塑料封装中。
13.如权利要求12所述的方法，其特征在于，在塑料封装中的包裹包括第二层与塑料封装的接触。
14.如权利要求12所述的方法，其特征在于，所述的在塑料封装中的包裹包括将塑料帽放在半导体集成电路印模上。
15.如权利要求10所述的方法，其特征在于，还包括：
在引线第一端和半导体集成电路印模表面上的焊接区之间形成第一引线接合；以及
在引线第二端和导线的内端之间形成第二引线接合；
其中在第一层中应用半导体集成电路印模包括将第一层用到引线、焊接区、第一引线接合和第二引线接合。
16.如权利要求10所述的方法，其特征在于，还包括：
将半导体集成电路印模包裹在塑料封装中；
其中第一层的使用包括将用第一层包裹塑料封装。
CN01806244A 2000-03-08 2001-03-07 电子器件封装 Pending CN1416593A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/520,928 2000-03-08
US09/520,928 US6368899B1 (en) 2000-03-08 2000-03-08 Electronic device packaging

Publications (1)

Publication Number Publication Date
CN1416593A true CN1416593A (zh) 2003-05-07

Family

ID=24074614

Family Applications (1)

Application Number Title Priority Date Filing Date
CN01806244A Pending CN1416593A (zh) 2000-03-08 2001-03-07 电子器件封装

Country Status (11)

Country Link
US (2) US6368899B1 (zh)
EP (1) EP1269531A1 (zh)
JP (1) JP2003526920A (zh)
KR (1) KR20030003696A (zh)
CN (1) CN1416593A (zh)
AU (1) AU2001242012A1 (zh)
BR (1) BR0109077A (zh)
CA (1) CA2401702A1 (zh)
IL (1) IL151498A0 (zh)
MX (1) MXPA02008736A (zh)
WO (1) WO2001067504A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399037C (zh) * 2005-04-30 2008-07-02 中国科学院空间科学与应用研究中心 一种针对商用塑封器件空间应用的筛选方法
CN1957466B (zh) * 2004-03-26 2011-09-14 英飞凌科技股份公司 纳米尺寸颗粒在制造半导体芯片上的抗刮保护层中的应用

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6613978B2 (en) * 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US6852567B1 (en) * 1999-05-31 2005-02-08 Infineon Technologies A.G. Method of assembling a semiconductor device package
US20020113322A1 (en) * 2000-06-12 2002-08-22 Shinichi Terashima Semiconductor device and method to produce the same
EP1215724B1 (en) * 2000-11-20 2012-10-31 Texas Instruments Incorporated Wire bonded semiconductor device with low capacitance coupling
US6726996B2 (en) * 2001-05-16 2004-04-27 International Business Machines Corporation Laminated diffusion barrier
US6649446B1 (en) * 2001-11-29 2003-11-18 Clarisay, Inc. Hermetic package for multiple contact-sensitive electronic devices and methods of manufacturing thereof
US6777349B2 (en) * 2002-03-13 2004-08-17 Novellus Systems, Inc. Hermetic silicon carbide
US7723162B2 (en) * 2002-03-22 2010-05-25 White Electronic Designs Corporation Method for producing shock and tamper resistant microelectronic devices
US7382043B2 (en) 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7517790B2 (en) * 2002-10-31 2009-04-14 International Business Machines Corporation Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification
KR100518560B1 (ko) * 2003-03-04 2005-10-04 삼성전자주식회사 원자층 증착법을 이용한 박막 형성방법
US20040178498A1 (en) * 2003-03-10 2004-09-16 Low Qwai H. Wire bonding to full array bonding pads on active circuitry
US20070275181A1 (en) 2003-05-16 2007-11-29 Carcia Peter F Barrier films for plastic substrates fabricated by atomic layer deposition
US7094633B2 (en) * 2003-06-23 2006-08-22 Sandisk Corporation Method for efficiently producing removable peripheral cards
US7332797B2 (en) * 2003-06-30 2008-02-19 Intel Corporation Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold
US7191516B2 (en) 2003-07-16 2007-03-20 Maxwell Technologies, Inc. Method for shielding integrated circuit devices
US6934065B2 (en) * 2003-09-18 2005-08-23 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
US7179688B2 (en) * 2003-10-16 2007-02-20 Kulicke And Soffa Industries, Inc. Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US6955949B2 (en) * 2003-10-16 2005-10-18 Kulicke & Soffa Investments, Inc. System and method for reducing or eliminating semiconductor device wire sweep
US6847122B1 (en) 2003-10-16 2005-01-25 Kulicke & Soffa Investments, Inc. System and method for preventing and alleviating short circuiting in a semiconductor device
US7098544B2 (en) * 2004-01-06 2006-08-29 International Business Machines Corporation Edge seal for integrated circuit chips
US7705432B2 (en) * 2004-04-13 2010-04-27 Vertical Circuits, Inc. Three dimensional six surface conformal die coating
ES2559410T3 (es) * 2004-04-23 2016-02-12 Philip Morris Products S.A. Generadores de aerosol y métodos para producir aerosoles
US8501277B2 (en) 2004-06-04 2013-08-06 Applied Microstructures, Inc. Durable, heat-resistant multi-layer coatings and coated articles
US7364934B2 (en) * 2004-08-10 2008-04-29 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
DE102004047510A1 (de) * 2004-09-28 2006-04-13 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten
JP2006118669A (ja) * 2004-10-25 2006-05-11 Sanoh Industrial Co Ltd 樹脂チューブ
US20060102597A1 (en) * 2004-11-16 2006-05-18 Exponent, Inc. Electron beam welding method and apparatus using controlled volumetric heating
EP1843816B1 (en) * 2005-02-01 2017-07-12 Second Sight Medical Products, Inc. Micro-miniature implantable coated device
US7409878B2 (en) * 2005-04-08 2008-08-12 Honeywell International Inc. Torqueshaft magnetic field measurement systems for gas turbine engines
DE102005025083B4 (de) * 2005-05-30 2007-05-24 Infineon Technologies Ag Thermoplast-Duroplast-Verbund und Verfahren zum Verbinden eines thermoplastischen Materials mit einem duroplastischen Material
DE102005025465B4 (de) * 2005-05-31 2008-02-21 Infineon Technologies Ag Halbleiterbauteil mit Korrosionsschutzschicht und Verfahren zur Herstellung desselben
DE102005028704B4 (de) * 2005-06-20 2016-09-08 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten
US20070135552A1 (en) * 2005-12-09 2007-06-14 General Atomics Gas barrier
DE102005061248B4 (de) * 2005-12-20 2007-09-20 Infineon Technologies Ag Systemträger mit in Kunststoffmasse einzubettenden Oberflächen, Verfahren zur Herstellung eines Systemträgers und Verwendung einer Schicht als Haftvermittlerschicht
KR100762878B1 (ko) 2006-01-23 2007-10-08 주식회사 하이닉스반도체 플래너 스택 패키지
DE112006003861B4 (de) * 2006-05-10 2015-09-17 Infineon Technologies Ag Halbleiterbaugruppe und Verfahren zur Herstellung einer Halbleiterbaugruppe
US8013332B2 (en) * 2006-10-20 2011-09-06 Sandisk Technologies Inc. Portable memory devices
US7928010B2 (en) * 2006-10-20 2011-04-19 Sandisk Corporation Method for producing portable memory devices
US8294248B2 (en) * 2006-11-30 2012-10-23 Marvell World Trade Ltd. Chip on leads
US20080157307A1 (en) * 2006-12-28 2008-07-03 Semiconductor Manufacturing International (Shanghai) Corporation Lead frame
US8110906B2 (en) * 2007-01-23 2012-02-07 Infineon Technologies Ag Semiconductor device including isolation layer
US7923823B2 (en) * 2007-01-23 2011-04-12 Infineon Technologies Ag Semiconductor device with parylene coating
US8236379B2 (en) 2007-04-02 2012-08-07 Applied Microstructures, Inc. Articles with super-hydrophobic and-or super-hydrophilic surfaces and method of formation
US20080248263A1 (en) * 2007-04-02 2008-10-09 Applied Microstructures, Inc. Method of creating super-hydrophobic and-or super-hydrophilic surfaces on substrates, and articles created thereby
US7939932B2 (en) * 2007-06-20 2011-05-10 Analog Devices, Inc. Packaged chip devices with atomic layer deposition protective films
DE102007035608A1 (de) * 2007-07-30 2009-02-05 Infineon Technologies Ag Halbleitermodul mit Weichvergussschicht und Verfahren zur Herstellung desselben
US8097934B1 (en) 2007-09-27 2012-01-17 National Semiconductor Corporation Delamination resistant device package having low moisture sensitivity
US7902644B2 (en) * 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
DE112008003425B4 (de) * 2007-12-20 2023-08-31 Aisin Aw Co., Ltd. Verfahren zum Herstellen eines Halbleiterbauelements
US9953952B2 (en) * 2008-08-20 2018-04-24 Infineon Technologies Ag Semiconductor device having a sealant layer including carbon directly contact the chip and the carrier
US8206829B2 (en) * 2008-11-10 2012-06-26 Applied Materials, Inc. Plasma resistant coatings for plasma chamber components
US20100164083A1 (en) * 2008-12-29 2010-07-01 Numonyx B.V. Protective thin film coating in chip packaging
JP5150597B2 (ja) * 2009-10-08 2013-02-20 新電元工業株式会社 半導体パッケージ及びその製造方法
DE102009058796A1 (de) * 2009-12-18 2011-06-22 OSRAM Opto Semiconductors GmbH, 93055 Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements
JP5427680B2 (ja) * 2010-04-14 2014-02-26 株式会社金陽社 有機薄膜太陽電池の製造方法
US20120166665A1 (en) * 2010-12-22 2012-06-28 Research In Motion Limited Method and system for selectively performing proxy services
US9069380B2 (en) 2011-06-10 2015-06-30 Aliphcom Media device, application, and content management using sensory input
US20120313296A1 (en) * 2011-06-10 2012-12-13 Aliphcom Component protective overmolding
US20120313272A1 (en) * 2011-06-10 2012-12-13 Aliphcom, Inc. Component protective overmolding
JP5956783B2 (ja) * 2012-03-02 2016-07-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2013142580A1 (en) * 2012-03-20 2013-09-26 Applied Nanotech Holdings, Inc. Application of dielectric layer and circuit traces on heat sink
EP2883415A2 (en) * 2012-08-13 2015-06-17 Aliphcom, Inc. Component protective overmolding using protective external coatings
DE102012108770A1 (de) * 2012-09-18 2014-03-20 Rudolf Heicks Elektronische Baugruppe mit einem räumlichen spritzgegossenen elektronischen Schaltungsträger
US20140141191A1 (en) * 2012-11-20 2014-05-22 Veeco Ald Inc. Hydrophobic and Oleophobic Encapsulation Material with Alternating Layers
US9233842B2 (en) * 2013-03-15 2016-01-12 Robert Bosch Gmbh Passivation layer for harsh environments and methods of fabrication thereof
JP6064928B2 (ja) * 2014-02-13 2017-01-25 トヨタ自動車株式会社 半導体装置
JP6672812B2 (ja) 2016-01-14 2020-03-25 三菱電機株式会社 半導体装置及びその製造方法
DE102016106137B4 (de) * 2016-04-04 2023-12-28 Infineon Technologies Ag Elektronikvorrichtungsgehäuse umfassend eine dielektrische Schicht und ein Kapselungsmaterial
DE102016109349A1 (de) * 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts
US10177057B2 (en) * 2016-12-15 2019-01-08 Infineon Technologies Ag Power semiconductor modules with protective coating
US10847384B2 (en) * 2017-05-31 2020-11-24 Palo Alto Research Center Incorporated Method and fixture for chip attachment to physical objects
JP2021533565A (ja) 2018-08-07 2021-12-02 コーニング インコーポレイテッド 気密封止パッケージ
US11552006B2 (en) * 2020-07-22 2023-01-10 Texas Instruments Incorporated Coated semiconductor devices

Family Cites Families (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL157456B (nl) * 1968-07-30 1978-07-17 Philips Nv Halfgeleiderinrichting in een isolerende kunststofomhulling.
US3771025A (en) 1969-10-02 1973-11-06 Gen Electric Semiconductor device including low impedance connections
US3828425A (en) 1970-10-16 1974-08-13 Texas Instruments Inc Method for making semiconductor packaged devices and assemblies
US3706840A (en) 1971-05-10 1972-12-19 Intersil Inc Semiconductor device packaging
US3914858A (en) 1974-08-23 1975-10-28 Nitto Electric Ind Co Method of making sealed cavity molded semiconductor devices
US4198444A (en) * 1975-08-04 1980-04-15 General Electric Company Method for providing substantially hermetic sealing means for electronic components
US4089575A (en) 1976-09-27 1978-05-16 Amp Incorporated Connector for connecting a circuit element to the surface of a substrate
US4091407A (en) 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
US4100675A (en) 1976-11-01 1978-07-18 Mansol Ceramics Company Novel method and apparatus for hermetic encapsulation for integrated circuits and the like
NL189379C (nl) 1977-05-05 1993-03-16 Richardus Henricus Johannes Fi Werkwijze voor inkapselen van micro-elektronische elementen.
JPS544781A (en) 1977-06-03 1979-01-13 Buichi Kataoka Fishing rod arranging apparatus in setting and throwing machine of fishing rod with reel
US4173683A (en) 1977-06-13 1979-11-06 Rca Corporation Chemically treating the overcoat of a semiconductor device
JPS56103452A (en) 1980-01-22 1981-08-18 Fujitsu Ltd Semiconductor device
JPS5795850A (en) 1980-12-04 1982-06-14 Ukenori Fukushi Method of drawing picture on glass surface and said glass picture
JPS5795650A (en) 1980-12-05 1982-06-14 Nec Corp Semiconductor device
US4975762A (en) 1981-06-11 1990-12-04 General Electric Ceramics, Inc. Alpha-particle-emitting ceramic composite cover
US4468411A (en) 1982-04-05 1984-08-28 Motorola, Inc. Method for providing alpha particle protection for an integrated circuit die
JPS58207657A (ja) 1982-05-28 1983-12-03 Fujitsu Ltd 半導体装置及びその製造方法
US4633573A (en) 1982-10-12 1987-01-06 Aegis, Inc. Microcircuit package and sealing method
US4506108A (en) 1983-04-01 1985-03-19 Sperry Corporation Copper body power hybrid package and method of manufacture
JPS60106150A (ja) 1983-11-15 1985-06-11 Nippon Telegr & Teleph Corp <Ntt> 耐放射線パツケ−ジ
JPS60124834A (ja) 1983-12-09 1985-07-03 Nec Corp 半導体装置の検査方法
JPS60180150A (ja) 1984-02-27 1985-09-13 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JPS60143398U (ja) 1984-03-05 1985-09-24 三菱電線工業株式会社 遮蔽材
US4523372A (en) 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
US4652465A (en) 1984-05-14 1987-03-24 Nissan Chemical Industries Ltd. Process for the production of a silver coated copper powder and conductive coating composition
JPS60257546A (ja) 1984-06-04 1985-12-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPS614249A (ja) 1984-06-19 1986-01-10 Sumitomo Electric Ind Ltd 半導体装置用パツケ−ジ
JPS614250A (ja) 1984-06-19 1986-01-10 Sumitomo Electric Ind Ltd 半導体装置用パツケ−ジ
US4804625A (en) 1984-09-27 1989-02-14 Amoco Corporation Assay procedures
US4663240A (en) 1984-11-06 1987-05-05 Enthone, Incorporated RFI shielded plastic articles and process for making same
FR2584863B1 (fr) 1985-07-12 1988-10-21 Inf Milit Spatiale Aeronaut Composant electronique durci vis-a-vis des radiations
US4687622A (en) 1985-10-29 1987-08-18 Irt Corporation Nuclear event detector
JPS62125651A (ja) 1985-11-26 1987-06-06 Nippon Telegr & Teleph Corp <Ntt> 耐放射線パツケ−ジ
US4625465A (en) * 1985-12-19 1986-12-02 Kirt Daryl L Hone stop assembly
US4935174A (en) 1986-01-13 1990-06-19 Canon Kabushiki Kaisha Resin molded article bearing electric circuit patterns and process for producing the same
FR2597652B1 (fr) 1986-04-16 1988-07-29 Aerospatiale Boitier de protection de circuits electroniques, durci vis-a-vis des rayons x
FR2597654B1 (fr) 1986-04-16 1989-06-30 Aerospatiale Gainage de protection de conducteurs electriques ou optiques, durci vis-a-vis des rayons x
US4891687A (en) 1987-01-12 1990-01-02 Intel Corporation Multi-layer molded plastic IC package
US4835120A (en) 1987-01-12 1989-05-30 Debendra Mallik Method of making a multilayer molded plastic IC package
US5047260A (en) 1987-02-06 1991-09-10 Key-Tech, Inc. Method for producing a shielded plastic enclosure to house electronic equipment
US5180513A (en) 1987-02-06 1993-01-19 Key-Tech, Inc. Shielded plastic enclosure to house electronic equipment
US4839716A (en) 1987-06-01 1989-06-13 Olin Corporation Semiconductor packaging
JPS644781A (en) 1987-06-29 1989-01-09 Olympus Optical Co Suction type liquid developing head
US4888449A (en) 1988-01-04 1989-12-19 Olin Corporation Semiconductor package
US4953002A (en) 1988-03-31 1990-08-28 Honeywell Inc. Semiconductor device housing with magnetic field protection
US4979019A (en) 1988-05-11 1990-12-18 Refractory Composites, Inc. Printed circuit board with inorganic insulating matrix
KR900019177A (ko) 1988-05-19 1990-12-24 야마자키 순페이 전기 장치 및 제조방법
DE3818114A1 (de) 1988-05-27 1989-11-30 Gruenzweig & Hartmann Montage Absorber fuer elektromagnetische und akustische wellen
JP2600366B2 (ja) 1989-03-09 1997-04-16 富士通株式会社 半導体チップの実装方法
JPH02278740A (ja) 1989-04-19 1990-11-15 Matsushita Electric Works Ltd 半導体装置のパッケージング方法
JPH03165058A (ja) 1989-11-24 1991-07-17 Mitsubishi Electric Corp 半導体装置
US4967315A (en) 1990-01-02 1990-10-30 General Electric Company Metallized ceramic circuit package
JPH03212006A (ja) 1990-01-17 1991-09-17 Sony Corp 高周波回路用パッケージ
US5139969A (en) 1990-05-30 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Method of making resin molded semiconductor device
JPH0494560A (ja) 1990-08-10 1992-03-26 Seiko Epson Corp 半導体装置
US5847467A (en) * 1990-08-31 1998-12-08 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
US5250845A (en) 1990-11-30 1993-10-05 Hughes Aircraft Company Totally enclosed hermetic electronic module
US5166772A (en) 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
JPH04273200A (ja) 1991-02-27 1992-09-29 Toshiba Corp シールド装置
JPH04291948A (ja) 1991-03-20 1992-10-16 Fujitsu Ltd 半導体装置及びその製造方法及び放熱フィン
US5149662A (en) 1991-03-27 1992-09-22 Integrated System Assemblies Corporation Methods for testing and burn-in of integrated circuit chips
US5138430A (en) 1991-06-06 1992-08-11 International Business Machines Corporation High performance versatile thermally enhanced IC chip mounting
US5206794A (en) 1991-12-20 1993-04-27 Vlsi Technology, Inc. Integrated circuit package with device and wire coat assembly
CA2080177C (en) 1992-01-02 1997-02-25 Edward Allan Highum Electro-magnetic shield and method for making the same
US5268331A (en) 1992-01-07 1993-12-07 Texas Instruments Incorporated Stabilizer/spacer for semiconductor device lead frames
US5202536A (en) 1992-02-03 1993-04-13 Schlegel Corporation EMI shielding seal with partial conductive sheath
US5317107A (en) 1992-09-24 1994-05-31 Motorola, Inc. Shielded stripline configuration semiconductor device and method for making the same
US5656830A (en) 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
US5589129A (en) 1993-02-19 1996-12-31 Kabushiki Kaisha Toshiba Method of manufacturing a molding using a filler or an additive concentrated on an arbitrary portion or distributed at a gradient concentration
US5384477A (en) 1993-03-09 1995-01-24 National Semiconductor Corporation CMOS latchup suppression by localized minority carrier lifetime reduction
CA2092371C (en) 1993-03-24 1999-06-29 Boris L. Livshits Integrated circuit packaging
EP0645810A4 (en) * 1993-04-06 1997-04-16 Tokuyama Corp SEMICONDUCTOR CHIP PACKAGE.
US5294826A (en) 1993-04-16 1994-03-15 Northern Telecom Limited Integrated circuit package and assembly thereof for thermal and EMI management
US5880403A (en) 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
US5825042A (en) 1993-06-18 1998-10-20 Space Electronics, Inc. Radiation shielding of plastic integrated circuits
US5455745A (en) 1993-07-26 1995-10-03 National Semiconductor Corporation Coated bonding wires in high lead count packages
US5406117A (en) 1993-12-09 1995-04-11 Dlugokecki; Joseph J. Radiation shielding for integrated circuit devices using reconstructed plastic packages
FI117224B (fi) 1994-01-20 2006-07-31 Nec Tokin Corp Sähkömagneettinen häiriönpoistokappale, ja sitä soveltavat elektroninen laite ja hybridimikropiirielementti
US5770304A (en) 1994-07-11 1998-06-23 Nippon Paint Co., Ltd. Wide bandwidth electromagnetic wave absorbing material
US5672918A (en) 1994-08-18 1997-09-30 The United States Of America As Represented By The United States Department Of Energy System level latchup mitigation for single event and transient radiation effects on electronics
JP2875479B2 (ja) 1994-09-08 1999-03-31 日本ペルノックス株式会社 半導体の封止方法
US5552338A (en) 1994-09-26 1996-09-03 Intel Corporation Method of using latchup current to blow a fuse in an integrated circuit
US5577319A (en) 1995-03-31 1996-11-26 Motorola, Inc. Method of encapsulating a crystal oscillator
US5851852A (en) 1996-02-13 1998-12-22 Northrop Grumman Corporation Die attached process for SiC
JP2734443B2 (ja) * 1996-03-19 1998-03-30 日本電気株式会社 樹脂封止型半導体装置
US5780163A (en) 1996-06-05 1998-07-14 Dow Corning Corporation Multilayer coating for microelectronic devices
US5834891A (en) 1996-06-18 1998-11-10 Ppg Industries, Inc. Spacers, spacer units, image display panels and methods for making and using the same
US5888850A (en) 1997-09-29 1999-03-30 International Business Machines Corporation Method for providing a protective coating and electronic package utilizing same
US6365521B1 (en) * 1997-12-31 2002-04-02 Intel Corporation Passivation for tight metal geometry
JP3132449B2 (ja) * 1998-01-09 2001-02-05 日本電気株式会社 樹脂外装型半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1957466B (zh) * 2004-03-26 2011-09-14 英飞凌科技股份公司 纳米尺寸颗粒在制造半导体芯片上的抗刮保护层中的应用
CN100399037C (zh) * 2005-04-30 2008-07-02 中国科学院空间科学与应用研究中心 一种针对商用塑封器件空间应用的筛选方法

Also Published As

Publication number Publication date
KR20030003696A (ko) 2003-01-10
IL151498A0 (en) 2003-04-10
EP1269531A1 (en) 2003-01-02
AU2001242012A1 (en) 2001-09-17
CA2401702A1 (en) 2001-09-13
BR0109077A (pt) 2003-06-03
US20030013235A1 (en) 2003-01-16
WO2001067504A1 (en) 2001-09-13
US6368899B1 (en) 2002-04-09
US6963125B2 (en) 2005-11-08
MXPA02008736A (es) 2003-09-25
JP2003526920A (ja) 2003-09-09

Similar Documents

Publication Publication Date Title
CN1416593A (zh) 电子器件封装
US6787397B2 (en) Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
CN1246898C (zh) 高度湿敏电子器件元件
US9379033B2 (en) Sensor package
US7371603B2 (en) Method of fabricating light emitting diode package
EP2309558A2 (en) Light emitting diode and manufacturing method thereof
US8420445B2 (en) Method for packing semiconductor components and product produced according to the method
JP2000036552A (ja) 半導体装置、及び半導体装置で用いる封止材中の金属分の分取方法
EP1918987B1 (en) Method for manufacturing semiconductor device
US6191492B1 (en) Electronic device including a densified region
CN1685507A (zh) 带有适合射频应用的导体结构的元件的制造方法
CN114975294A (zh) 核上具有形态粘附促进者壳的填料颗粒
CN1146984C (zh) 半导体封装用芯片支持基片、半导体装置及其制造方法
US6756670B1 (en) Electronic device and its manufacturing method
KR100638892B1 (ko) 발광다이오드 패키지 제조방법
JP2668043B2 (ja) 保護絶縁膜を有する半導体装置，その製造方法およびその製造装置
CN1682367A (zh) 半导体装置的制造方法
JPH03175632A (ja) 半導体装置およびその製造方法
JP2700351B2 (ja) 半導体装置およびその製造方法
KR0163305B1 (ko) 와이어 본딩 공정이 완료된 칩의 전기적 연결 부분을 보호하기 위한 보호 층 형성방법
JPH11315189A (ja) 半導体装置封止用樹脂組成物及びこれを用いた半導体装置
JPH01292846A (ja) 電子装置作製方法
JPH01292833A (ja) 電子装置作製方法
JPH05304139A (ja) 半導体用ガラス及びこれを用いた半導体デバイス
JPS62122237A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication