CN1380695A - 半导体集成电路装置及其设计方法 - Google Patents
半导体集成电路装置及其设计方法 Download PDFInfo
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- CN1380695A CN1380695A CN01125142A CN01125142A CN1380695A CN 1380695 A CN1380695 A CN 1380695A CN 01125142 A CN01125142 A CN 01125142A CN 01125142 A CN01125142 A CN 01125142A CN 1380695 A CN1380695 A CN 1380695A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
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Abstract
Description
Claims (29)
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05132196A JP3546582B2 (ja) | 1996-03-08 | 1996-03-08 | 半導体装置 |
JP051330/1996 | 1996-03-08 | ||
JP051321/1996 | 1996-03-08 | ||
JP05133096A JP3722307B2 (ja) | 1996-03-08 | 1996-03-08 | 半導体集積回路 |
JP14701096 | 1996-06-10 | ||
JP147010/1996 | 1996-06-10 | ||
JP30153896A JP3345282B2 (ja) | 1996-06-10 | 1996-11-13 | 半導体集積回路装置の設計方法 |
JP301538/1996 | 1996-11-13 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN97103057A Division CN1077727C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路的设计方法及其半导体集成电路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1380695A true CN1380695A (zh) | 2002-11-20 |
CN1317764C CN1317764C (zh) | 2007-05-23 |
Family
ID=27462622
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011251425A Expired - Fee Related CN1317764C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路装置及其设计方法 |
CN97103057A Expired - Fee Related CN1077727C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路的设计方法及其半导体集成电路装置 |
CNB011251417A Expired - Fee Related CN100356571C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路装置 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN97103057A Expired - Fee Related CN1077727C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路的设计方法及其半导体集成电路装置 |
CNB011251417A Expired - Fee Related CN100356571C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路装置 |
Country Status (5)
Country | Link |
---|---|
US (6) | US6069834A (zh) |
KR (4) | KR100429945B1 (zh) |
CN (3) | CN1317764C (zh) |
SG (1) | SG74580A1 (zh) |
TW (1) | TW318933B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101901627A (zh) * | 2006-12-22 | 2010-12-01 | 富士通半导体股份有限公司 | 存储器设备、存储器控制器和存储器系统 |
CN105677968A (zh) * | 2016-01-06 | 2016-06-15 | 深圳市同创国芯电子有限公司 | 可编程逻辑器件电路图绘制方法及装置 |
Families Citing this family (88)
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SG74580A1 (en) * | 1996-03-08 | 2000-08-22 | Hitachi Ltd | Semiconductor ic device having a memory and a logic circuit implemented with a single chip |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
JP3597706B2 (ja) * | 1997-07-25 | 2004-12-08 | 株式会社東芝 | ロジック混載メモリ |
US6442667B1 (en) * | 1998-06-08 | 2002-08-27 | Texas Instruments Incorporated | Selectively powering X Y organized memory banks |
JP3869128B2 (ja) * | 1998-09-11 | 2007-01-17 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP4437565B2 (ja) * | 1998-11-26 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路装置、半導体集積回路装置の設計方法、及び、記録媒体 |
JP4212171B2 (ja) * | 1999-01-28 | 2009-01-21 | 株式会社ルネサステクノロジ | メモリ回路/ロジック回路集積システム |
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CN101901627A (zh) * | 2006-12-22 | 2010-12-01 | 富士通半导体股份有限公司 | 存储器设备、存储器控制器和存储器系统 |
CN101901627B (zh) * | 2006-12-22 | 2015-05-06 | 富士通半导体股份有限公司 | 存储器设备、存储器控制器和存储器系统 |
CN105677968A (zh) * | 2016-01-06 | 2016-06-15 | 深圳市同创国芯电子有限公司 | 可编程逻辑器件电路图绘制方法及装置 |
CN105677968B (zh) * | 2016-01-06 | 2019-09-13 | 深圳市紫光同创电子有限公司 | 可编程逻辑器件电路图绘制方法及装置 |
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CN1344028A (zh) | 2002-04-10 |
US6335898B2 (en) | 2002-01-01 |
CN100356571C (zh) | 2007-12-19 |
US6246629B1 (en) | 2001-06-12 |
US6097663A (en) | 2000-08-01 |
KR100433738B1 (ko) | 2004-06-04 |
US20010014051A1 (en) | 2001-08-16 |
KR100439096B1 (ko) | 2004-07-05 |
US6609236B2 (en) | 2003-08-19 |
US6069834A (en) | 2000-05-30 |
TW318933B (en) | 1997-11-01 |
KR100441865B1 (ko) | 2004-07-27 |
KR100429945B1 (ko) | 2004-10-20 |
CN1163484A (zh) | 1997-10-29 |
US5995439A (en) | 1999-11-30 |
CN1077727C (zh) | 2002-01-09 |
US20020009834A1 (en) | 2002-01-24 |
KR970067852A (ko) | 1997-10-13 |
SG74580A1 (en) | 2000-08-22 |
CN1317764C (zh) | 2007-05-23 |
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