CN1380695A - 半导体集成电路装置及其设计方法 - Google Patents
半导体集成电路装置及其设计方法 Download PDFInfo
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- CN1380695A CN1380695A CN01125142A CN01125142A CN1380695A CN 1380695 A CN1380695 A CN 1380695A CN 01125142 A CN01125142 A CN 01125142A CN 01125142 A CN01125142 A CN 01125142A CN 1380695 A CN1380695 A CN 1380695A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
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Abstract
Description
Claims (29)
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP051321/1996 | 1996-03-08 | ||
JP051330/1996 | 1996-03-08 | ||
JP05132196A JP3546582B2 (ja) | 1996-03-08 | 1996-03-08 | 半導体装置 |
JP05133096A JP3722307B2 (ja) | 1996-03-08 | 1996-03-08 | 半導体集積回路 |
JP14701096 | 1996-06-10 | ||
JP147010/1996 | 1996-06-10 | ||
JP301538/1996 | 1996-11-13 | ||
JP30153896A JP3345282B2 (ja) | 1996-06-10 | 1996-11-13 | 半導体集積回路装置の設計方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN97103057A Division CN1077727C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路的设计方法及其半导体集成电路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1380695A true CN1380695A (zh) | 2002-11-20 |
CN1317764C CN1317764C (zh) | 2007-05-23 |
Family
ID=27462622
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011251417A Expired - Fee Related CN100356571C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路装置 |
CN97103057A Expired - Fee Related CN1077727C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路的设计方法及其半导体集成电路装置 |
CNB011251425A Expired - Fee Related CN1317764C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路装置及其设计方法 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011251417A Expired - Fee Related CN100356571C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路装置 |
CN97103057A Expired - Fee Related CN1077727C (zh) | 1996-03-08 | 1997-03-07 | 半导体集成电路的设计方法及其半导体集成电路装置 |
Country Status (5)
Country | Link |
---|---|
US (6) | US6069834A (zh) |
KR (4) | KR100429945B1 (zh) |
CN (3) | CN100356571C (zh) |
SG (1) | SG74580A1 (zh) |
TW (1) | TW318933B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101901627A (zh) * | 2006-12-22 | 2010-12-01 | 富士通半导体股份有限公司 | 存储器设备、存储器控制器和存储器系统 |
CN105677968A (zh) * | 2016-01-06 | 2016-06-15 | 深圳市同创国芯电子有限公司 | 可编程逻辑器件电路图绘制方法及装置 |
Families Citing this family (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG74580A1 (en) * | 1996-03-08 | 2000-08-22 | Hitachi Ltd | Semiconductor ic device having a memory and a logic circuit implemented with a single chip |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
JP3597706B2 (ja) * | 1997-07-25 | 2004-12-08 | 株式会社東芝 | ロジック混載メモリ |
US6442667B1 (en) * | 1998-06-08 | 2002-08-27 | Texas Instruments Incorporated | Selectively powering X Y organized memory banks |
JP3869128B2 (ja) * | 1998-09-11 | 2007-01-17 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP4437565B2 (ja) * | 1998-11-26 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路装置、半導体集積回路装置の設計方法、及び、記録媒体 |
JP4212171B2 (ja) * | 1999-01-28 | 2009-01-21 | 株式会社ルネサステクノロジ | メモリ回路/ロジック回路集積システム |
US6178133B1 (en) | 1999-03-01 | 2001-01-23 | Micron Technology, Inc. | Method and system for accessing rows in multiple memory banks within an integrated circuit |
US6842104B1 (en) * | 1999-03-19 | 2005-01-11 | Matsushita Electric Industrial Co., Ltd. | System lsi and a cross-bus switch apparatus achieved in a plurality of circuits in which two or more pairs of a source apparatus and a destination apparatus are connected simultaneously and buses are wired without concentration |
JP2001043671A (ja) * | 1999-07-28 | 2001-02-16 | Oki Micro Design Co Ltd | 半導体装置 |
US7119809B1 (en) * | 2000-05-15 | 2006-10-10 | S3 Graphics Co., Ltd. | Parallel architecture for graphics primitive decomposition |
JP2002008399A (ja) * | 2000-06-23 | 2002-01-11 | Mitsubishi Electric Corp | 半導体集積回路 |
US6658544B2 (en) | 2000-12-27 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Techniques to asynchronously operate a synchronous memory |
US6944168B2 (en) * | 2001-05-04 | 2005-09-13 | Slt Logic Llc | System and method for providing transformation of multi-protocol packets in a data stream |
US6904057B2 (en) * | 2001-05-04 | 2005-06-07 | Slt Logic Llc | Method and apparatus for providing multi-protocol, multi-stage, real-time frame classification |
US6901052B2 (en) * | 2001-05-04 | 2005-05-31 | Slt Logic Llc | System and method for policing multiple data flows and multi-protocol data flows |
US7042848B2 (en) * | 2001-05-04 | 2006-05-09 | Slt Logic Llc | System and method for hierarchical policing of flows and subflows of a data stream |
KR100412131B1 (ko) | 2001-05-25 | 2003-12-31 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 셀 데이타 보호회로 |
WO2003003197A2 (en) * | 2001-06-28 | 2003-01-09 | Oak Technology, Inc. | System-on-a-chip controller |
CN100568395C (zh) * | 2001-06-29 | 2009-12-09 | Nxp股份有限公司 | 非易失性存储器和通过附加修改的空存储单元加速测试地址解码器的方法 |
US7075284B2 (en) * | 2002-07-08 | 2006-07-11 | Kabushiki Kaisha Toshiba | Time limit function utilization |
US7402897B2 (en) | 2002-08-08 | 2008-07-22 | Elm Technology Corporation | Vertical system integration |
US6891753B2 (en) * | 2002-09-24 | 2005-05-10 | Sandisk Corporation | Highly compact non-volatile memory and method therefor with internal serial buses |
US6983428B2 (en) * | 2002-09-24 | 2006-01-03 | Sandisk Corporation | Highly compact non-volatile memory and method thereof |
US6940753B2 (en) * | 2002-09-24 | 2005-09-06 | Sandisk Corporation | Highly compact non-volatile memory and method therefor with space-efficient data registers |
US6934199B2 (en) * | 2002-12-11 | 2005-08-23 | Micron Technology, Inc. | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency |
JP2004235515A (ja) * | 2003-01-31 | 2004-08-19 | Renesas Technology Corp | 半導体装置 |
US6600673B1 (en) | 2003-01-31 | 2003-07-29 | International Business Machines Corporation | Compilable writeable read only memory (ROM) built with register arrays |
US7159128B2 (en) * | 2003-04-16 | 2007-01-02 | Seiko Epson Corporation | Method and apparatus for selectively reducing the depth of digital data |
US6862203B2 (en) * | 2003-05-27 | 2005-03-01 | Macronix International Co., Ltd. | Memory with shielding effect |
US7219324B1 (en) * | 2003-06-02 | 2007-05-15 | Virage Logic Corporation | Various methods and apparatuses to route multiple power rails to a cell |
US20050012735A1 (en) * | 2003-07-17 | 2005-01-20 | Low Yun Shon | Method and apparatus for saving power through a look-up table |
US7099221B2 (en) | 2004-05-06 | 2006-08-29 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US7355875B2 (en) * | 2004-06-21 | 2008-04-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having capacitor arranged between power supplies to prevent voltage fluctuation |
US20060010339A1 (en) * | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
US7340668B2 (en) | 2004-06-25 | 2008-03-04 | Micron Technology, Inc. | Low power cost-effective ECC memory system and method |
KR100608882B1 (ko) * | 2004-06-30 | 2006-08-08 | 엘지전자 주식회사 | 무전극 조명기기의 도파관 시스템 |
CN100382085C (zh) * | 2004-07-07 | 2008-04-16 | 华为技术有限公司 | 一种印制电路板中集成设计元件的版图设计方法和装置 |
US7116602B2 (en) * | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US6965537B1 (en) * | 2004-08-31 | 2005-11-15 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
KR100587692B1 (ko) * | 2004-11-05 | 2006-06-08 | 삼성전자주식회사 | 반도체 메모리 장치에서의 회로 배선 배치구조와 그에따른 배치방법 |
CN100433178C (zh) * | 2005-04-11 | 2008-11-12 | 智元科技股份有限公司 | 存储器电路元件应用装置 |
JP4010336B2 (ja) | 2005-06-30 | 2007-11-21 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP4186970B2 (ja) | 2005-06-30 | 2008-11-26 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP4830371B2 (ja) | 2005-06-30 | 2011-12-07 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
US7755587B2 (en) * | 2005-06-30 | 2010-07-13 | Seiko Epson Corporation | Integrated circuit device and electronic instrument |
KR100828792B1 (ko) * | 2005-06-30 | 2008-05-09 | 세이코 엡슨 가부시키가이샤 | 집적 회로 장치 및 전자 기기 |
JP4661400B2 (ja) * | 2005-06-30 | 2011-03-30 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP4010335B2 (ja) | 2005-06-30 | 2007-11-21 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP4151688B2 (ja) | 2005-06-30 | 2008-09-17 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP4010332B2 (ja) * | 2005-06-30 | 2007-11-21 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
US7764278B2 (en) * | 2005-06-30 | 2010-07-27 | Seiko Epson Corporation | Integrated circuit device and electronic instrument |
JP4665677B2 (ja) | 2005-09-09 | 2011-04-06 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
KR100824798B1 (ko) * | 2005-11-08 | 2008-04-24 | 삼성전자주식회사 | 에지 서브 어레이에 전체 데이터 패턴을 기입할 수 있는 오픈 비트 라인 구조를 가지는 메모리 코어, 이를 구비한 반도체 메모리 장치, 및 에지 서브 어레이 테스트 방법 |
JP2007157944A (ja) * | 2005-12-02 | 2007-06-21 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
US7584442B2 (en) | 2005-12-09 | 2009-09-01 | Lsi Corporation | Method and apparatus for generating memory models and timing database |
JP4586739B2 (ja) | 2006-02-10 | 2010-11-24 | セイコーエプソン株式会社 | 半導体集積回路及び電子機器 |
US7301828B2 (en) | 2006-02-27 | 2007-11-27 | Agere Systems Inc. | Decoding techniques for read-only memory |
US7324364B2 (en) * | 2006-02-27 | 2008-01-29 | Agere Systems Inc. | Layout techniques for memory circuitry |
EP1990836A4 (en) * | 2006-02-28 | 2010-11-03 | Fujitsu Ltd | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE |
JP4790518B2 (ja) * | 2006-07-12 | 2011-10-12 | 富士通株式会社 | 半導体記憶装置及び半導体記憶装置を備えた情報処理装置 |
US7894289B2 (en) | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US7900120B2 (en) | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
JP5143413B2 (ja) * | 2006-12-20 | 2013-02-13 | オンセミコンダクター・トレーディング・リミテッド | 半導体集積回路 |
US7865857B1 (en) * | 2007-01-23 | 2011-01-04 | Cadence Design Systems, Inc. | System and method for improved visualization and debugging of constraint circuit objects |
WO2008126229A1 (ja) * | 2007-03-29 | 2008-10-23 | Fujitsu Limited | 半導体集積回路および制御信号分配方法 |
US7733724B2 (en) * | 2007-11-30 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling global bit line pre-charge time for high speed eDRAM |
US8117567B2 (en) * | 2007-12-03 | 2012-02-14 | International Business Machines Corporation | Structure for implementing memory array device with built in computation capability |
US20090141530A1 (en) * | 2007-12-03 | 2009-06-04 | International Business Machines Corporation | Structure for implementing enhanced content addressable memory performance capability |
US7924588B2 (en) * | 2007-12-03 | 2011-04-12 | International Business Machines Corporation | Content addressable memory with concurrent two-dimensional search capability in both row and column directions |
US8649262B2 (en) * | 2008-09-30 | 2014-02-11 | Intel Corporation | Dynamic configuration of potential links between processing elements |
US7974124B2 (en) * | 2009-06-24 | 2011-07-05 | Sandisk Corporation | Pointer based column selection techniques in non-volatile memories |
JP4908560B2 (ja) * | 2009-08-31 | 2012-04-04 | 株式会社東芝 | 強誘電体メモリ及びメモリシステム |
KR101096185B1 (ko) * | 2010-05-25 | 2011-12-22 | 주식회사 하이닉스반도체 | 데이터 전송회로 및 전송방법, 데이터 전송회로를 포함하는 메모리장치 |
US8605526B2 (en) * | 2011-05-31 | 2013-12-10 | Infineon Technologies Ag | Memory reliability verification techniques |
US8842473B2 (en) | 2012-03-15 | 2014-09-23 | Sandisk Technologies Inc. | Techniques for accessing column selecting shift register with skipped entries in non-volatile memories |
KR101394488B1 (ko) * | 2012-10-02 | 2014-05-13 | 서울대학교산학협력단 | 전해질을 이용한 다이내믹 램 |
US9305614B2 (en) | 2012-12-21 | 2016-04-05 | Cypress Semiconductor Corporation | Memory device with internal combination logic |
JP6597628B2 (ja) * | 2014-10-24 | 2019-10-30 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US9710590B2 (en) * | 2014-12-31 | 2017-07-18 | Arteris, Inc. | Estimation of chip floorplan activity distribution |
WO2016166631A1 (en) * | 2015-04-13 | 2016-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Decoder, receiver, and electronic device |
US10403352B2 (en) * | 2017-02-22 | 2019-09-03 | Micron Technology, Inc. | Apparatuses and methods for compute in data path |
CN111095417B (zh) * | 2017-09-07 | 2023-08-29 | 松下控股株式会社 | 使用非易失性半导体存储元件的神经网络运算电路 |
JP2019160150A (ja) | 2018-03-16 | 2019-09-19 | 株式会社東芝 | 半導体装置 |
JP7023149B2 (ja) | 2018-03-22 | 2022-02-21 | キオクシア株式会社 | 半導体装置 |
US10884664B2 (en) | 2019-03-14 | 2021-01-05 | Western Digital Technologies, Inc. | Executable memory cell |
US10884663B2 (en) | 2019-03-14 | 2021-01-05 | Western Digital Technologies, Inc. | Executable memory cells |
US11601656B2 (en) * | 2021-06-16 | 2023-03-07 | Western Digital Technologies, Inc. | Video processing in a data storage device |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212777A (en) * | 1989-11-17 | 1993-05-18 | Texas Instruments Incorporated | Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation |
JP2880547B2 (ja) * | 1990-01-19 | 1999-04-12 | 三菱電機株式会社 | 半導体記憶装置 |
US5226134A (en) * | 1990-10-01 | 1993-07-06 | International Business Machines Corp. | Data processing system including a memory controller for direct or interleave memory accessing |
US5384745A (en) * | 1992-04-27 | 1995-01-24 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device |
JP3280704B2 (ja) * | 1992-05-29 | 2002-05-13 | 株式会社東芝 | 半導体記憶装置 |
DE69329788T2 (de) * | 1992-10-14 | 2001-08-02 | Sun Microsystems, Inc. | Direktzugriffspeicherentwurf |
JP3307478B2 (ja) * | 1993-09-13 | 2002-07-24 | 株式会社日立製作所 | 半導体集積回路装置 |
US5371396A (en) | 1993-07-02 | 1994-12-06 | Thunderbird Technologies, Inc. | Field effect transistor having polycrystalline silicon gate junction |
US5617367A (en) * | 1993-09-01 | 1997-04-01 | Micron Technology, Inc. | Controlling synchronous serial access to a multiport memory |
JPH07111100A (ja) * | 1993-10-08 | 1995-04-25 | Nec Corp | テスト回路 |
JP2742220B2 (ja) * | 1994-09-09 | 1998-04-22 | 松下電器産業株式会社 | 半導体記憶装置 |
JP3279101B2 (ja) * | 1994-11-21 | 2002-04-30 | ソニー株式会社 | 半導体集積回路 |
TW330265B (en) * | 1994-11-22 | 1998-04-21 | Hitachi Ltd | Semiconductor apparatus |
JP2915312B2 (ja) * | 1995-02-10 | 1999-07-05 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体集積回路装置 |
US5535172A (en) * | 1995-02-28 | 1996-07-09 | Alliance Semiconductor Corporation | Dual-port random access memory having reduced architecture |
JP2629645B2 (ja) * | 1995-04-20 | 1997-07-09 | 日本電気株式会社 | 半導体記憶装置 |
JP3824689B2 (ja) * | 1995-09-05 | 2006-09-20 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
JPH09161476A (ja) * | 1995-10-04 | 1997-06-20 | Toshiba Corp | 半導体メモリ及びそのテスト回路、並びにデ−タ転送システム |
SG74580A1 (en) * | 1996-03-08 | 2000-08-22 | Hitachi Ltd | Semiconductor ic device having a memory and a logic circuit implemented with a single chip |
JP3171097B2 (ja) * | 1996-03-25 | 2001-05-28 | 日本電気株式会社 | 半導体記憶装置 |
US5953278A (en) * | 1996-07-11 | 1999-09-14 | Texas Instruments Incorporated | Data sequencing and registering in a four bit pre-fetch SDRAM |
US5675537A (en) * | 1996-08-22 | 1997-10-07 | Advanced Micro Devices, Inc. | Erase method for page mode multiple bits-per-cell flash EEPROM |
-
1997
- 1997-03-04 SG SG1997000648A patent/SG74580A1/en unknown
- 1997-03-04 TW TW086102579A patent/TW318933B/zh not_active IP Right Cessation
- 1997-03-06 KR KR1019970007427A patent/KR100429945B1/ko not_active IP Right Cessation
- 1997-03-07 CN CNB011251417A patent/CN100356571C/zh not_active Expired - Fee Related
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- 1998-11-10 US US09/188,367 patent/US5995439A/en not_active Expired - Lifetime
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- 2001-11-14 KR KR1020010070713A patent/KR100433738B1/ko not_active IP Right Cessation
- 2001-11-14 KR KR1020010070712A patent/KR100439096B1/ko not_active IP Right Cessation
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101901627A (zh) * | 2006-12-22 | 2010-12-01 | 富士通半导体股份有限公司 | 存储器设备、存储器控制器和存储器系统 |
CN101901627B (zh) * | 2006-12-22 | 2015-05-06 | 富士通半导体股份有限公司 | 存储器设备、存储器控制器和存储器系统 |
CN105677968A (zh) * | 2016-01-06 | 2016-06-15 | 深圳市同创国芯电子有限公司 | 可编程逻辑器件电路图绘制方法及装置 |
CN105677968B (zh) * | 2016-01-06 | 2019-09-13 | 深圳市紫光同创电子有限公司 | 可编程逻辑器件电路图绘制方法及装置 |
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US20020009834A1 (en) | 2002-01-24 |
KR970067852A (ko) | 1997-10-13 |
US6609236B2 (en) | 2003-08-19 |
KR100429945B1 (ko) | 2004-10-20 |
CN1077727C (zh) | 2002-01-09 |
KR100439096B1 (ko) | 2004-07-05 |
CN100356571C (zh) | 2007-12-19 |
TW318933B (en) | 1997-11-01 |
US5995439A (en) | 1999-11-30 |
CN1344028A (zh) | 2002-04-10 |
US20010014051A1 (en) | 2001-08-16 |
CN1317764C (zh) | 2007-05-23 |
US6335898B2 (en) | 2002-01-01 |
SG74580A1 (en) | 2000-08-22 |
US6097663A (en) | 2000-08-01 |
KR100441865B1 (ko) | 2004-07-27 |
CN1163484A (zh) | 1997-10-29 |
KR100433738B1 (ko) | 2004-06-04 |
US6246629B1 (en) | 2001-06-12 |
US6069834A (en) | 2000-05-30 |
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