CN1253662A - 半导体元件装配用基板及其制造方法和半导体器件 - Google Patents
半导体元件装配用基板及其制造方法和半导体器件 Download PDFInfo
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- CN1253662A CN1253662A CN98804590A CN98804590A CN1253662A CN 1253662 A CN1253662 A CN 1253662A CN 98804590 A CN98804590 A CN 98804590A CN 98804590 A CN98804590 A CN 98804590A CN 1253662 A CN1253662 A CN 1253662A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 253
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims description 85
- 229920005989 resin Polymers 0.000 claims abstract description 42
- 239000011347 resin Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims description 147
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 239000002184 metal Substances 0.000 claims description 68
- 230000015572 biosynthetic process Effects 0.000 claims description 38
- 238000004080 punching Methods 0.000 claims description 34
- 238000012545 processing Methods 0.000 claims description 30
- 238000007789 sealing Methods 0.000 claims description 21
- 239000004744 fabric Substances 0.000 claims description 18
- 238000010276 construction Methods 0.000 claims description 10
- 239000004745 nonwoven fabric Substances 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 5
- 208000034189 Sclerosis Diseases 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 71
- 239000011889 copper foil Substances 0.000 abstract description 48
- 229910052802 copper Inorganic materials 0.000 abstract description 23
- 239000010949 copper Substances 0.000 abstract description 23
- 229910000990 Ni alloy Inorganic materials 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 81
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 46
- 238000005530 etching Methods 0.000 description 37
- 239000011521 glass Substances 0.000 description 24
- 229910052759 nickel Inorganic materials 0.000 description 23
- 239000007788 liquid Substances 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 16
- 239000003822 epoxy resin Substances 0.000 description 15
- 229920000647 polyepoxide Polymers 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 10
- 238000010023 transfer printing Methods 0.000 description 9
- 239000005030 aluminium foil Substances 0.000 description 8
- 239000011888 foil Substances 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 238000011068 loading method Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 4
- 238000005470 impregnation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000003801 milling Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- -1 polytetrafluoroethylene Polymers 0.000 description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000314 lubricant Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000009812 interlayer coupling reaction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/45012—Cross-sectional shape
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract
公开一种可靠性高、可以小型化、可以降低造价的具有具备用来装配半导体元件的凹部的基板的半导体器件。通过把由将成为布线构件的铜布线(12)、镍合金等的缓冲层(11)和将成为载体层的铜箱(10)构成的可进行拉伸加工的布线体粘接到树脂基板(14、15)上,同时用模具(13)的突起部分(13a)进行冲压加工,形成埋入到基板表面中的布线(2),并且通过在构成布线(2)的两端的将连接到半导体器件(1)的内部连接端子部分和将连接到外部连接端子(5)的外部连接端于部分之间提供台阶,在基板的中央部分形成容纳半导体器件(1)的凹部。
Description
技术领域
本发明涉及装配半导体元件的半导体元件装配用基板、其制造方法和具备已经装配上了半导体元件的半导体元件装配用基板的半导体器件。
发明的背景
最近的半导体器件,借助于集成度的增大和高频化,有望实现多引脚且小型的封装。为此,使用现有的引线框架的周边端子式类型,如果增加端子数则封装将导致大型化。对策之一是缩小端子节距,但是要缩小到0.4mm以下是困难的。
作为导致端子数的增加的对策,有把端子配置成面状的面积阵列式的封装。在该面积阵列封装上,必须有用来把引线从芯片端子引向外部端子的布线基板。如果把外部端子电极设于布线基板的下表面上,则芯片的装配面要分成布线基板的上表面的情况和下表面的情况。在把芯片装配到上表面上的情况下,就要有联结布线基板的上表面和下表面的层间连接。在把芯片装配到布线基板的下表面上的情况下,则不需要这种连接。但是,在把芯片装配到布线基板的下表面上的情况下,为了吸收芯片的厚度和密封所需要的厚度,就必须有凹部。
该凹部被称之为空腔,在空腔存在于下面的情况下,被称作空腔在下构造。为制作该构造,一般地说,可以用在基板上锪孔或者是把基板锪透粘接到基板上的办法制作。在该构造的情况下,由于布线面是同一个面,故芯片连接部分和外部电极的高度变化的情况下,就需要多层构造的布线。可以用这些方法形成满足芯片收容部分和芯片连接部分和外部电极部分之间的立体式的位置关系。
作为面积阵列式半导体封装之一,有把焊料球用作连接端子的网格焊球阵列(BGA)。该BGA与使用现有的引线框架的半导体器件比价格昂贵,人们希望降低其价格。价格高的主要理由是,半导体元件装配用基板的构造或制造工艺比起引线框架来复杂。因此,人们希望开发构造和制造工艺简单的半导体元件装配用基板。
面积阵列式半导体封装所用的布线基板,一般被称之为插入层(interposer)基板,插入层基板粗分起来有薄膜形状、硬板形状等。布线层数为1层2层或3层以上。一般说,布线层数少的造价低。
可以期望最低的造价的是1层的布线构造。在布线存在于插入层基板的至少两面上的情况下,就可以把半导体芯片装配部分和外部端子分放到表面和背面上。但是,如果用1层的布线构造的插入层基板,则半导体芯片装配部分和外部端子就变成为在同一个面上。在这样的1层的布线构造中,就必须把至少与芯片的厚度那么厚的凹部设置在布线面一侧,以便容纳半导体芯片,其制造方法就成了问题。
被称作TAB(Tape Automated Bonding,载带自动键合)和TCP(Tape Carrier Package,载带封装)的插入层基板和封装技术,锪通插入层基板的中央部分设置半导体芯片。在硬板中,仍然锪通插入层基板的中央部分制作半导体芯片收容部分,作为底板,或者是把金属板粘接起来,或者是对插入层基板的中央部分进行锪孔加工形成凹部。若用这种方法,则布线在平面部分上,且在凹部上不存在布线。
发明的概述
本发明是考虑到上述那些问题而发明的,其目的是提供一种半导体元件装配用基板及其制造方法、以及在半导体元件装配用基板上已经装配上半导体元件的半导体器件,上述半导体元件装配用基板可以实现小型化、高可靠性、价格便宜,且可以容易地实现设计和制造方法的标准化。
为了实现上述目的,本发明在具备凹部的半导体元件装配用基板,或者在把半导体元件装配到该凹部中之后,用密封树脂密封后的半导体器件中,其特征是:上述半导体元件装配用基板具备沿该基板表面和上述凹部的基板壁面配置的布线。上述布线由下述部分构成:与在上述凹部开口一侧的该基板表面上设置的外部连接端子连接的外部连接端子部分,与上述所装配的半导体元件连接的内部连接端子部分,和上述外部连接端子部分与上述内部连接端子部分之间的布线部分。上述布线埋入到上述基板表面和上述凹部的基板壁面中,上述内部连接端子部分位于上述凹部内。
例如,上述凹部的基板壁面,假定是具备伸向该凹部的底面方向的预定倾斜角度范围内的倾斜度的壁面,其倾斜度为5~40度,更为理想的是在10~40度的范围内。此外,在用上述凹部的基板壁面的高度G和水平距离L来表示的情况下,要使倾斜构造变成为使两者之比L/G为1.5<L/G<10,更为理想的是2<L/G<10,最为理想的是3<L/G<10。
上述凹部,例如借助于凸型的冲压成型构成。此外,上述凹部也可以作成为形成了多个台阶。
此外,还可以构成为:在上述凹部上,设置通过再次对该凹部进行锪孔加工形成的、用来收容半导体元件的半导体元件收容部分。在这种情况下,上述锪孔加工后的半导体元件收容部分的深度,理想的是比应该装配的半导体芯片的厚度还深。
此外,在上述发明的半导体元件装配用基板和半导体器件中,该基板表面部分的上述外部连接端子与上述凹部内的上述内部连接端子之间的台阶,理想的是在0.05mm以上。
装配于上述凹部中的半导体元件的端子,或者是与上述内部连接端子部分金属丝键合,或者是面朝下直接连接到上述内部连接端子部分上。
此外,在上述发明的半导体元件装配用基板和半导体器件中,上述布线,理想的是设置在除上述凹部的拐角部分之外的壁面区域上。
此外,也可以作成为这样的构成:上述凹部形成于该基板的主平面的大致的中心位置上,在上述凹部内这样地装配半导体元件,使得该元件对于该半导体元件装配用基板的厚度方向处于大致的中央位置。此外,还可以作成为这样的构造:在上述凹部内,把半导体元件装配为对于该基板的厚度方向从中央偏移该基板的厚度的30%以内。此外,还可以把上述凹部的底面区域作成为可以收容多个元件的宽广度,同时,形成连往上述多个元件的布线,并在该凹部内装配多个半导体元件和无源元元件。
此外,在上述发明的半导体元件装配用基板和半导体器件中,上述布线是利用完全由金属构成的,可进行拉伸加工的布线构成体形成的布线,上述可进行拉伸加工的布线构成体,理想的是具有如下构造:至少含有具有构成上述布线的第1金属层,和作为载体层起作用的第2金属层。
此外,还可以构成为:使上述凹部的深度,比将要装配的半导体元件的厚度小,且对于该半导体元件装配用基板的厚度方向,从中央部分把上述凹部的底面锪孔加工成应该装配的该半导体元件的厚度的0.5到2.5倍的范围内的深度。此外,还可以构成为:使上述凹部的深度,比要装配的半导体元件的厚度小,而且,对该凹部的底面进行锪孔加工,并具有使预浸坯料硬化形成的树脂层以便至少使露出来的锪孔底面由无纺布构成。或者,在形成了上述凹部的树脂层的背面上,粘接厚度为0.20mm以上的金属板,并对该凹部的底面实行锪孔加工,使得上述凹部的深度,比要装配的半导体元件的厚度小,而且,在上述金属板上的锪孔深度变成为0.05mm以上。
此外,树脂层的锪孔加工,也可以在达到上述金属板之前结束。
此外,为了实现上述目的,本发明在半导体元件装配用基板的制造方法中,其特征是:采用把至少含有第1金属层和作为其载体层起作用的第2金属层的构造的、全部由金属构成的可进行拉伸加工的布线构成体加压粘接到树脂基板上的同时,在该树脂基板上形成具备预定的倾斜角度范围内的倾斜度的壁面的凹部,剩下上述第1金属层,除去其它的金属层的办法,从该基板表面开始沿上述凹部的基板壁面配置形成:在上述凹部开口一侧的该基板表面上设置的外部端子连接的外部连接端子,与上述装配上的半导体元件连接的内部连接端子,和由上述外部连接端子部分与上述内部连接端子部分之间的布线构成的、埋入到上述基板表面和上述凹部的基板壁面内的布线。
其中,上述可进行拉伸加工的布线构成体的断裂伸长率理想的是2%以上。此外,构成上述可进行拉伸加工的布线构成体的上述载体层的厚度,理想的是处于0.010mm到0.050mm的范围内。此外,上述凹部的基板壁面的倾斜角度范围理想的是在5度以上40度以下,上述凹部的深度理想的是至少应在要容纳的半导体元件的厚度的30%以上。此外,还可以构成为:在上述凹部形成之后,对该凹部的底面进行锪孔加工,在上述锪孔加工之后,进行上述其它的金属层的除去。在有其它的金属层的状态下,通过锪孔加工,可以以良好的精度锪孔加工端部。
此外,为了实现上述目的,本发明在具备用来装配半导体元件的凹部和布线的半导体元件装配用基板的制造方法中,其特征是:使上述凹部的深度比要装配的半导体元件的厚度小,而且,对该凹部的底面进行锪孔加工,在进行上述锪孔加工时,切断连往上述所装配的半导体元件的布线的一部分,使该布线的端部到达锪孔加工所形成的凹部的边缘部分。提高凹部的边缘部分的加工精度。
倘采用本发明,则可以形成能够收容半导体元件的凹部的同时,还可以形成与半导体元件的连接节距对应的微细布线,这对于面积阵列式半导体封装是合适的。应用了该技术的半导体封装,对CSP(ChipScale Package,芯片规模封装),FBGA(Fine Pitch Ball Grid Array,细节距网格焊球阵列),BGA(Ball Grid Array,网格焊球阵列),LGA(LandGrid Array,网格焊台阵列)等是合适的。
附图的简单说明
图1的剖面图示出了本发明的半导体封装的剖面构成的一个例子。
图2的剖面图示出了本发明的半导体封装的剖面构成的另外的例子。
图3剖面图示出了装配了多个半导体元件的本发明的半导体封装的剖面构造例子。
图4的剖面图示出了具有高散热性能的本发明的半导体封装的剖面构造的例子。
图5的剖面图示出了全部由金属构成的可拉伸加工的布线构成体的剖面构造的例子。
图6的剖面图示出了全部由金属构成的可拉伸加工的布线构成体的剖面构造的另外的例子。
图7示出了成型冲压时的材料构成,是在构成中使用无纺布预浸坯料的例子的说明图。
图8示出了成型冲压时的材料构成,是使用去掉了预浸坯料的构成的例子的说明图。
图9示出了为了形成高散热构造的成型冲压时的材料构成,是在背面使用金属板的例子的说明图。
图10的剖面图示出了本发明的半导体器件的另外的例子。
图11的剖面图示出了本发明的半导体器件的另外的例子。
图12的剖面图示出了本发明的半导体器件的另外的例子。
图13的剖面图示出了本发明的半导体器件的另外的例子。
图14的剖面图示出了本发明的半导体器件的制造方法(冲压构成)的另外的例子。
图15的剖面图示出了本发明的半导体器件的制造方法(冲压构成)的另外的例子。
图16的剖面图示出了本发明的半导体器件的制造方法(冲压构成)的另外的例子。
图17的剖面图示出了本发明的半导体器件的另外的例子。
图18的剖面图示出了本发明的半导体器件的另外的例子。
图19的剖面图示出了本发明的半导体器件的制造方法(冲压构成)的另外的例子。
图20的剖面图示出了本发明的半导体器件的制造方法(冲压构成)的另外的例子。
图21(a)的剖面图示出了本发明的半导体元件装配用基板的另外的例子。
图21(b)的剖面图示出了本发明的半导体器件的另外的例子。
图22(a)的剖面图示出了本发明的半导体元件装配用基板的另外的例子。
图22(b)的剖面图示出了本发明的半导体器件的另外的例子。
图23的剖面图示出了本发明的半导体器件的制造方法(冲压构成)。
优选实施方案
参照图1~图4说明应用了本发明的半导体器件的实施方案。另外,本发明不受限于下述实施方案。
本实施方案的半导体器件,如各个图所示,具备:半导体元件(半导体芯片)1;具有用来装配半导体芯片1的凹部或贯通孔部分的绝缘基板7;在绝缘基板7的表面上形成,电连到半导体芯片1上的同时,在实际装配时进行与外部之间的连接的外部电极5;对容纳半导体芯片1的凹部或贯通孔部分进行密封的密封树脂4。
本实施方案的半导体器件,还设有电连半导体芯片1和外部电极5的布线2。该布线2由下述构成:用来和半导体芯片1连接的金属丝3所连接的内部连接端子部分,与外部电极5连接的外部连接端子部分,以及该内部连接端子部分和外部连接端子部分之间的布线。在上述内部连接端子部分和上述外部连接端子部分之间设有台阶。
其中,连接金属丝3和外部电极5之间的布线2,从配置外部电极5的基板表层部分到上述凹部的底面的表层部分为止连续地埋入。此外,半导体芯片1、金属丝3、金属丝3和布线2之间的连接部分(内部连接端子部分)、和布线2的主要部分或所有的部分位于上述凹部内,并用密封树脂进行密封。
在图1~图4中,6是在绝缘基板7的表面上形成的表面绝缘层,在图1~图4中,8是设于绝缘基板7的背面一侧的金属板。
上述半导体器件和半导体元件装配用基板,采用把至少含有第1金属层和用作其载体层的第2金属层的多层构造的全部由金属构成的可进行拉伸加工的布线构成体粘接到树脂基板上,同时在该树脂基板上形成具备预定倾斜角度范围倾斜度的壁面的上述凹部,剩下上述第1金属层,除去其它金属层的办法,通过从该基板表面开始沿上述凹部的基板壁面配置形成下述布线来制造。该布线由在上述凹部开口一侧的该基板表面上设置的与外部连接端子连接的外部连接端子部分,与上述所装配的半导体元件连接的内部连接端子部分,和由上述外部连接端子部分与上述内部连接端子部分之间的布线构成、并埋入到上述基板表面和上述凹部的基板壁面内。
把上述可进行拉伸加工的布线构成体推压粘接到树脂基板上,剩下第1金属层除去其它的金属层后,作为第1金属层的与布线的别的金属层没有接触的3面,和已埋入到树脂基板上且已与别的金属层接触的1面在同一个面上露出来。在本发明中,所谓埋入布线就意味着这样的情况。
在上述可进行拉伸加工的布线构成体中,作为第1金属层的布线与别的金属层接触的布线面(a)的宽度,比与布线面(a)相反的面的布线面(b)的宽度大。在本发明中,宽度大的布线(a)的面露出来,并可以把该面用作为端子,故可以使单位面积的布线密度增大,使高密度化成为可能。
可进行拉伸加工的布线构成体,既可以是至少含有用作布线的第1金属层和用作其载体层的第2金属层的多层构造,也可以是由作为用一个的金属箔的一个面,通过规定的光刻胶图形形成的半刻蚀布线的布线起作用的第1金属层和作为其载体层起作用的第2金属层构成的构造。
上述可进行拉伸加工的布线构成体,在推压粘接到树脂基板上,剩下第1金属层,除去其它的金属层的情况下,也可以把其它的金属层的一部分,例如,内部连接端子部分、外部连接端子部分的部位等剩下。
上述凹部,是用与之对应的凸型的冲压机成型的,采用对其本身或该凹部再次进行锪孔加工的办法,形成将成为半导体芯片1的收容部分的半导体元件收容部分。其中,凹部也可以设置多个台阶。
此外,上述凹部或对该凹部进行锪孔加工形成的半导体收容部分的深度,也可以作成为比应该装配的半导体芯片1的厚度还深。
另外,在对上述凹部进行锪孔加工的情况下,也可以构成为:在进行了该锪孔加工后,除去上述其它的金属层(载体层)。
此外,在本实施方案中,设置布线2的倾斜部分的倾斜角度,规定为与下述该器件用基板的制造方法中的制造条件对应起来设定的、预定的角度范围内。
更为具体地说,上述凹部壁面的倾斜角度,规定为5度~40度以下,较为理想的是为5~25度,更为理想的是5~18度。该倾斜角度,不但根据冲压加工所用的模具突起部分的形状,还要根据形成布线2所用的可进行拉伸加工的布线构成体(转印用金属箔)的物理特性和凹部形成冲压时的制造条件等决定。倾斜角度意味着最大倾斜角度。
此外,如果用倾斜部分的高度G和水平距离L表示(参照图1),则对于本实施方案的半导体器件的倾斜部分来说,规定为1.5<G/L<10,更为理想的是2<G/L<10,最为理想的是3<G/L<10。
此外,上述台阶的深度理想的是要收容的半导体芯片1的厚度的30%。半导体芯片1的厚度,一般说为0.2~0.5mm,故台阶的深度至少必须是0.06~0.15mm。
台阶的深度也会因外部电极5的高度而不同。如图1~图4所示,在把焊料球用做外部电极5的情况下,余裕度会因焊料球的大小而异。例如,若焊料球的直径为0.7mm左右,则进行低的金属丝键合,若把密封树脂4的高度压至0.2mm左右,则可以充分地保持封装与母板基板的间隔。但是,当焊料球的直径小于0.4mm时,保持封装和母板基板的间隔而不设置凹部,将会变得困难起来。
此外,在不使用焊料球的LGA(Land Grid Array,网格焊台阵列)中必须在凹部内设置金属丝键合连接部分。
在装配半导体芯片1的绝缘基板7中,在设置正方形、长方形的台阶的情况下,其拐角部分最容易断裂。此外,即便是达不到断裂的情况下,也会遭受到最大的变形。为此,在拐角部分处,在设置布线和长期可靠性方面就有可能产生问题,理想的是不在这里设置布线。在拐角部分设置布线的情况下,可以在拐角部分处设置R。
此外,在绝缘基板7的凹部中,要把半导体芯片1装配为使得对该基板的厚度方向变成为中央。为此,可以把发生温度循环情况下的该半导体器件的挠曲抑制得很小。
另一方面,在使半导体元件从中央部分偏移开来进行装配的情况下,存在着基板的刚性和密封树脂的硬化收缩量的关系,即便是偏移基板厚度的30%,实质上仍可以确保可靠性。
此外,半导体芯片1的收容部分除去利用冲压机进行的凹部形成之外,还可以如图1或图4所示,对凹部内再次进行锪孔加工的办法,制作各种各样规格的半导体元件装配用基板。锪孔加工,通常在印制布线基板中进行,故可以借助于立铣刀机械式地进行,加工尺寸在XYZ方向上都可以精密地进行控制。
在本实施方案中,锪孔加工深度必须处于容纳芯片厚度的0.5倍~2.5倍的范围内。这关系到金属丝键合连接的容易性。对于高度低的环形金属丝键合来说,在芯片一侧的键合位置与在基板一侧的键合位置的高度变化最好是变化不大。
锪孔加工面的状态,影响与半导体芯片1之间的粘接和与密封树脂之间的粘接。在用布状的连续玻璃纤维形成用来装配半导体芯片1的绝缘基板7的情况下,有时候在锪孔加工面上玻璃纤维和树脂会剥离。在这样的情况下,密封树脂和芯片粘接树脂向锪孔加工面上的沾润性不好,粘接力弱。无纺布的玻璃纤维是短纤维,锪孔加工面是平滑的。因此,密封树脂和芯片粘接树脂向锪孔加工面上的沾润性好,粘接力强。对详细的制造方法,将在以下进行说明。
此外,还可以构成为:在绝缘基板7的中心部分形成对于收容半导体元件厚度不充分的凹部和布线,再对该凹部进行锪孔加工,在锪孔时,切断一部分布线2,使得布线2的端部到达由锪孔所形成的凹部。
此外,如图3所示,还可以构成为:在绝缘基板7的中心部分,形成可以收容多个元件的凹部和布线,在该凹部内装配多个半导体元件或无源元件。布线2用作凹部内的半导体芯片间的布线以及向凹部和向凹部外的布线。
另外,在凹部形成冲压时,如果把金属板设置在背面一侧,则可以同时使作为散热层起作用的金属部分一体化。
此外,如图4所示,也可以构成为:对安装在绝缘基板7的背面上的金属板8进行锪孔加工,并使金属层在因锪孔而形成的凹部的底面上露出来。在为了使金属层露出来的锪孔中使用立铣刀的情况下,必须切入金属面中去。因此,必须加厚金属板8。在使用薄的金属层的情况下,虽然实质上在立铣刀加工中板厚精度的修正是困难的,但是,采用单独使用激光加工、等离子体加工、树脂刻蚀加工等或与立铣刀加工一起使用的办法则可以制作。此外,还可以用对需要进行锪孔的部分反复进行锪除,粘接别的基板或金属板的办法形成。
其次,参照图5~图8对本实施方案的半导体器件的制造方法进行说明。
对实施例1进行说明
在本例的制造方法中,最初,作为用来形成含有布线2的布线的转印用金属箔,例如如图5或图6所示,使用先用电镀法在厚度35微米的铜箔(载体箔)10上形成0.5微米的镍层11,再形成5微米的铜层12这样的3层构造箔。该铜箔是日本电解株式会社生产的。
另外,在本发明中,转印用金属箔全都是用金属构成,只要是不含一切的树脂等的金属箔,也可以用上述构造以外的构造。就是说,转印用的金属箔,只要至少具有载体层(在本例中是铜箔10)和布线层(在本例中是铜层12)即可,在载体层和布线层由同种的金属构成的情况下,则在层间设置由不同金属构成的缓冲层(在本例中是镍合金11)。另外,载体层在后边的工序中用刻蚀法除去。载体层也可以剩下一部分做为端子灵活使用。
此外,转印用金属箔,在加工温度区域(作为冲压机温度的150℃~250℃)中,必须具有2%以上的断裂伸长率(断裂伸长率理想的是100%以下)。转印用金属箔规定载体层的厚度处于0.010mm~0.050mm的范围内。若比这还薄,则处理困难,若比这还厚,则难于顺从模具的形状。载体层可以在转印工序前边,对尚未形成布线的面进行正面刻蚀使之变薄。
在本例中,把将成为布线构件的厚度5微米的铜箔12用通常的光刻胶法形成光刻胶图形进行刻蚀。刻蚀液必须具有不刻蚀镍而刻蚀铜的选择性。在印制板业界中一般常用的碱性刻蚀剂是合适的。厚度35微米的载体箔10被光刻胶保护使得不被刻蚀。
把该带图形的铜箔10~12,用图7所示的构成,在温度180℃、压力25kg/cm2下加热加压2小时。图7示出了这样的构成:在冲压机上模13和冲压机下模17之间,从上边开始,配置多个铝箔18、3层构造的带图形的铜箔(铜箔10、镍合金11和铜布线12),多个玻璃布预浸坯料14,无纺布预浸坯料15,玻璃布预浸坯料14,和作为金属板的铜箔16。
冲压机上模13的突起部分13a的剖面成台形形状,其高度为0.15毫米,其侧面的倾斜角度为45度。作为缓冲垫层把3个厚度25微米的铝箔18插入到模具和铜箔之间进行冲压。预浸坯料使用在玻璃布上含浸了耐热环氧树脂的日立化成工业(株)的产品。
在这里,厚度0.1mm的玻璃布预浸坯料14全部共使用了8个。此外,还用了1个玻璃纤维的厚度为0.2mm的无纺布预浸坯料15。该无纺布预浸坯料插入到第6个和第7个玻璃布预浸坯料之间。用这样的条件制作的玻璃环氧树脂基板要制作多个,同一的布线和凹部形成多个。对之用先前说过的碱性刻蚀剂刻蚀载体铜箔10全面地除去之,其次,用镍选择刻蚀液刻蚀除去镍层11。
用以上的条件就可以在厚度1.0mm的板上形成具有深度为0.15毫米的凹部,且在含有凹部的表面层上连续地形成布线。此外,为了调整深度,再用立铣刀器件从凹部开始对该基板再进行铣削到深度0.55mm,加工为可以装配半导体芯片。阻焊剂层用通常的方法设计,在端子部分上进行5微米厚的镍、0.5微米厚的金的电镀。
在这里,把厚度为0.28mm的半导体芯片1粘接到该凹部内,用金属丝键合进行连接。对半导体芯片1和金属丝键合部分(金属丝3和布线2的内部连接端子部分)用液态树脂4密封,在装上焊料球5之后,切断分离成单个片,制成半导体器件。
用以上的制造方法,例如可以得到图1所示的那样的构造。倘采用本构造,则可以制作与芯片尺寸接近的比较小的封装,可以制作芯片规模封装。
对实施例2进行说明
在本例的制造方法中,也可以在厚度35微米的铜箔(载体箔)上,用电镀法形成0.5微米的镍层,再准备形成了5微米的铜层的3层构造箔。该铜箔使用日本电解株式会社的产品。
在上述厚度5微米的铜层上,用通常的光刻胶法形成并刻蚀光刻胶图形。刻蚀液必须具有不刻蚀镍而刻蚀铜的选择性。在印制板业界中一般常用的碱性刻蚀剂是合适的。厚度35微米的载体箔被光刻胶保护使得不被刻蚀。
对由铜箔10、镍合金11和铜层12构成的带图形的铜箔,用图8所示的构成,在180℃、压力25kg/cm2下2小时加热加压。图8示出了这样的构成:在冲压机上模13和冲压机下模17之间,配置多个铝箔18、3层构造的带图形的铜箔(铜箔10、镍合金11和铜布线12),玻璃布预浸坯料14,多个有锪掉部分的预浸坯料19,多个玻璃布预浸坯料14,和作为金属板的铜箔16。
冲压机上模13的突起部分,高度为0.5mm,其侧面的倾斜度制作成30度。作为缓冲层,在模具和铜箔之间,插入厚度25微米的一个铝箔进行冲压。
预浸坯料使用向玻璃布中含浸耐热环氧树脂的日立化成工业(株)的产品。制作把相当于上述冲压机上模13的突起部分的部分锪掉的预浸坯料,作为层构成使用与突起的高度相当的厚度的量。在这次的突起高度为0.5mm的情况下,使用5个已锪掉0.1mm的预浸坯料和5个未进行锪掉的预浸坯料。
使用多个用以上那样的条件制成的玻璃环氧树脂基板,并形成多个同样的布线和凹部。对之用先前说过的碱性刻蚀剂刻蚀载体铜箔10全面地除去之,其次,用镍选择刻蚀液刻蚀除去镍层11。
借助于以上的操作,就可以在厚度1mm的板上形成具有深度为0.5mm的凹部,在含有凹部的表面层上可以连续地形成布线。阻焊剂层用通常的方法设计,在端子部分上进行5微米厚的镍、0.5微米厚的金的电镀。把半导体芯片1粘接到该凹部内,用金属丝键合法进行连接。用液态树脂4密封芯片和金属丝键合部分。在装上焊料球5之后,切断基板,制成单个片的半导体器件。
倘采用本例的制造方法,就可以得到例如在图2或图3所示的那样的基板背面上再安装上金属板的构造。倘采用本例的构造,由于倾斜部分的倾斜角度小,故倾斜部分变长,虽然封装尺寸会变大,但是,由于不需要锪孔加工工序,所以可以低价格化。此外,如图3所示,具有可以收容多个芯片,且可以同时形成该芯片间的布线的效应。
对实施例3进行说明
在本例的制造方法中,在厚度35微米的铜箔(载体箔)上,用电镀法形成0.5微米的镍层,进而准备形成了5微米的铜层的3层构造箔。该铜箔使用日本电解株式会社的产品。
上述厚度为5微米的铜层,用众所周知的光刻胶法形成光刻胶图形并进行刻蚀。刻蚀液必须具有不刻蚀镍而刻蚀铜的选择性。在印制板业界中一般常用的碱性刻蚀剂是合适的。厚度35微米的载体箔10被抗蚀剂保护使得不被刻蚀。
对用图9示出的该带图形铜箔的构成,在温度180℃、压力25kg/cm2下加热加压2小时。图9示出了这样的构成:在冲压机上模13和冲压机下模17之间,从上边开始,配置多个铝箔18、3层构造的带图形的铜箔(铜箔10、镍合金11和铜布线12),多个玻璃布预浸坯料14、19,和作为金属板的铜板16’。
模具的突起部分的高度为0.20mm,其侧面的倾斜度制作成30度。作为缓冲层,在模具和铜箔之间,插入厚度25微米的一个铝箔18进行冲压。
预浸坯料使用向玻璃布中含浸耐热环氧树脂的日立化成工业(株)的产品。使用6个厚度0.1mm的预浸坯料。在第2个和第3个预浸坯料19中,对相当于模具突起部分的部分进行了锪掉加工。此外,在基板的背面一侧,配置厚度0.40mm的已经进行了粘接粗化处理的铜板并进行冲压。冲压后的总体的厚度为1.0mm。
制造多个用以上那样的条件制成的玻璃环氧树脂基板,并形成多个同样的布线和凹部。对之用先前说过的碱性刻蚀剂刻蚀载体铜箔全面地除去之,其次,用镍选择刻蚀液刻蚀除去镍层。
借助于以上的操作,就可以在厚度1mm的板上形成具有深度为0.20mm的凹部,在含有凹部的表面层上可以连续地形成布线。再用立铣刀器件对该基板进行铣削一直到0.65mm的深度,加工为可以装配半导体芯片。阻焊剂层用通常的方法设计,在端子部分上进行5微米厚的镍、0.5微米厚的金的电镀。
把半导体芯片粘接到该凹部内,用金属丝键合法进行连接。用液态树脂4密封芯片和金属丝键合部分。在装上焊料球5之后,切断制成单个片的半导体器件。
倘采用本例的制造方法,则可以得到例如图4那样的构造。倘采用本构造,就可以用一揽子冲压加工组装散热板,可以提供能够达到低价格、高可靠性的制造方法。
倘采用以上的实施例1到实施例3,则有可能做到小型化、高可靠性和价格便宜,可以提供容易实现设计和制造方法的标准化的、装配半导体元件的半导体元件装配用基板及其制造方法,以及把半导体元件装配到半导体元件装配用基板上的半导体器件。
其次,参照图10~图16说明本发明的半导体器件、基板和制造方法的另外的实施方案。
本实施方案的半导体器件是在其布线基板的一部分上设置凹部,在该凹部内装配半导体芯片而构成的半导体器件,向布线基板的含有凹部的布线基板表层部分埋入连续的布线导体。
说得更具体一点,在具有高度不同的2个以上的表层部分的布线基板中,这是这样的一种基板:例如如图10所示,在第1表层部分上设置与外部连接端子5连接的外部连接端子部分,在第2表层部分上设置与半导体芯片1连接的内部连接端子部分,在第1表层部分和第2表层部分上设置0.05mm以上的台阶,向第1表层部分和第2表层部分及其中间部分的表层内埋入连续的布线导体形成布线2。
该布线基板可以用在铜等的金属箔上设置布线导体,在把树脂层粘接到该金属箔上之际,同时形成凹部的制造方法实现。
此外,作为实现上述布线基板的方法,在对已经设有布线导体的金属箔和含浸过树脂的多层玻璃布进行重叠压缩、形成凹部的布线基板的制造方法中,可以用在预先除去了一部分与凹部对应的玻璃布之后进行压缩的办法制造。
此外,若用本实施方案的另外的形态,则在具有凹部的布线基板中,例如如图11所示,可以提供在金属丝键合部分和芯片粘接部分这2个台阶上形成凹部的布线基板及其制造方法。在该形成2个台阶的凹部的方法中,第1个台阶用具有凸部的模具对预浸坯料进行压缩形成凹部,第2个台阶则可以用切削加工的办法形成。
在一个布线基板上设置多个凹部,在各个凹部内装配上芯片、进行树脂密封、装上焊料球之后,采用切断分离的办法,就可以制造半导体器件。
图10~图13是本实施例中的典型半导体器件的剖面图。
1是半导体芯片,2是布线,3是金属丝,4是密封树脂,5是外部端子电极,6是表面绝缘层,7是绝缘基板,8是金属板,9是绝缘板。
如图11所示,凹部也可以一部分是贯通孔,该半导体器件如图12、13所示,背面可以用金属板8、绝缘板9进行支持。
用图14说明本实施例的半导体器件的制造方法的一个例子。
在厚度为35微米的铜箔(载体箔,日本电解株式会社生产)10上,电镀形成0.5微米的镍层11,再准备已经形成了5微米的铜层的3层构造箔。用通常的光刻胶法使厚度5微米的铜层形成光刻胶图形,进行刻蚀,形成布线导体12。
刻蚀液必须具有刻蚀铜而不刻蚀镍的选择性。在印制板业界中一般常用的碱性刻蚀剂是合适的。厚度35微米的载体箔被光刻胶保护使得不被刻蚀。
对该带图形(布线导体12)的铜箔10,用图14所示的构成,在温度180℃、压力25kg/cm2下加热加压2小时。模具13的突起部分为0.15mm,突起部分的倾斜角制作成90度。作为缓冲层,在模具13、17和铜箔10、16之间插入厚度为50微米的聚四氟乙烯(杜邦公司生产)薄片(未画出)进行冲压。预浸坯料(不锪掉)14使用在玻璃布上含浸有耐热环氧树脂的日立化成的产品。
用这样的条件制作的玻璃环氧树脂基板制成多个,并形成多个同一的布线和凹部。对之用先前说过的碱性刻蚀剂刻蚀载体铜箔,全面地除去。
其次,用镍选择刻蚀液刻蚀除去镍层。用以上的条件在厚度1mm的基板上形成具有深度为0.15毫米的凹部,且在含有凹部的表面层上连续地形成布线。再用铣削器件对该基板进行深度0.5mm的铣削,加工为可以装配半导体芯片1,然后再切断成单个片。把半导体芯片1粘接到凹部内,用金属丝键合进行连接。用液态树脂密封半导体芯片1和金属丝键合部分,制成半导体器件。
参照图15说明本实施例的制造方法的另外的例子。
对与上述图14同样的带图形的铜箔10,用图15所示的构成,在温度180℃、压力25kg/cm2下加热加压2小时。在本例中,模具13的突起部分为0.5mm,突起部分的倾斜角度制作成45度。作为缓冲层,在模具13、17和铜箔10、16之间插入厚度为50微米的聚四氟乙烯(杜邦公司生产)薄片(未画出)进行冲压。预浸坯料(不锪掉)14使用在玻璃布上含浸有耐热环氧树脂的日立化成的产品。制作锪掉与模具突起部分相当部分的预浸坯料15,把相当于突起的高度的厚度量用作层构成。
如本例所示,在突起的高度为0.5mm的情况下,使用5个厚度锪掉0.1mm的预浸坯料15,5个未进行锪掉的预浸坯料14。用这样的条件制作的玻璃环氧树脂基板一次制成多个,并形成多个同一的布线和凹部。对之用先前说过的碱性刻蚀剂蚀刻并全面地除去载体铜箔。其次,用镍选择刻蚀液刻蚀除去镍层。
用以上的条件在厚度1mm的板上形成具有深度为0.5微米的凹部,且在含有凹部的表面层上连续地形成布线。把半导体芯片1粘接到凹部内,用金属丝键合进行连接。用液态树脂密封半导体芯片1和金属丝键合部分。在装上焊料球5后,切断基板,制成单个片的半导体器件。
参照图16说明本实施例的制造方法的另外的例子。
对与上述图14同样的带图形的铜箔10,用图16所示的构成,在温度180℃、压力25kg/cm2下加热加压2小时。在本例中,模具13的突起部分为0.5mm,突起部分的倾斜角度制作成45度。作为缓冲层,在模具13、17和铜箔10、16之间插入厚度为50微米的聚四氟乙烯(杜邦公司生产)薄片(未画出)进行冲压。预浸坯料使用在玻璃布上含浸有耐热环氧树脂的日立化成的产品。
对厚度为0.5mm的玻璃环氧树脂基板18’锪掉与模具突起部分相当的部分。在这种情况下,把未锪掉0.1mm厚度的预浸坯料14置于一个玻璃环氧树脂基板18’和带图形的铜箔10之间,在玻璃环氧树脂基板18’的下部使用3个预浸坯料14。
用这样的条件制作的玻璃环氧树脂基板一次制成多个,并形成多个同一的布线和凹部。对之用先前说过的碱性刻蚀剂刻蚀并全面地除去载体铜箔。其次,用镍选择刻蚀液刻蚀除去镍层。
用以上的条件在厚度1mm的板上形成具有深度为0.5毫米的凹部,且在含有凹部的表面层上连续地形成布线。把半导体芯片1粘接到凹部内,用金属丝键合进行连接。用液态树脂密封半导体芯片1和金属丝键合部分。在装上焊料球后,切断基板,制成单个片的半导体器件。
如上所述,倘采用本实施例,则可以简单的构造,简单的制造工艺,低价格制作半导体器件。
其次,参照图17~图20说明半导体器件、基板和制造方法的另外的实施例。
本实施例的半导体器件,如图17所示,具备半导体芯片1;具备用来装配半导体芯片1的半导体元件收容部分的绝缘基板7;在绝缘基板7的表面上形成,电连到半导体芯片1上,同时在实际装配时进行与外部之间的连接的外部电极5;和密封容纳半导体芯片1的半导体芯片收容部分的密封树脂4,此外,还具备用来与半导体芯片1连接的金属丝3和在与外部电极5之间设置台阶,并沿在该台阶间进行连接的倾斜部分配置的布线2。另外,图中的标号表示在绝缘基板7的表面上形成的表面绝缘层。
本实施例的半导体装置,在例如用以下说明的图20的制造方法制造的具有凹部的半导体器件装配用基板中,再在该凹部的底面进行锪孔加工,形成装配半导体芯片1的半导体器件收容部分。
此外,基板凹部的倾斜角度变成为比45度更为平缓的角度。该倾斜角度由冲压成型用的模具的突起部分的倾斜角度和转印用的铜箔(载体层)10的刚性和冲压压力的平衡等决定。
本实施例的半导体器件,不限定于图17的例子,例如图18所示,也可以构成为:不是在凹部壁面上而是在凹部的底面内配置布线2’,同时在其下方把绝缘层夹在中间设置接地层1801。此外,还可以构成为:具备把接地层1801和外部电极5连接起来的层间连接部分1802。
在本实施例中,并不特别限定接地层1801的形成方法和层间连接的形成方法。例如,使将成为接地层1801的铜箔或铜图形与已经形成的布线基板相向,在其间把预浸坯料等的绝缘粘接薄片夹在中间,再使预浸坯料进行叠层,采用冲压的办法,形成多层构造的基板。
参照图19、图20说明本实施例中的半导体元件装配用基板的制造方法。
在本实施例在制造方法中,和上边说过的2个实施例的制造方法及其基本构成是一样的。以下,主要对不同的部分进行说明,同样的部分则予以省略。
另外,本实施例的制造方法,也和上述2个实施例一样,作为用来形成布线2的转印用金属箔,使用由厚度25微米的铜箔(载体层)10,将成为布线层的铜层12以及载体层10和铜层12之间的缓冲层11构成的3层构造。另外,在图中还同时示出了11、12这两层。
在本例中,把该带图形的铜箔10~12,如图19所示,用温度190℃的热盘1901和顶板1902夹在中间,在压力30kg/cm2下加热加压。在这里,在冲压上模13的冲压下模17之间,从图面上方开始,配置一个铝箔18,3层构造的带图形的铜箔10~12,多个预浸坯料1905、1906和厚度为35微米的铜箔16。
冲压上模13的突起部分其剖面呈现台形形状,其侧面的倾斜角度为30度。预浸坯料1906,在与冲压上模13的突起部分对应的部分处开一个窗口,从上边配置2个。
此外,本实施例的制造方法,并不限定于图19的例子,例如,也可以作成为图20那样的构成。
就是说,把带图形的铜箔10~12,用温度190℃的热盘1901和顶板1902夹在中间,在压力20kg/cm2下加热加压。在这里,在突起部分侧面的倾斜角度为45度的冲压上模13的冲压下模17之间,从图面上方开始,配置3个铝箔18,含有厚度35微米的铜箔10的3层构造箔10~12,1个开有窗口的预浸坯料1906,多个预浸坯料1905和厚度为35微米的铜箔16。
倘采用上述图20的制造方法,就可以制造具备图17所示的那样平缓的倾斜角度的壁面的凹部。
本发明的半导体元件装配用基板,在具备图21(a)、图22(b)那样的凹部的半导体元件装配用基板中,其特征是:具备沿该基板表面和上述凹部的基板壁面配置的布线,上述布线由下述部分构成:与设于上述凹部开口一侧的该基板表面上的外部连接端子连接的外部连接端子部分,与上述所装配的半导体元件连接的内部连接端子部分,和上述外部连接端子部分和上述内部连接端子部分之间的布线部分。上述布线埋入到上述基板表面和上述凹部的基板壁面内,上述内部连接端子部分位于上述凹部内。
在图21(a)、图22(a)中,7是绝缘基板,2是埋入到基板表面和上述凹部的基板壁面内形成的布线。在图21(a)的半导体元件装配用基板中,在凹部的中央部分形成有贯通孔。图21(b)示出了使用了该基板的半导体器件。在图21(b)中,1是在已经装配到基板上的状态下所装配的半导体元件,4是密封树脂,5是外部连接端子。基板凹部形成布线的内部连接端子部分,并用树脂密封。该基板可以用上边说过的方法制造。
在图22(a)的半导体元件装配用基板中,是一种在两端形成凹部的构造,用一次制造多个的办法制造上述基板,可以采用在凹部处切断的办法制造。使用了该基板的半导体器件示于图22(b)。在图22(b)中,1是半导体元件,4是密封树脂,5是外部连接端子。在基板两端的凹部内形成有布线的内部连接端子部分,并用树脂密封。
在本发明中,一次制造多个半导体元件装配用基板,就是说,可以用一揽子冲压的办法一次制造多个。
图23的剖面图示出了冲压机构成,该图示出了用一次制造多个的办法制造半导体元件装配用基板的工序。13是形成有多个凹型13a的冲压机上模,17是冲压机下模,10是形成了多组布线的铜箔,14是预浸坯料。
若用图23的冲压机构成,在上模、下模之间加热加压,则用纵横均等地配置的多个凸型13a,可以一揽子形成多个凹部,同时,经由凹部的壁面,从基板表面的外部连接端子部分,向凹部内的内部连接端子部分连续地埋入形成布线12。在这种情况下,基板表面的外部连接端子部分,可以高精度(高的尺寸稳定性)地保持均等地受到形成相邻的凹部所产生的张力的冲压前的平面的位置。就是说,借助于本发明的半导体元件装配用基板的一次制造多个,可以进行凹部的形成而不会与外部连接端子部分的冲压前的平面的位置产生位置偏离。在基板表面上形成的外部连接端子部分保持冲压前的平面的位置,使得在外部连接端子部分上形成外部连接端子的部位以外形成阻焊剂的情况下的位置对准作业变得容易起来。对于最外侧来说,只要在上模13的边缘的全周上设置虚设凸型13b即可。借助于虚设凸型13b,不仅可以防止最外侧的基板的外部连接端子部分的位置偏离,还可以防止预浸坯料的树脂流动。一次制造多个理想的是7×7以上。
如上所述,在本发明中,可以采用下述工序制造半导体器件。这些工序是:准备冲压机构成的工序,该冲压机构成含有:具有纵横均等地配置的多个突起的冲压机上模、由与上述突起部分已进行了位置对准的规定的布线和金属箔构成的布线构成体、预浸坯料和冲压机下模;埋入工序,采用在冲压机上模和冲压机下模之间进行冲压的办法,在冲压后的基板上一揽子形成多个凹部的同时,把上述规定的布线埋入到上述基板表面和上述凹部的基板壁面内;除去上述金属箔的工序;装配半导体元件的工序;树脂密封凹部的工序;形成外部连接端子的工序;切断分离成单个片的工序。
Claims (37)
1、一种在半导体元件装配用基板上形成凹部,把半导体元件装配到该凹部内之后,用密封树脂进行密封的半导体器件,其特征是:
上述半导体元件装配用基板具备沿该基板表面和上述凹部的基板壁面配置的布线,
上述布线由下述部分构成:与在上述凹部开口一侧的该基板表面上设置的外部连接端子连接的外部连接端子部分,与上述所装配的半导体元件连接的内部连接端子部分,以及上述外部连接端子部分与上述内部连接端子部分之间的布线部分,
上述布线埋入到上述基板表面和上述凹部的基板壁面内,
上述内部连接端子部分位于上述凹部内。
2、权利要求1所述的半导体器件,其特征是:上述凹部的基板壁面具备向该凹部的底面方向延伸的在规定倾斜角度范围内的倾斜。
3、权利要求2所述的半导体器件,其特征是:上述凹部的基板壁面的倾斜角度处于5~40度的范围内。
4、权利要求2所述的半导体器件,其特征是:上述凹部的基板壁面倾斜构造的高度G及其水平距离L之比L/G在1.5<L/G<10的范围内。
5、权利要求1所述的半导体器件,其特征是:上述凹部由凸型冲压成型的办法构成。
6、权利要求1所述的半导体器件,其特征是:上述凹部形成多个台阶。
7、权利要求5所述的半导体器件,其特征是:在上述凹部内,还设有用来收容半导体元件的半导体元件收容部分,该部分是用对该凹部进一步进行锪孔加工的办法形成的。
8、权利要求7所述的半导体器件,其特征是:上述锪孔加工后的半导体元件收容部分的深度比应该装配的半导体元件的厚度还大。
9、权利要求1所述的半导体器件,其特征是:位于该基板表面上的上述外部连接端子部分与上述凹部内的上述内部连接端子部分的台阶高度在0.05mm以上。
10、权利要求1所述的半导体器件,其特征是:装配到上述凹部内的半导体元件的端子和上述内部连接端子部分进行金属丝键合连接。
11、权利要求1所述的半导体器件,其特征是:面朝下地把半导体元件的端子直接连接到上述内部连接端子部分上。
12、权利要求1所述的半导体器件,其特征是:上述布线设于除上述凹部的拐角部分之外的壁面区域上。
13、权利要求1所述的半导体器件,其特征是:上述凹部在该基板的主平面的大体上的中心位置处形成,
在上述凹部内,把半导体元件装配为使得对于该半导体元件装配用基板的厚度方向,大体上变成为中央。
14、权利要求1所述的半导体器件,其特征是:在上述凹部内把半导体元件偏移装配为对于该基板的厚度方向,从中央偏移该基板的厚度的30%以内。
15、权利要求1所述的半导体器件,其特征是:上述凹部在底面区域上具备可以收容多个元件的宽广度的同时,还形成有布向上述多个元件的布线,在该凹部内装配多个半导体元件和无源元件。
16、权利要求1所述的半导体器件,其特征是:上述布线是利用完全由金属构成的,可进行拉伸加工的布线构成体形成的布线,
上述可进行拉伸加工的布线构成体具有如下的多层构造:至少含有具有构成上述布线的第1金属层,和作为载体层起作用的第2金属层。
17、一种具备用来装配半导体元件的凹部的半导体元件装配用基板,其特征是:上述半导体元件装配用基板具备沿该基板表面和上述凹部的基板壁面配置的布线,
上述布线由下述部分构成:与在上述凹部开口一侧的该基板表面上设置的外部连接端子连接的外部连接端子部分,与上述所装配的半导体元件连接的内部连接端子部分,和上述外部连接端子部分与上述内部连接端子部分之间的布线部分,
上述布线埋入到上述基板表面和上述凹部的基板壁面内,
上述内部连接端子部分位于上述凹部内。
18、权利要求17所述的半导体元件装配用基板,其特征是:使上述凹部的深度,比将要装配的半导体元件的厚度小,
相对该半导体元件装配用基板的厚度方向,从中央部分把上述凹部的底面锪孔加工成应该装配的该半导体元件的厚度的0.5到2.5倍的范围内的深度。
19、权利要求17所述的半导体元件装配用基板,其特征是:使上述凹部的深度,比要装配的半导体元件的厚度小,而且,对该凹部的底面进行锪孔加工,
具有使预浸坯料硬化形成的树脂层以便至少使露出来的锪孔底面由无纺布构成。
20、权利要求17所述的半导体元件装配用基板,其特征是:其构成为把金属板粘接到形成了上述凹部的树脂层的背面。
21、一种半导体元件装配用基板的制造方法,其特征是:采用把至少含有第1金属层和作为其载体层起作用的第2金属层的多层构造且全部由金属构成的可进行拉伸加工的布线构成体加压粘接到树脂基板上,同时在该树脂基板上形成具备预定倾斜角度范围内的倾斜度的壁面的凹部,剩下上述第1金属层,除去其它的金属层的办法,
从该基板表面开始沿上述凹部的基板壁面配置形成在上述凹部开口一侧的该基板表面上设置的与外部连接端子连接的外部连接端子部分,与所述装配上的半导体元件连接的内部连接端子部分,和由上述外部连接端子部分与上述内部连接端子部分之间的布线部分构成的、埋入到上述基板表面和上述凹部的基板壁面内的布线。
22、权利要求21所述的半导体元件装配用基板的制造方法,其特征是:上述可进行拉伸加工的布线构成体的断裂伸长率在2%以上。
23、权利要求21所述的半导体元件装配用基板的制造方法,其特征是:构成上述可进行拉伸加工的布线构成体的上述载体层的厚度处于0.010mm到0.050mm的范围内。
24、权利要求21所述的半导体元件装配用基板的制造方法,其特征是:上述凹部的基板壁面的倾斜角度范围为5度以上40度以下,上述凹部的深度为要容纳的半导体元件的厚度的至少30%以上。
25、一种具备用来装配半导体元件的凹部和布线的半导体元件装配用基板的制造方法,其特征是:
使上述凹部的深度比要装配的半导体元件的厚度小,而且,对该凹部的底面进行锪孔加工,
在进行上述锪孔加工时,切断布向上述所装配的半导体元件的布线的一部分,使该布线的端部到达锪孔加工所形成的凹部的边缘部分。
26、权利要求21所述的半导体元件装配用基板的制造方法,其特征是:在形成了上述凹部之后,对该凹部的底面施行锪孔加工,
在上述锪孔加工之后,进行上述其它的金属层的除去。
27、权利要求17所述的半导体元件装配用基板,其特征是:上述凹部的基板壁面具备向该凹部的底面方向延伸预定倾斜角度范围内的斜度。
28、权利要求27所述的半导体元件装配用基板,其特征是:上述凹部的基板壁面的倾斜角度在5~40度的范围内。
29、权利要求27所述的半导体元件装配用基板,其特征是:上述凹部的基板壁面的倾斜构造的高度G及其水平距离L之比L/G在1.5<L/G<10的范围内。
30、权利要求17所述的半导体元件装配用基板,其特征是:上述凹部用凸型冲压机成型的办法构成。
31、权利要求17所述的半导体元件装配用基板,其特征是:上述凹部形成多个台阶。
32、权利要求30所述的半导体元件装配用基板,其特征是:在上述凹部内,还设有用来收容半导体元件的半导体元件收容部分,该部分是用对该凹部进一步进行锪孔加工的办法形成的。
33、权利要求32所述的半导体元件装配用基板,其特征是:上述锪孔加工后的半导体元件收容部分的深度比应该装配的半导体元件的厚度还大。
34、权利要求17所述的半导体器件装配用基板,其特征是:位于该基板表面部分的上述外部连接端子部分与上述凹部内的上述内部连接端子部分的台阶高度在0.05mm以上。
35、一种半导体器件的制造方法,其特征是:具备下述工序:
准备冲压机构成的工序,该冲压机构成含有:具有纵横均等地配置的多个突起部分的冲压机上模、由与上述突起部分已进行了位置对准的规定布线和载体金属箔构成的布线构成体、预浸坯料和冲压机下模;
埋入工序,采用在冲压机上模和冲压机下模之间进行冲压的办法,在冲压后的预浸坯料的基板上一揽子形成多个凹部的同时,把上述规定的布线埋入到上述基板表面和上述凹部的基板壁面内;
除去上述载体金属箔的工序;
装配半导体元件的工序;
树脂密封凹部的工序;
形成外部连接端子的工序;
切断分离成单个片的工序。
36、权利要求35所述的半导体器件的制造方法,其特征是:在冲压机上模的周缘上形成虚设突起部分。
37、一种具备凹部的半导体元件装配用基板,其特征是:
上述半导体元件装配用基板具备沿该基板表面和上述凹部的基板壁面配置的布线,
上述布线由下述部分构成:与在上述凹部开口一侧的该基板表面上设置的外部连接端子连接的外部连接端子部分,与上述所装配的半导体元件连接的内部连接端子部分,和上述外部连接端子部分与上述内部连接端子部分之间的布线部分,
上述布线埋入到上述基板表面和上述凹部的基板壁面内,
上述内部连接端子部分位于上述凹部内。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP112753/1997 | 1997-04-30 | ||
JP11275397 | 1997-04-30 | ||
JP2589698 | 1998-02-06 | ||
JP25896/1998 | 1998-02-06 |
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CN1253662A true CN1253662A (zh) | 2000-05-17 |
CN100370602C CN100370602C (zh) | 2008-02-20 |
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CNB988045907A Expired - Fee Related CN100370602C (zh) | 1997-04-30 | 1998-04-30 | 半导体元件装配用基板及其制造方法和半导体器件 |
Country Status (9)
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US (1) | US6268648B1 (zh) |
EP (1) | EP0980096A4 (zh) |
JP (1) | JP3314939B2 (zh) |
KR (1) | KR100553281B1 (zh) |
CN (1) | CN100370602C (zh) |
AU (1) | AU7082798A (zh) |
HK (1) | HK1027215A1 (zh) |
TW (1) | TW419797B (zh) |
WO (1) | WO1998049726A1 (zh) |
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- 1998-04-30 AU AU70827/98A patent/AU7082798A/en not_active Abandoned
- 1998-04-30 KR KR1019997009932A patent/KR100553281B1/ko not_active IP Right Cessation
- 1998-04-30 TW TW87106686A patent/TW419797B/zh not_active IP Right Cessation
- 1998-04-30 JP JP54683398A patent/JP3314939B2/ja not_active Expired - Fee Related
- 1998-04-30 EP EP98917736A patent/EP0980096A4/en not_active Withdrawn
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CN115662973A (zh) * | 2022-11-09 | 2023-01-31 | 英诺赛科(苏州)半导体有限公司 | 半导体封装器件及其制造方法 |
CN115662973B (zh) * | 2022-11-09 | 2023-12-29 | 英诺赛科(苏州)半导体有限公司 | 半导体封装器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
AU7082798A (en) | 1998-11-24 |
CN100370602C (zh) | 2008-02-20 |
KR100553281B1 (ko) | 2006-02-22 |
EP0980096A1 (en) | 2000-02-16 |
JP3314939B2 (ja) | 2002-08-19 |
KR20010020324A (ko) | 2001-03-15 |
TW419797B (en) | 2001-01-21 |
US6268648B1 (en) | 2001-07-31 |
WO1998049726A1 (fr) | 1998-11-05 |
EP0980096A4 (en) | 2005-03-09 |
HK1027215A1 (en) | 2001-01-05 |
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