CN1228837C - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN1228837C CN1228837C CNB021416885A CN02141688A CN1228837C CN 1228837 C CN1228837 C CN 1228837C CN B021416885 A CNB021416885 A CN B021416885A CN 02141688 A CN02141688 A CN 02141688A CN 1228837 C CN1228837 C CN 1228837C
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- Prior art keywords
- semiconductor device
- electrode
- resin
- semiconductor chip
- semiconductor
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- H—ELECTRICITY
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP274504/2001 | 2001-09-11 | ||
| JP2001274504A JP3868777B2 (ja) | 2001-09-11 | 2001-09-11 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1405881A CN1405881A (zh) | 2003-03-26 |
| CN1228837C true CN1228837C (zh) | 2005-11-23 |
Family
ID=19099523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021416885A Expired - Fee Related CN1228837C (zh) | 2001-09-11 | 2002-09-10 | 半导体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6784537B2 (enExample) |
| JP (1) | JP3868777B2 (enExample) |
| CN (1) | CN1228837C (enExample) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7323361B2 (en) * | 2002-03-29 | 2008-01-29 | Fairchild Semiconductor Corporation | Packaging system for semiconductor devices |
| US6794740B1 (en) * | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
| JP4294405B2 (ja) * | 2003-07-31 | 2009-07-15 | 株式会社ルネサステクノロジ | 半導体装置 |
| US7315081B2 (en) * | 2003-10-24 | 2008-01-01 | International Rectifier Corporation | Semiconductor device package utilizing proud interconnect material |
| JP4312616B2 (ja) * | 2004-01-26 | 2009-08-12 | Necエレクトロニクス株式会社 | 半導体装置 |
| EP1603157B1 (en) * | 2004-05-31 | 2008-01-09 | STMicroelectronics S.r.l. | Vertical conduction power electronic device package and corresponding assembling method |
| JP4468115B2 (ja) | 2004-08-30 | 2010-05-26 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP4153932B2 (ja) | 2004-09-24 | 2008-09-24 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| DE112005002899B4 (de) * | 2004-11-23 | 2016-11-17 | Siliconix Inc. | Halbleiterbauelement mit einem Chip, der zwischen einer becherförmigen Leiterplatte und einer Leiterplatte mit Mesas und Tälern angeordnet ist, und Verfahren zur dessen Herstellung |
| US20060145319A1 (en) * | 2004-12-31 | 2006-07-06 | Ming Sun | Flip chip contact (FCC) power package |
| US20060108635A1 (en) * | 2004-11-23 | 2006-05-25 | Alpha Omega Semiconductor Limited | Trenched MOSFETS with part of the device formed on a (110) crystal plane |
| JP4547279B2 (ja) | 2005-02-08 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| DE102005011159B4 (de) * | 2005-03-09 | 2013-05-16 | Infineon Technologies Ag | Halbleiterbauteil mit oberflächenmontierbaren Außenkontaktflächen und Verfahren zur Herstellung desselben |
| US7230333B2 (en) * | 2005-04-21 | 2007-06-12 | International Rectifier Corporation | Semiconductor package |
| US7402462B2 (en) * | 2005-07-12 | 2008-07-22 | Fairchild Semiconductor Corporation | Folded frame carrier for MOSFET BGA |
| JP4860994B2 (ja) * | 2005-12-06 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US20070215997A1 (en) * | 2006-03-17 | 2007-09-20 | Martin Standing | Chip-scale package |
| US7772036B2 (en) * | 2006-04-06 | 2010-08-10 | Freescale Semiconductor, Inc. | Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing |
| US7768075B2 (en) | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
| US8124460B2 (en) * | 2006-07-17 | 2012-02-28 | Stats Chippac Ltd. | Integrated circuit package system employing an exposed thermally conductive coating |
| DE102007002157A1 (de) * | 2007-01-15 | 2008-07-17 | Infineon Technologies Ag | Halbleiteranordnung und zugehörige Herstellungsverfahren |
| US7879652B2 (en) * | 2007-07-26 | 2011-02-01 | Infineon Technologies Ag | Semiconductor module |
| US8426960B2 (en) * | 2007-12-21 | 2013-04-23 | Alpha & Omega Semiconductor, Inc. | Wafer level chip scale packaging |
| US7955893B2 (en) | 2008-01-31 | 2011-06-07 | Alpha & Omega Semiconductor, Ltd | Wafer level chip scale package and process of manufacture |
| US8680658B2 (en) * | 2008-05-30 | 2014-03-25 | Alpha And Omega Semiconductor Incorporated | Conductive clip for semiconductor device package |
| US8482119B2 (en) * | 2008-06-24 | 2013-07-09 | Infineon Technologies Ag | Semiconductor chip assembly |
| US8373257B2 (en) * | 2008-09-25 | 2013-02-12 | Alpha & Omega Semiconductor Incorporated | Top exposed clip with window array |
| US7851856B2 (en) * | 2008-12-29 | 2010-12-14 | Alpha & Omega Semiconductor, Ltd | True CSP power MOSFET based on bottom-source LDMOS |
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| JP5126278B2 (ja) * | 2010-02-04 | 2013-01-23 | 株式会社デンソー | 半導体装置およびその製造方法 |
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| JP5822468B2 (ja) * | 2011-01-11 | 2015-11-24 | ローム株式会社 | 半導体装置 |
| JP5601282B2 (ja) * | 2011-06-01 | 2014-10-08 | 株式会社デンソー | 半導体装置 |
| JP5851897B2 (ja) * | 2012-03-19 | 2016-02-03 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN103681535B (zh) * | 2012-09-01 | 2016-10-19 | 万国半导体股份有限公司 | 带有厚底部基座的晶圆级封装器件及其制备方法 |
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| JP6386746B2 (ja) * | 2014-02-26 | 2018-09-05 | 株式会社ジェイデバイス | 半導体装置 |
| JP6538396B2 (ja) * | 2015-03-27 | 2019-07-03 | 株式会社ジェイデバイス | 半導体装置 |
| WO2016203764A1 (ja) * | 2015-06-17 | 2016-12-22 | パナソニックIpマネジメント株式会社 | 半導体装置及びモジュール部品 |
| CN108028234B (zh) * | 2015-12-04 | 2021-12-31 | 瑞萨电子株式会社 | 半导体芯片、半导体器件以及电子器件 |
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| JPH09312374A (ja) * | 1996-05-24 | 1997-12-02 | Sony Corp | 半導体パッケージ及びその製造方法 |
| US6075289A (en) * | 1996-10-24 | 2000-06-13 | Tessera, Inc. | Thermally enhanced packaged semiconductor assemblies |
| JP3695893B2 (ja) | 1996-12-03 | 2005-09-14 | 沖電気工業株式会社 | 半導体装置とその製造方法および実装方法 |
| JP3460559B2 (ja) * | 1997-12-12 | 2003-10-27 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
| EP0978871A3 (en) * | 1998-08-05 | 2001-12-19 | Harris Corporation | A low power packaging design |
| JP4260263B2 (ja) * | 1999-01-28 | 2009-04-30 | 株式会社ルネサステクノロジ | 半導体装置 |
| US6215180B1 (en) * | 1999-03-17 | 2001-04-10 | First International Computer Inc. | Dual-sided heat dissipating structure for integrated circuit package |
| US6963141B2 (en) * | 1999-12-31 | 2005-11-08 | Jung-Yu Lee | Semiconductor package for efficient heat spreading |
| TW454321B (en) * | 2000-09-13 | 2001-09-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipation structure |
| TW476147B (en) * | 2001-02-13 | 2002-02-11 | Siliconware Precision Industries Co Ltd | BGA semiconductor packaging with through ventilator heat dissipation structure |
| US6534859B1 (en) * | 2002-04-05 | 2003-03-18 | St. Assembly Test Services Ltd. | Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package |
-
2001
- 2001-09-11 JP JP2001274504A patent/JP3868777B2/ja not_active Expired - Fee Related
-
2002
- 2002-09-10 US US10/237,689 patent/US6784537B2/en not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2003086737A (ja) | 2003-03-20 |
| CN1405881A (zh) | 2003-03-26 |
| JP3868777B2 (ja) | 2007-01-17 |
| US6784537B2 (en) | 2004-08-31 |
| US20030052405A1 (en) | 2003-03-20 |
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