WO2006058030A2 - Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys - Google Patents

Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys Download PDF

Info

Publication number
WO2006058030A2
WO2006058030A2 PCT/US2005/042376 US2005042376W WO2006058030A2 WO 2006058030 A2 WO2006058030 A2 WO 2006058030A2 US 2005042376 W US2005042376 W US 2005042376W WO 2006058030 A2 WO2006058030 A2 WO 2006058030A2
Authority
WO
WIPO (PCT)
Prior art keywords
lead frame
die
solder layer
contact
semiconductor package
Prior art date
Application number
PCT/US2005/042376
Other languages
French (fr)
Other versions
WO2006058030A3 (en
Inventor
Mohammed Kasem
Frank Kuo
Serge Robert Jaunay
Sen Mao
Oscar Ou
Peter Wang
Chang-Sheng Chen
Original Assignee
Siliconix Incorporated
Owyang, King
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/996,149 priority Critical
Priority to US10/996,148 priority patent/US7394150B2/en
Priority to US10/996,149 priority patent/US7238551B2/en
Priority to US10/996,148 priority
Application filed by Siliconix Incorporated, Owyang, King filed Critical Siliconix Incorporated
Priority claimed from CN2005800467643A external-priority patent/CN101443906B/en
Publication of WO2006058030A2 publication Critical patent/WO2006058030A2/en
Publication of WO2006058030A3 publication Critical patent/WO2006058030A3/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73151Location prior to the connecting process on different surfaces
    • H01L2224/73153Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0101Neon [Ne]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A semiconductor package (20) includes a die (14) that is interposed, flip-chip style, between an upper lead frame and a lower lead frame (12). The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers (16,18). The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas 121 and using a double solder reflow process.

Description

SEMICONDUCTOR PACKAGE INCLUDING DIE INTERPOSED BETWEEN CUP-SHAPED LEAD FRAME AND LEAD FRAME HAVING MESAS AND

VALLEYS

Field of the Invention

[0001] This invention relates to packages for semiconductor dice and in particular a package for a semiconductor die such as a vertical MOSFET that has terminals on both sides of the die.

Background

[0002] There is a continuing need for packages for semiconductor dice that are compact, easy to manufacture and economical. There is a particular need for packages that can be used to make connections to terminals on both sides of the die. For example, vertical power MOSFETs, whether of the planar or trench-gated variety, typically have source and gate terminals on the front side of the die and a drain terminal on the backside of the die. The package must therefore provide connectibility to both sides of the die. Similarly, integrated circuits may need a ground contact to the front side to minimize transient effects.

[0003] Vertical trench MOSFETs, in particular, are now widely used in high-end electronic systems such as high-frequency DC-DC converters. These components are used in desktop and notebook computers and servers. In these applications it is critical that the MOSFETs have minimal electrical and thermal resistance.

[0004] U.S. Patent No. 6,744,124 describes a semiconductor die package that has many advantages. The die, for example a trench MOSFET, is mounted in a flip-chip manner inside a cup-shaped lead frame. The drain terminal on the top side of the die is in electrical contact with the cup-shaped lead frame, which has leads that are configured to be coplanar with the bottom surface of the die, on which the source and gate terminals are located.

[0005] While the package described in the above-referenced patent has excellent electrical and thermal properties, there is still a need for a package that has even better thermal and electrical characteristics. Moreover, the package should be sufficiently rugged to be abie to withstand numerous thermal cycles without failure and the lower surface of the die should be protected from scratching.

Summary

[0006] In a semiconductor package according to this invention, a semiconductor die is interposed between an upper lead frame and a lower lead frame. The upper lead frame is cup-shaped and is in electrical contact with a terminal on the top side of the die. The bottom lead frame contains contacts that are in electrical contact with one or more terminals on the bottom of the die. The ends of the upper lead frame are electrically connected to respective contacts which are part of the lower lead frame. The terminals on the bottom of the die are also electrically connected to respective contacts which are part of the lower lead frame.

[0007] The lower lead frame includes a series of raised mesas and valleys. The raised mesas are separated by valleys. The terminals on the bottom of the die are connected to the lower lead frame via a layer of solder which generally covers the mesas of the lower lead frame. The ends of the upper lead frame are lodged in cavities in the lower lead frame.

[0008] The terminal on the top side of the die is connected to upper lead frame via a layer of solder. The surface of the upper lead frame that faces the die has a plurality of grooves which allow greater compliance between the upper lead frame and the die and thereby minimize cracking of the solder layer and/or the die as the package undergoes thermal cycling. The upper surface of the upper lead frame may be left exposed in the finished package to maximize heat transfer from the package.

[0009] According to one aspect of the invention, the relative thickness of the upper solder layer and the lower solder layer are set such that the package is able to undergo numerous thermal cycles without fractures or cracks in either solder layer. Generally, the upper solder layer is thinner than the lower solder layer because the upper solder layer has a wider area of contact between the upper lead frame and the die. [υυiυj i ne relative proportions Deiween the thickness of the upper solder layer and the lower solder layer are achieved by a unique double-reflow process. In accordance with this process, drops of a solder paste are first applied to the lower lead frame, typically on the tops of the mesas. The die is then placed onto the solder paste drops, and the solder paste is reflowed. As the solder paste reflows, it forms a solder layer that flows into the valleys of the lower lead frame.

[0011] After the solder that connects the die with the lower lead frame has been reflowed, solder paste drops are applied to the top side of the die, and the upper lead frame is placed into position over the die, resting on the solder paste drops on the backside of the die. At the same time or as a separate process step, solder paste is placed on the portions of the lower lead frame that will be contacted by the upper lead frame. Then, a second reflow process is performed. As the solder paste reflows, the die is lifted from the lower lead frame to a position intermediate between the upper and lower lead frames, and solder is drawn from the valleys in the lower lead frame. This lifting of the die occurs as a result of the surface tension of the solder. By regulating the amount of solder paste that is applied to the lower and upper lead frames, respectively, the position of the die between the upper and lower lead frames is optimized.

[0012] The resulting package provides excellent electrical and thermal conductivity between the terminals on the top and bottom sides of the die and the upper and lower lead frames, respectively. The contacts for the terminals on the top and bottom sides of the die are located in a single plane, ideal for surface mounting on a printed circuit board or other flat surface. The package can be made very thin and compact and is able to withstand numerous thermal cycles without solder or die cracking.

[0013] While the package of this invention is usable with numerous varieties of semiconductor dice, it is particularly suited to vertical power MOSFETs, wherein the drain terminal is typically on the top side (backside) of the die and the source and gate terminals are on the bottom (front side) of the die.

Brief Description of the Drawings [Oθr4]*Frg7i A'rs a^erspectfVe view of the upper lead frame.

[0015] Fig. 1B is a perspective view of an alternative embodiment of the upper lead frame.

[0016] Fig. 2 is a perspective view of the lower lead frame.

[0017] Fig. 3 is a view of the upper lead frame from below.

[0018] Fig. 4 is a plan view of the lower lead frame from above.

[0019] Fig. 5 is a cross-sectional view of a semiconductor package in accordance with this invention.

[0020] Fig. 6 is a view of the semiconductor package from above.

[0021] Fig. 7 is a view of the semiconductor package from below.

[0022] Fig. 8 is a perspective view of an alternative form of lower lead frame.

[0023] Fig. 9 is a view of the semiconductor die from below.

[0024] Fig. 10 is a view of an small active die and a dummy die that can be substituted in the package for a single larger active die.

[0025] Figs. 11A-11K illustrate the steps of a process of fabricating a semiconductor package of this invention.

[0026] Figs. 12A-12D illustrate several patterns of grooves that may be formed on the underside of upper lead frame.

[0027] Figs. 13A and 13B illustrate the pattern and size of solder paste drops that may be placed on the source contact of the lower lead frame shown in Fig. 8 to provide an acceptable lower solder layer.

[0028] Figs. 14A and 14B illustrate the pattern and size of solder paste drops that may be placed on the backside of the die to provide an acceptable upper solder layer. jDeiailed βeScn'ptibϊf

[0029] Figs. 1 A and 2 are perspective views of an upper lead frame 10 and a lower lead frame 12 in accordance with this invention. Upper lead frame 10 is cup-shaped, with a relatively flat central portion 102 and downward-bent side portions 104 that terminate in feet 106A and 106B. Lower lead frame 12, which is shown after the tie bars (not shown) have been severed, includes four components, drain contacts 122 and 124, a source contact 126, and a gate contact 128. Longitudinal openings 101 and 103 are formed in upper lead frame 10 at the locations where the sheet metal is bent to form side portion 104.

[0030] Upper lead frame 10 and lower lead frame 12 can be made of a copper alloy sheet that is 0.006" to 0.012" thick. The copper alloy may be alloy 194. As indicated, lower lead frame 12 has been partially etched to form a plurality of raised mesas 121 on source contact 126 and a plurality of raised mesas 123 on gate contact 128. Also, the etching process is used to form longitudinal cavities 125 and 127 in drain contacts 122 and 124, respectively. Mesas 121 and 123 and cavities 125 and 127 can be formed by etching the copper alloy of lower lead frame 12 with a chemical solution to a thickness about one-half of its original thickness. Alternatively, mesas 121 and 123 and cavities 125 and 127 may be formed by progressive stamping.

[0031] Fig. 1B is a perspective view of an alternative form of upper lead frame 11, which has side walls 112

[0032] Figs. 3 and 4 illustrate views of the underside of upper lead frame 10 and the top side of lower lead frame 12, respectively. As shown in Fig. 3, a cross-shaped groove 105 is formed by partially etching the lower surface of upper lead frame 10. As described below, groove 105 improves the compliance of upper lead frame 10 with a semiconductor die during thermal cycles. Groove 105 reduces the accumulation of stress during thermal cycles. Groove 105 can be formed by etching upper lead frame 10 to a thickness of 0.002" to 0.006". Figs. 12A to 12D illustrate several patterns of grooves that may be formed on the underside of upper lead frames 10 and 11 , including a single cross (Fig. 12A), a double cross (Fig. 12B), and a series of parallel grooves (Figs. 12C and 12D). However, it has been found that forming too many grooves in upper le"a"d' frame 10 reduces the strength of the lead frame and increases the risk of die cracking during the molding process. During the molding process the flat central portion 102 of the upper lead frame 10 protects the die from differential forces that might crack it.

[0033] Fig. 4 shows a top view of lower lead frame 12 before the tie bars 129 have been severed. Of course, it will be understood by those skilled in the art that lead frame 12 is normally only a single panel in an array of panels each of which will form a single package and all of which are processed simultaneously. The orthogonal dashed lines indicate where lower lead frame 12 will be severed by a dicing saw or punch tool when the packages are singulated. The hatched areas represent the unetched portions of lower lead frame 12; the open areas represent the areas that are etched to form mesas 121 and 123 and cavities 125 and 127.

[0034] Fig. 5 shows a cross-sectional view of a semiconductor package 20 which contains upper lead frame 10 and lower lead frame 12. Fig. 5 is taken at the section line 5-5 shown in Figs. 3 and 4. Package 20 includes a semiconductor die 14 which is interposed between upper lead frame 10 and lower lead frame 12. In this embodiment semiconductor die 14 contains a vertical trench MOSFET with a drain terminal (not shown) on the top surface of die 14 and source and gate terminals (not shown) on the lower surface of die 14.

[0035] The drain terminal on the top surface of die 14 is electrically and thermally connected to upper lead frame 10 by an upper solder layer 16, which as shown extends into groove 105 on the bottom surface of upper lead frame 10. Foot 106A of upper lead frame 10 extends into cavity 127 of drain contact 124 and makes electrical and thermal contact with drain contact 124 via a solder layer 17A. Similarly, foot 106B of upper lead frame 10 extends into cavity 125 of drain contact 122 and makes electrical and thermal contact with drain contact 122 via a solder layer 17B. As described below, solder layers 17A and 17B may be deposited at the same time. In some embodiments cavities 125 and 127 may be omitted in the drain contacts. tυυjoj rvererπng again TO ifre bottom surface of die 14, the source terminal (not shown) is electrically and thermally connected to source contact 126 via a solder layer 18A, which extends from top surfaces of the mesas 121 to the source terminal of die 14. Similarly, the gate terminal of die 14 (not shown) is electrically and thermally connected to gate contact 128 via a solder layer 18B, which extends from top surfaces of the mesas 123 to the gate terminal of die 14. As described below, Solder layers 18A and 18B may be deposited at the same time as a lower solder layer 18.

[0037] The remaining areas of package 20 are filled with a molding compound, which is typically a plastic such as Nitto 8000CH4, and which forms a protective capsule for die 14 and other components of package 20. Note in particular that the molding compound 13 fills the area between mesas 121 over the source contact 126.

[0038] As indicated in Fig. 5, the lower solder layer 18 is generally thicker than the upper solder layer 16. Therefore, lower solder layer 18 is more rugged and is better able to withstand differential lateral expansion between die 14 and the elements of lower lead frame 12. On the other hand, upper solder layer 16 has a wider area of contact between die 14 and upper lead frame 10. This increases the strength of upper solder layer 16 and consequently upper solder layer 16 does not need to be as rugged as lower solder layer 18. In addition, the cross groove 105 that is formed in upper lead frame 10 reduces the lateral stress that upper lead frame 10 imposes on upper solder layer 16, and this also lessens the tendency of upper solder layer 16 to crack or fracture as package 20 experiences repeated thermal cycles. Typically, the ratio of the thickness between upper solder layer 16 and lower solder layer 18 is in the range of 1 :10 to 1 :2. For example, in one embodiment the upper solder layer 16 was 1.1 mils thick and the lower solder layer 18 was 2.8 mils thick. In another embodiment, the upper solder layer 16 was 0.4 mils thick and the lower solder layer 18 was 3.0 mils thick. Generally, where satisfactory results have been obtained, the lower solder layer is greater than 2.0 mils thick and the upper solder layer is less than 1.2 mils thick.

[0039] Figs. 6 and 7 show top and bottom views, respectively, of semiconductor package 20. Note with respect to Fig. 6 that the top surface of upper lead frame 10 is left exposed to improve the ability ot package 20 to transfer heat trom die 14 to the external environment (e.g., atmosphere).

[0040] Different patterns of raised mesas may be formed on the lower lead frame. For example, Fig. 8 illustrates a bottom view of a lower lead frame 15 wherein the source contact 152 is divided into six paddle-like sections 152A-152F, which are separated by slots formed in source contact 152. Each of sections 152A-152F has four raised mesas 154. Gate contact 156 and drain contacts 158 are similar to the gate and drain contacts in lower lead frame 12, shown in Fig. 4.

[0041] Preferably a silicone-based die coating is applied to the passivation layer of the die to help prevent cracking of the passivation layer. One die coating that has been found acceptable is Dow Corning HIPEC Q1 - 4939. Packages having a lower lead frame of the kind shown in Fig. 8 along with a die coating have survived 1000 thermal cycles from -65° C to +150° C with no die, solder or passivation cracking.

[0042] Figs. 11A-11K illustrate a process of fabricating the semiconductor package 20 shown in Fig. 5. Note that Figs. 11A-11K are schematic and not drawn to scale.

[0043] As shown in Fig. 11 A, the process begins with lower lead frame 12, which is formed in a conventional manner (typically by stamping). Lower lead frame 12 is then partially etched, preferably using the process described above, to form mesas 121 on source contact 126, mesas 123 on gate contact 128, cavity 125 in drain contact 122, and cavity 127 in drain contact 124.

[0044] As shown in Fig. 11 B, solder paste drops 201 are dispensed on the top surfaces of mesas 121 and solder paste drops 203 are dispensed on the top surfaces of mesas 123. As described below, the volume of drops 201 and 203 is set to help assure the correct thickness of the upper and lower solder layers in the finished package. Fig. 13A shows a pattern of solder paste drops 202 that are placed on the mesas 154 of the lead frame 15, illustrated in Fig. 8. As shown in Fig. 13B, the diameter of each of solder paste drops 202 is 1.0 mm and the height of each of solder paste drops 202 is 0.34 mm, yielding a volume of 0.00027 cc. Since there are a total ότ six αrops zu-Ton me source contact of lead frame 15, the combined volume of the solder paste drops 202 is about 0.00162 cc. When the process is completed, as described below, this produces a lower solder layer having a thickness of 3.5 mils.

[0045] Next, as shown in Fig. 11 C, semiconductor die 14 is placed onto solder paste drops 201 and 203, with source terminal 14S in contact with drops 201 and gate terminal in contact with drops 203.

[0046] The solder paste is then reflowed by heating it. This first reflow causes the solder to flow into the valleys between and around the mesas 121 and 123, and die 14 settles downward towards source contact 126 and gate contact 128. The result is shown in Fig. 11 D. It is preferable to restrict the reflowing solder to defined areas of the die, since in the finished package a large, laterally expansive solder layer between lower lead frame 12 and die 14 tends to impose a greater stress on the solder layer and the die. Therefore, it is desirable to structure the die 14 as shown in Fig. 9, with segregated source and drain pads, each of which is surrounded by a passivation layer. Fig. 9 is a view of the front side of die 14. The source terminal is separated into separate source pads 150, 152, 154, 156, 160, and gate pad 158 is connected to the gate terminal. As the solder paste drops melt, the passivation layer 170 acts as a barrier that prevents the solder from flowing from one pad to another.

[0047] As shown in Fig. 11 E, solder paste drops 205 are then dispensed in cavities 125 and 127 and, as shown in Fig. 11 F, solder paste drops 207 are dispensed on the backside of die 14, in contact with the drain terminal. Alternatively, solder paste drops 207 can be deposited in the same step as solder paste drops 205. The size of solder paste drops 207 is set at the correct level in relationship to the size of solder paste drops201 and 203, to provide the desired thicknesses of the upper and lower solder layers in the finished package. Fig. 14A shows an alternative pattern of solder paste drops 208 that may be placed on the backside of die 14. As shown in Fig. 14B, the diameter of each of solder paste drops 208 is 1.4 mm and the height of each of solder paste drops 208 is 0.45 mm, yielding a volume of 0.00068 cc. Since there are a total of four drops 208 on the backside of die 14, the combined volume of the solder paste drό^' 208"i^abo'UtO:002¥ltcc. When the process is completed, as described below, this produces an upper solder layer having a thickness of 0.8 mil.

[0048] As shown in Fig. 11 G, upper lead frame 10 is placed on top of solder paste drops 205 and 207, with feet 106 in contact with solder paste drops 205.

[0049] Next, a second reflow process is carried out. In the second reflow process, solder paste drops 205 and 207 melt, causing upper lead frame 10 initially to settle towards die 14. As the solder continues to melt, however, the surface tension of the resulting liquid solder tends to pull die 14 upward towards upper lead frame 10. This lifts die 14 away from lower lead frame 12. As a result, the solder between die 14 and source contact 126 is drawn out of the valleys between mesas 121 and onto the top surfaces of the mesas 121. Successive stages of this process are shown in Figs. 11 H to 11 J. Figs. 11H and 111 illustrate the flattening of the solder paste drops 207, and Fig. 11 J illustrates the formation of upper solder layer 16 and lower solder layers 18A and 18B. Because of the surface tension in the upper solder layer 16, die 14 is suspended at a desired position between upper lead frame 10 and lower lead frame 12. As indicated above, the actual location of die 14 is primarily determined by the respective sizes of solder paste drops 201 and 207 (and to a lesser degree the sizes of solder paste drops 203). Through a trial-and-error process, those of skill in the art will be able to adjust the sizes of the solder paste drops to produce upper and lower solder layers having the desired thicknesses.

[0050] Finally, the structure is processed in transfer molding equipment and the tie bars are severed to produce semiconductor package 20, shown in Fig. 11 K. Preferably, a Boschman Flexstar 3020 Molding System is used to perform the molding and a Disco DAD341 saw machine is used to separate the packages. Techniques described in U.S. Patent No. 5,098,626 and No. 6,613,607, each of which is incorporated herein by reference in its entirety, may be used to advantage. It has been found useful to modify the Boschman equipment by substituting an insert that has a flat lower surface instead of a lower surface that has a cavity. The lower surface of the insert contacts the top surface of the upper lead frame (through a seal film) and "it has been found "tπat eliminating me cavity reduces the tendency of the die to crack under the pressure of the insert.

[0051] The semiconductor package described herein is extremely efficient and rugged and can be adapted to various die sizes. For example, a "dummy" die may be mounted inside the package if the active die is too small to be mounted by itself. For example, as shown in Fig. 10, if the active die 14A is too small is to be mounted in package 20, a dummy die 14B can be mounted next to die 14A so that both dice 14A and 14B occupy essentially the same space as die 14 shown in Fig. 5.

[0052] Although the present invention is illustrated in connection with specific embodiments for instructional purposes, the present invention is not limited thereto. Various adaptations and modifications may be made without departing from the scope of the invention. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.

Claims

Claims1 We claim:
1. A semiconductor package comprising: a semiconductor die having a first terminal on a top surface of said die and at least a second terminal on a bottom surface of said die; an upper lead frame in electrical contact with said first terminal, said upper lead frame having bent portions extending downward around a pair of opposite edges of said semiconductor die, each of said bent portions terminating in a foot; a lower lead frame comprising at least two contacts, a first one of said contacts having a plurality of raised mesas formed in a top surface of said first contact, said mesas being separated by valleys; a first solder layer connecting said first terminal of said die to said upper lead frame; a second solder layer connecting said second terminal of said die to said first contact of said lower lead frame.
2. The semiconductor package of Claim 1 wherein said second solder layer is thicker than said first solder layer.
3. The semiconductor package of Claim 1 wherein a groove is formed in a lower surface of said upper lead frame.
4. The semiconductor package of Claim 3 wherein said groove is formed in the shape of a cross on said lower surface of said upper lead frame.
5. The semiconductor package of Claim 3 wherein said first solder layer extends into said groove.
6. The semiconductor package of Claim 1 wherein said second solder layer covers a top surface of each of said mesas.
7. The semiconductor package of Claim 1 comprising a third solder layer connecting said upper lead frame to a second one of said contacts of said lower lead frame.
8. The semiconductor package of Claim 7 wherein. said second one of said contacts has a cavity formed in a top surface thereof. y. Tne semrconauctor package of Claim 1 comprising a protective capsule formed of a molding compound, said molding compounding separating said at least two contacts.
10. The semiconductor package of Claim 9 wherein said valleys contain said molding compound.
11. The semiconductor package of Claim 1 wherein a passivation layer overlies a portion of said die, said passivation layer being coated with a silicone-based layer.
12. The semiconductor package of Claim 1 wherein said upper lead frame comprises a pair of sidewalls that extend downward over a second pair of opposite edges of said die.
13. A package for a vertical MOSFET, said package comprising: a semiconductor die containing said vertical MOSFET, said die having a drain terminal on a top surface of said die and a source terminal and a gate terminal on a bottom surface of said die; an upper lead frame in electrical contact with said drain terminal, said upper lead frame having bent portions extending downward around opposite edges of said semiconductor die, each of said bent portions terminating in a foot; a lower lead frame comprising a source contact, a gate contact, and a pair of drain contacts, each of said source contact and said gate contact having a plurality of raised mesas formed in a top surface thereof, said raised mesas separated by valleys, said source, gate and drain contacts having coplanar bottom surfaces; a first solder layer connecting said drain terminal to said upper lead frame; a second solder layer connecting said source terminal to said source contact; a third solder layer connecting said gate terminal to said gate contact; and a'prdtective capsule Tormed of a molding compound, portions of said molding compound separating said first and second contacts.
14. The package of Claim 13 wherein said source contact comprises a plurality of paddle-like sections separated by slots, each of said paddle sections comprising a plurality of said raised mesas.
15. A method of fabricating a semiconductor package comprising: providing a lower lead frame, said lower lead frame having at least a first contact and a second contact; partially etching said lower lead frame so as to form a plurality of raised mesas in said first contact, said mesas being separated by valleys; dispensing a first plurality of solder paste drops on said mesas; placing a semiconductor die on said first plurality of solder paste drops; performing a first reflow of said first plurality of solder paste drops so as form a first solder layer between said die and said lower lead frame; dispensing a second plurality of solder paste drops on a top surface of said die; placing an upper lead frame on said second plurality of solder paste drops, said upper lead frame comprising bent portions at opposite ends of said upper lead frame, each of said bent portions extending downward and terminating in a foot; performing a second reflow of said plurality of solder paste drops and said first solder layer.
16. The method of Claim 15 comprising dispensing a third plurality of solder paste drops in said cavity and bringing said foot into contact with one of said third plurality of solder drops.
17. The method of Claim 15 wherein during said second reflow a portion of said first solder layer flows from said valleys.
18. The method of Claim 15 wherein a vertical distance between said lower lead frame and said die increases during said second reflow.
PCT/US2005/042376 2004-11-23 2005-11-22 Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys WO2006058030A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/996,149 2004-11-23
US10/996,148 US7394150B2 (en) 2004-11-23 2004-11-23 Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
US10/996,149 US7238551B2 (en) 2004-11-23 2004-11-23 Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
US10/996,148 2004-11-23

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN2005800467643A CN101443906B (en) 2004-11-23 2005-11-22 Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
DE112005002899.2T DE112005002899B4 (en) 2004-11-23 2005-11-22 Semiconductor device with a chip, which is arranged between a cup-shaped printed circuit board and a circuit board with mesas and valleys, and method for its preparation
JP2007543413A JP4575955B2 (en) 2004-11-23 2005-11-22 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
WO2006058030A2 true WO2006058030A2 (en) 2006-06-01
WO2006058030A3 WO2006058030A3 (en) 2009-04-02

Family

ID=36498476

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/042376 WO2006058030A2 (en) 2004-11-23 2005-11-22 Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys

Country Status (3)

Country Link
JP (1) JP4575955B2 (en)
DE (1) DE112005002899B4 (en)
WO (1) WO2006058030A2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010534937A (en) * 2007-07-27 2010-11-11 フェアチャイルド・セミコンダクター・コーポレーション Double-side cooled integrated power device package, module and manufacturing method
ITMI20111218A1 (en) * 2011-06-30 2012-12-31 St Microelectronics Srl of high speed power device? switching
JP2013517624A (en) * 2010-01-19 2013-05-16 ヴィシェイ−シリコニックス Semiconductor package and method
US8723311B2 (en) 2011-06-30 2014-05-13 Stmicroelectronics S.R.L. Half-bridge electronic device with common heat sink on mounting surface
US8755188B2 (en) 2011-06-30 2014-06-17 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink
US8817475B2 (en) 2011-06-30 2014-08-26 Stmicroelectronics S.R.L. System with shared heatsink
US8837153B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. Power electronic device having high heat dissipation and stability
US8837154B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. System with stabilized heatsink
US9105598B2 (en) 2011-06-30 2015-08-11 Stmicroelectronics S.R.L. Package/heatsink system for electronic device
US9275943B2 (en) 2011-06-30 2016-03-01 Stmicroelectronics S.R.L. Power device having reduced thickness

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010147201A1 (en) * 2009-06-19 2010-12-23 株式会社安川電機 Power conversion device
WO2013157172A1 (en) * 2012-04-20 2013-10-24 パナソニック株式会社 Semiconductor package and method for producing same, semiconductor module, and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030052408A1 (en) * 2000-04-13 2003-03-20 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6744124B1 (en) * 1999-12-10 2004-06-01 Siliconix Incorporated Semiconductor die package including cup-shaped leadframe
US6762067B1 (en) * 2000-01-18 2004-07-13 Fairchild Semiconductor Corporation Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails
US7119447B2 (en) * 2001-03-28 2006-10-10 International Rectifier Corporation Direct fet device for high frequency application
US6870254B1 (en) * 2000-04-13 2005-03-22 Fairchild Semiconductor Corporation Flip clip attach and copper clip attach on MOSFET device
JP4085563B2 (en) * 2000-08-24 2008-05-14 富士電機ホールディングス株式会社 Power semiconductor module manufacturing method
JP4102012B2 (en) * 2000-09-21 2008-06-18 株式会社東芝 Semiconductor device manufacturing method and semiconductor device
JP2002315357A (en) * 2001-04-16 2002-10-25 Hitachi Ltd Inverter device
JP3868777B2 (en) * 2001-09-11 2007-01-17 株式会社東芝 Semiconductor device
JP2003188335A (en) * 2001-12-14 2003-07-04 Eastern Japan Semiconductor Technologies Inc Semiconductor device and its manufacturing method
JP2004214368A (en) * 2002-12-27 2004-07-29 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030052408A1 (en) * 2000-04-13 2003-03-20 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010534937A (en) * 2007-07-27 2010-11-11 フェアチャイルド・セミコンダクター・コーポレーション Double-side cooled integrated power device package, module and manufacturing method
KR101534463B1 (en) * 2010-01-19 2015-07-07 비쉐이-실리코닉스 Semiconductor package and method
JP2013517624A (en) * 2010-01-19 2013-05-16 ヴィシェイ−シリコニックス Semiconductor package and method
US8837153B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. Power electronic device having high heat dissipation and stability
US8755188B2 (en) 2011-06-30 2014-06-17 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink
US8817475B2 (en) 2011-06-30 2014-08-26 Stmicroelectronics S.R.L. System with shared heatsink
US8723311B2 (en) 2011-06-30 2014-05-13 Stmicroelectronics S.R.L. Half-bridge electronic device with common heat sink on mounting surface
US8837154B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. System with stabilized heatsink
US8860192B2 (en) 2011-06-30 2014-10-14 Stmicroelectronics S.R.L. Power device having high switching speed
ITMI20111218A1 (en) * 2011-06-30 2012-12-31 St Microelectronics Srl of high speed power device? switching
US9105598B2 (en) 2011-06-30 2015-08-11 Stmicroelectronics S.R.L. Package/heatsink system for electronic device
US9275943B2 (en) 2011-06-30 2016-03-01 Stmicroelectronics S.R.L. Power device having reduced thickness
US9786516B2 (en) 2011-06-30 2017-10-10 Stmicroelectronics S.R.L. Power device having reduced thickness

Also Published As

Publication number Publication date
JP4575955B2 (en) 2010-11-04
DE112005002899B4 (en) 2016-11-17
WO2006058030A3 (en) 2009-04-02
DE112005002899T5 (en) 2007-10-04
JP2008533694A (en) 2008-08-21

Similar Documents

Publication Publication Date Title
TWI573223B (en) Integrated circuits protected by substrates with cavities, and methods of manufacture
KR101496085B1 (en) Packaging with interposer frame
US9218987B2 (en) Method for top-side cooled semiconductor package with stacked interconnection plates
US8361839B1 (en) Structure and method for power field effect transistor
US9698080B2 (en) Conductor structure for three-dimensional semiconductor device
US8183662B2 (en) Compact semiconductor package with integrated bypass capacitor
US20160379940A1 (en) Semiconductor device and methods of manufacturing semiconductor devices
KR101159016B1 (en) Embedded die package using a pre-molded carrier
US6562647B2 (en) Chip scale surface mount package for semiconductor device and process of fabricating the same
KR101360163B1 (en) Semiconductor die package including multiple dies and a common node structure
US7319266B2 (en) Encapsulated electronic device structure
US6798044B2 (en) Flip chip in leaded molded package with two dies
US8058104B2 (en) Reversible leadless package and methods of making and using same
US7112871B2 (en) Flipchip QFN package
US8481368B2 (en) Semiconductor package of a flipped MOSFET and its manufacturing method
JP4699353B2 (en) Alternative FLMP package design and package manufacturing method
US7655500B2 (en) Packaged microelectronic devices and methods for packaging microelectronic devices
US6521987B1 (en) Plastic integrated circuit device package and method for making the package
US8513059B2 (en) Pre-molded clip structure
US10418319B2 (en) Method of manufacturing a semiconductor device
US7145225B2 (en) Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
JP2013219369A (en) Method and device for flip-chip-on-lead semiconductor package
US6611052B2 (en) Wafer level stackable semiconductor package
US6717245B1 (en) Chip scale packages performed by wafer level processing
US5986209A (en) Package stack via bottom leaded plastic (BLP) packaging

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200580046764.3

Country of ref document: CN

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007543413

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1120050028992

Country of ref document: DE

RET De translation (de og part 6b)

Ref document number: 112005002899

Country of ref document: DE

Date of ref document: 20071004

Kind code of ref document: P

122 Ep: pct application non-entry in european phase

Ref document number: 05852032

Country of ref document: EP

Kind code of ref document: A2