CN116053148A - 具有双侧冷却的功率模块封装 - Google Patents
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Abstract
本发明涉及具有双侧冷却的功率模块封装。多芯片封装包含安装在第一引线框(310)上的第一半导体装置(301),其中所述第一半导体装置的主要产热表面朝向所述第一引线框的散热区域(312)定向且接触所述散热区域(312)。第二半导体装置(302)被安装于第二引线框(320)上,其中所述第二半导体装置的主要产热表面朝向所述第二引线框的散热区域(322)定向且接触所述散热区域(322)。
Description
分案申请的相关信息
本申请是分案申请。本申请的母案为申请号“201710069208.2”、申请日为2017年2月8日且发明名称为“具有双侧冷却的功率模块封装”的中国发明专利申请。上述申请要求了申请日为2016年2月25日的美国专利申请“15/054,117”的优先权。
技术领域
本发明涉及损耗大量功率的集成电路的紧凑封装,且特定来说,涉及多功能装置。
背景技术
一些集成电路具有无引线封装,例如将集成电路物理且电耦合到印刷电路板的四方扁平无引线(QFN)及双扁平无引线(DFN)装置。扁平无引线装置(也被称为微引线框(MLF)及小轮廓无引线(SON)装置)是基于将集成电路连接到印刷电路板的表面而无需印刷电路板中的穿孔的表面安装技术。在一些实例中,扁平无引线封装是通常使用平面铜引线框衬底制造的准芯片级塑料囊封封装。封装上的周边凸面(land)提供与印刷电路板的电耦合。所述凸面用作接触件且可被称为集成电路内部的引线;然而,引线并未延伸超过集成电路封装的边界。
一些集成电路及其它电子装置具有耦合到所述电路及装置内的电子组件的导电夹片。所述夹片可处于一个平面上,且所述电路及装置的引线或接触件可处于第二平面上。夹片被焊接到引线或以其它方式被电及/或机械接合到引线。
发明内容
本发明中描述的标的物的一个新颖方面可被实施于一种多芯片封装中,所述多芯片封装包括:第一半导体装置,其被安装于第一引线框上,其中所述第一半导体装置的主要产热表面朝向所述第一引线框的散热区域定向且接触所述散热区域;第二半导体装置,其被安装于第二引线框上,其中所述第二半导体装置的主要产热表面朝向所述第二引线框的散热区域定向且接触所述散热区域;其中所述第一引线框是与突出接触区域共面的经蚀刻的引线框,且所述第二引线框是与接触所述第一引线框上的对应突出接触区域的突出接触区域共面的经蚀刻的引线框;且其中所述第一引线框的所述散热区域的表面被暴露于所述多芯片封装的第一侧上,且所述第二引线框的所述散热区域的表面被暴露于所述多芯片封装的与所述第一侧相对的第二侧上。
本发明中描述的标的物的另一新颖方面可被实施于一种用于制造多芯片封装的方法中,所述方法包括:通过蚀刻导电材料片材制造具有散热区域的上引线框及具有散热区域的下引线框;将第一芯片的第一侧附接到所述下引线框的所述散热区域;将第二芯片的第一侧附接到所述上引线框的所述散热区域;将所述上引线框叠加于所述下引线框上方,使得所述第一芯片的第二侧被附接到所述第二引线框的所述散热区域且所述第二芯片的第二侧被附接到所述第一引线框的所述散热区域以形成组合件;及使用模制化合物囊封所述组合件,使得所述上引线框的所述散热区域的表面及所述下引线框的所述散热区域的表面被暴露。
本发明中描述的标的物的另一新颖方面可被实施于一种多芯片封装中,其包括:第一半导体装置,其被安装于第一引线框上,其中所述第一半导体装置的漏极区域朝向所述第一引线框的散热区域定向且接触所述散热区域,且其中所述第一半导体装置的源极区域朝向第二引线框定向且接触所述第二引线框;第二半导体装置,其被安装于所述第二引线框上,其中所述第二半导体装置的漏极区域朝向所述第二引线框的散热区域定向且接触所述散热区域,且其中所述第二半导体装置的源极区域朝向所述第一引线框定向且接触所述第一引线框;且其中所述第一引线框的所述散热区域的表面被暴露于所述多芯片封装的第一侧,且所述第二引线框的所述散热区域的表面被暴露于所述多芯片封装的与所述第一侧相对的第二侧。
附图说明
现将仅通过实例且参考附图描述根据本发明的特定实施例:
图1是示范性场效应晶体管(FET)单元的横截面图;
图2是可包含若干FET单元的示范性功率装置的3D视图;
图3到4是包含经安装以允许双侧冷却的两个功率装置的示范性封装的侧视图;
图5是图3到4的封装的俯视图;
图6是经完整模制的封装的3D视图;
图7到9说明用于制造具有双侧冷却的封装的过程;及
图10是具有双侧冷却的封装的另一实施例的侧视图。
从附图及以下详细描述将明白本实施例的其它特征。
具体实施方式
现将参考附图详细描述本发明的特定实施例。为了一致性,由相同参考数字标示各个图中的相同元件。在本发明的实施例的以下详细描述中,陈述若干特定细节以便提供对本发明的更透彻理解。然而,所属领域的一般技术人员将明白本发明可在没有这些特定细节的情况下实践。在其它实例中,尚未详细描述的众所周知的特征以避免不必要地使描述复杂化。
功率MOSFET(金属氧化物半导体场效应晶体管)可在高电流应用(例如,汽车、住宅、工业等等)中用作开关。在许多应用中,可能需要高侧开关与低侧开关两者来控制共同装置,例如发动机或其它类型的制动器。在这些应用中,可通过将两个功率MOSFET及某种控制逻辑封装于单个小形状因子封装中来提供具有成本效益的解决方案。本发明的实施例提供小形状因子封装,其从封装的顶表面及底表面有效地消散由两个功率MOSFET产生的热量,如下文将更详细描述。
图1是示范性功率MOSFET单元100的横截面图。功率MOSFET的一般操作是众所周知的;参见(例如)“功率MOSFET(Power MOSFET)”(2015年12月29日更新的维基百科)。通常使用的配置是垂直扩散MOS(VDMOS)结构(其也被称为双扩散MOS或被简单称为DMOS)。MOSFET单元100说明装置的“垂直性”。源极电极101及N+掺杂源极区域被放置于漏极电极102及N+漏极区域上方,从而在晶体管处于接通状态时产生主要垂直通过主体区域106的电流。通过扩散过程获得P+阱紧接着进行第二扩散以产生N+区域,因此命名为双扩散。
功率MOSFET具有与典型横向MOSFET不同的结构,这是因为其结构通常是垂直的而非平面的。在平面结构中,电流与击穿电压额定值两者都依据沟道尺寸(分别是沟道的宽度及长度)而变化,从而导致硅区域的低效使用。在垂直结构的情况下,晶体管的电压额定值依据N外延层106的掺杂及厚度而变化,而电流额定值依据沟道宽度而变化。这使晶体管有可能在紧凑硅片内承受高阻断电压与高电流两者。
Rn是外延层106的电阻。因为此层的作用是承受阻断电压,所以Rn与装置的电压额定值直接相关。高电压MOSFET需要厚的低掺杂层(即,高电阻性),而低电压晶体管仅需要具有更高掺杂水平的薄层(即,低电阻性)。因此,Rn是负责高电压MOSFET的电阻的主要因素。
图2是可包含大量FET单元100的示范性功率MOSFET装置200的3D视图。可提供接触每一FET单元的源极区域的共同源极接触件201。可提供接触每一FET单元的漏极区域的共同漏极接触件202。栅极接触件203耦合到每一FET单元的栅极。可提供接触每一FET单元的漏极区域的共同漏极接触件202。
当功率装置200正传导电流时,将在每一FET单元的源极区域中及在形成每一FET单元的外延区域206(返回参考图1)的体层206中归因于体电阻Rn而产生热量。热量的很大一部分可移动到背侧漏极区域202,这是因为体Si具有比模制化合物更好的热传导性。
图3到4是包含以允许双侧冷却的方式安装的两个功率装置301、302的示范性封装300的侧视图。功率装置301、302可类似于(例如)功率MOSFET 200。在此实例中,功率MOSFET301安装成其漏极区域耦合到引线框310且其源极区域耦合到单独引线框320。这在本文中被称为“面向上”定向。功率MOSFET 302安装成其漏极区域耦合到引线框320且其源极区域耦合到单独引线框310。这在本文中被称为“面向下”定向。
参考图4,面向上的FET 301将趋于如上文更详细描述那样通过其漏极散热,如由箭头311所指示。因此,耦合到MOSFET 301且接近MOSFET 301的引线框310的区域312可为MOSFET 301提供散热区域312。以类似方式,面向下的FET 302将趋于如上文更详细描述那样通过其漏极散热,如由箭头321所指示。因此,耦合到MOSFET 302且接近MOSFET 302的引线框320的区域322可为MOSFET 302提供散热区域322。以此方式,由MOSFET 301消散的大部分热量可通过封装300的底侧被有效地消散,而由MOSFET 302消散的大部分热量可通过封装300的顶侧被有效地消散。因此,功率模块300被提供有效双侧冷却,其中互锁结构促进热量在两个方向上被消散。
再次参考图3,可通过蚀刻铜片或其它导电材料以形成所期望的引线图案来制造引线框310、320。此外,可执行多个蚀刻步骤以形成多级引线框,其中所选择的部分具有较高轮廓,如314、324处所指示。以此方式,引线框320可被反转且被安装于引线框310的顶部上,且使用(例如)焊膏315进行导电耦合,同时留下其中可放置功率MOSFET301、302且使用焊膏(如316处所指示)进行导电耦合的空腔区域。在组装之后,可加热组合件以使焊膏回流。多个经蚀刻的引线框的制造是众所周知的;例如,参见以引用方式并入的美国公开案2014-0346656,即李韩梦(Lee Han Meng)的“多级引线框(Multilevel Leadframe)”。
图5是图3到4的封装300的俯视图。在此视图中,说明驱动器控制逻辑模块430。驱动器模块430控制MOSFET装置301、302的操作。以此方式,两个功率MOSFET装置301、302及其相关联的控制逻辑430可一起被封装于单个封装300中。在此实例中,封装300是大约5.2×6.0×0.9mm,其比其中两个MOSFET以面向上方式并排安装的现有装置的容量小大约38%。
由点线矩形描画功率消散区域322的轮廓。图6是功率模块300的完整模制的封装的3D视图。应注意,封装模制经控制使得使功率消散区域322被暴露。以类似方式,使功率消散区域312被暴露于封装功率模块300的底侧上。为了使暴露的功率消散区域上方的模具溢料最小化,通过回流过程控制引线框组合件的高度。
图7到9说明用于制造具有双侧冷却的封装的过程。图7说明被形成701到顶侧引线框320中的铜带的部分,再次参考图3。类似地,形成702底侧引线框310。通常,多个引线框将同时形成于导电材料片或带上。虽然通常将铜片用于引线框,但也可使用其它类型的导电材料或铜合金;举例来说,Cu-Sn、Cu-Fe-P、Cu-Cr-Sn-Zn等等。可基于导电性、抗张强度、热膨胀率等等选择各种合金以用于特定应用。
将第一蚀刻掩模施加到导电片上,所述第一蚀刻掩模将用于在所述片上形成第一蚀刻图案。所述掩模可使用已知的施加技术形成于所述片上。举例来说,可将光敏掩模材料施加于所述片且使其暴露于穿过含有待蚀刻的图案的图像的光罩的光。接着,可使用合适的溶剂清洗掉未曝光的区域。替代地,可使用丝网印刷过程或其它已知或稍后待开发的施加过程施加所述掩模。一旦第一掩模就位,就使用合适的蚀刻剂蚀刻掉被暴露的铜片区域。允许蚀刻过程前进到小于所述片的厚度某一深度以便形成各种平台,其在本文还被称为图3中所说明的“突出接触区域”。接着,可执行第二及/或第三掩模及蚀刻序列以完成引线框。
接着,可将焊膏施加703于顶侧引线框320并将其施加704于底侧引线框310。举例来说,在底侧引线框上:焊膏740耦合到MOSFET 301的漏极侧;焊膏741耦合到MOSFET 302的源极接触件,焊膏742耦合到驱动器模块430,且焊膏743耦合底侧引线框310上的上升平台以匹配顶侧引线框320上的上升平台。各种焊膏图案可以类似方式施加于顶侧引线框320。接着,可在裸片附接过程705期间将面向下的MOSFET 302放置于顶侧引线框320上的焊膏中,通常通过机械拾取和放置机器。类似地,可在另一裸片附接过程706中将面向上的MOSFET 301放置于底侧引线框310上的焊膏中。可将额外焊膏放置于MOSFET 301的源极接触件上方以协助耦合到顶侧引线框320。类似地,可将额外焊膏放置于MOSFET 302的源极接触件上方以协助耦合到底侧引线框310。
接着,将顶侧引线框反转并将其叠加于底侧引线框上方以形成组合件。图8说明展示装置300的6×3矩阵的引线框带的部分。
图9是包含上述步骤的流程图。在叠加708引线框之后,接着,可将驱动器IC 430放置910于焊膏742上,返回参考图7。在加热以回流焊膏之后,可执行线接合912以将驱动器IC430连接到底侧引线框310上的垫。
接着,可执行模制过程914。如关于图6所论述,引线框组合件及模制过程经控制使得热支出区域312、322保持被暴露以改进热传递。
接着,可通过使模制引线框组合件单一化916来生产个别封装。在此实例中,可通过锯切轮廓850来执行单一化916,返回参考图8。
在此实例中,单一化装置是QFN(四方扁平无引线)封装。例如四方扁平无引线(QFN)及双扁平无引线(DFN)的扁平无引线封装将集成电路物理且电连接到印刷电路板。扁平无引线,也被称为微引线框(MLF)及SON(小轮廓无引线),是一种表面安装技术,其是在无需穿孔的情况下将IC连接到PCB的表面的若干封装技术中的一者。扁平无引线是使用平面铜引线衬底制成的准芯片级封装塑料囊封封装。封装底部上的周边凸面提供与PCB的电连接。QFN封装类似于四方扁平封装及球栅阵列。
图10是具有双侧冷却的封装1000的另一实施例的侧视图。在此实例中,选项散热器1060可被附接到封装1000的顶侧热支出区域320以进一步协助散热。图10还说明位于其上安装有封装1000的衬底中的热传导层1062。封装1000的底侧上的热支出310区域可耦合到热传导层1062以协助散热。在此实例中,衬底可为印刷电路板(PCB)。此衬底的范围可在(例如)集成电路(IC)裸片、多芯片封装中的衬底、其上安装有若干IC的印刷电路板(PCB)等等内变动。衬底可为任何常用的或后来开发的用于电子系统及封装的材料,例如(举例来说):硅、陶瓷、树脂玻璃、光纤玻璃、塑料、金属等等。
其它实施例
虽然已参考说明性实施例描述本发明,但本描述内容不希望以限制意义来理解。所属领域的技术人员在参考本说明书之后将明白本发明的各种其它实施例。举例来说,除QFN外的其它封装类型可形成有双侧冷却,例如四方扁平封装、球栅阵列等等。
在另一实施例中,可通过冲压过程形成引线框,其中通过使引线框的部分弯曲来形成突出接触区域。
贯穿本说明书及权利要求书使用某些术语以指代特定系统组件。如所属领域的技术人员应了解,数字系统中的组件可由不同名称指代且所述组件可以本文未展示的方式被组合而不背离所描述的功能性。此文件不希望区分在名称上不同但在功能上相同的组件。在以下论述及权利要求书中,以开放式方式使用术语“包含”及“包括”,且因此,所述术语应被解译为意味着“包含,但不限于”。此外,术语“耦合”及其派生物希望意味着间接、直接、光学及/或无线电连接。因此,如果第一装置耦合到第二装置,那么那个连接可为通过直接电连接、通过经由其它装置及连接的间接电连接、通过光学电连接及/或通过无线电连接。
尽管本文可以顺序方式呈现并描述方法步骤,但可省略、重复、同时执行及/或以与图式中所展示及/或本文所描述的顺序不同的顺序执行所展示及所描述的步骤中的一或多者。因此,本发明的实施例不应被认为是限于图式中所展示及/或本文所描述的步骤的特定排序。
因此,应预期,所附权利要求书将覆盖如落于本发明的真正范围及精神内的实施例的任何此类修改。
Claims (21)
1.一种用于制造多芯片封装的方法,所述方法包括:
通过蚀刻导电材料片材制造具有散热区域的上引线框及具有散热区域的下引线框;
将第一芯片的第一侧附接到所述下引线框的所述散热区域;
将第二芯片的第一侧附接到所述上引线框的所述散热区域;
将所述上引线框叠加于所述下引线框上方,使得所述第一芯片的第二侧被附接到所述上引线框的所述散热区域且所述第二芯片的第二侧被附接到所述下引线框的所述散热区域以形成组合件;及
使用模制化合物囊封所述组合件,使得所述上引线框的所述散热区域的表面及所述下引线框的所述散热区域的表面被暴露。
2.根据权利要求1所述的用于制造多芯片封装的方法,其进一步包含使用模制材料囊封所述第一半导体装置及所述第二半导体装置,使得所述第一引线框的所述散热区域的所述散热表面的所述表面及所述第二引线框的所述散热区域的所述表面保持被暴露。
3.根据权利要求2所述的用于制造多芯片封装的方法,其进一步包含通过所述第一引线框及所述第二引线框将第三半导体装置互连到所述第一半导体装置及所述第二半导体装置,且使用所述模制材料囊封所述第三半导体装置。
4.根据权利要求2或3所述的用于制造多芯片封装的方法,其进一步包含将散热器连接到所述第二引线框的所述散热区域。
5.根据权利要求2或3所述的用于制造多芯片封装的方法,其进一步包含附接到所述第一引线框的所述散热区域的衬底。
6.根据权利要求4所述的用于制造多芯片封装的方法,其进一步包含附接到所述第一引线框的所述散热区域的衬底。
7.根据权利要求5或6所述的用于制造多芯片封装的方法,其中所述衬底为印刷电路板。
8.一种制造多芯片封装的方法,所述方法包括:
将第一半导体装置安装于第一引线框上,其中所述第一半导体装置的主要产热表面朝向所述第一引线框的散热区域定向且接触所述第一引线框的所述散热区域;
将第二半导体装置安装于第二引线框上,其中所述第二半导体装置的主要产热表面朝向所述第二引线框的散热区域定向且接触所述第二引线框的所述散热区域;
其中所述第一引线框是与突出接触区域共面的经蚀刻的引线框,且所述第二引线框是与接触所述第一引线框上的对应突出接触区域的突出接触区域共面的经蚀刻的引线框;且
其中所述第一引线框的所述散热区域的表面被暴露于所述多芯片封装的第一侧上,且所述第二引线框的所述散热区域的表面被暴露于所述多芯片封装的与所述第一侧相对的第二侧上。
9.根据权利要求8所述的制造多芯片封装的方法,其进一步包含使用模制材料囊封所述第一半导体装置及所述第二半导体装置,使得所述第一引线框的所述散热区域的所述散热表面的所述表面及所述第二引线框的所述散热区域的所述表面保持被暴露。
10.根据权利要求9所述的制造多芯片封装的方法,其进一步包含通过所述第一引线框及所述第二引线框将第三半导体装置互连到所述第一半导体装置及所述第二半导体装置,且使用所述模制材料囊封所述第三半导体装置。
11.根据权利要求9或10所述的制造多芯片封装的方法,其进一步包含将散热器连接到所述第二引线框的所述散热区域。
12.根据权利要求9、10或11所述的制造多芯片封装的方法,其进一步包含附接到所述第一引线框的所述散热区域的衬底。
13.根据权利要求12所述的制造多芯片封装的方法,其中所述衬底为印刷电路板。
14.一种用于制造多芯片封装的方法,所述方法包括:
将第一半导体装置安装于第一引线框上,其中所述第一半导体装置的漏极区域朝向所述第一引线框的散热区域定向且接触所述第一引线框的所述散热区域,且所述第一半导体装置的源极区域朝向第二引线框定向且接触所述第二引线框;
将第二半导体装置安装于第二引线框上,其中所述第二半导体装置的漏极区域朝向所述第二引线框的散热区域定向且接触所述第二引线框的所述散热区域且其中所述第二半导体装置的源极区域朝向所述第一引线框定向且接触所述第一引线框;以及
其中所述第一引线框的所述散热区域的表面被暴露于所述多芯片封装的第一侧上,且所述第二引线框的所述散热区域的表面被暴露于所述多芯片封装的与所述第一侧相对的第二侧上。
15.根据权利要求14所述的制造多芯片封装的方法,其中所述第一引线框是与突出接触区域共面的经刻蚀的引线框,且所述第二引线框是与接触所述第一引线框上的对应突出接触区域的突出接触区域共面的经刻蚀的引线框。
16.根据权利要求14所述的制造多芯片封装的方法,其中所述第一引线框是与突出接触区域共面的经冲压的引线框,且所述第二引线框是与接触所述第一引线框上的对应突出接触区域的突出接触区域共面的经冲压的引线框。
17.根据权利要求14所述的制造多芯片封装的方法,其进一步包含用模制材料囊封所述第一半导体装置及所述第二半导体装置,使得所述第一引线框的所述散热区域的所述散热表面的所述表面及所述第二引线框的所述散热区域的所述表面保持被暴露。
18.根据权利要求14所述的制造多芯片封装的方法,其进一步包含通过所述第一引线框及所述第二引线框将第三半导体装置互连到所述第一半导体装置及所述第二半导体装置。
19.根据权利要求14所述的制造多芯片封装的方法,其中所述第一半导体装置及所述第二半导体装置两者都是垂直功率MOSFET(金属氧化物半导体场效应晶体管)装置。
20.根据权利要求17所述的制造多芯片封装的方法,其进一步包含附接到所述第一引线框的所述散热区域的衬底。
21.根据权利要求20所述的制造多芯片封装的方法,其中所述衬底为印刷电路板。
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