CN111987050A - 具有节省空间的引线和管芯焊盘设计的半导体封装 - Google Patents
具有节省空间的引线和管芯焊盘设计的半导体封装 Download PDFInfo
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- CN111987050A CN111987050A CN202010439767.XA CN202010439767A CN111987050A CN 111987050 A CN111987050 A CN 111987050A CN 202010439767 A CN202010439767 A CN 202010439767A CN 111987050 A CN111987050 A CN 111987050A
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Abstract
本发明公开了一种半导体封装,其包括:管芯焊盘,所述管芯焊盘具有管芯附接表面、与管芯附接表面相对的后表面、以及在管芯附接表面与后表面之间延伸的外部边缘侧,所述外部边缘侧具有阶梯形轮廓,其中,管芯焊盘的上部区段横向悬垂超过管芯焊盘的下部区段;半导体管芯,所述半导体管芯安装在管芯附接表面上,并且具有处于半导体管芯的上表面上的第一电端子;和第一导电夹,所述第一导电夹直接电接触第一电端子,并且环绕管芯焊盘的外部边缘侧,使得第一导电夹的区段至少部分地位处于这样的区域内,所述区域直接处于管芯焊盘的上部区段下方,并且直接横向邻近下部区段。
Description
技术领域
本发明的实施例总体上涉及半导体封装,并且更具体地涉及用于半导体封装的互连构造。
背景技术
半导体封装被设计成提供半导体管芯与诸如印刷电路板(PCB)的外部装置之间的连接兼容性,并且保护半导体管芯免受诸如极端温度、湿度、灰尘颗粒等的潜在的破坏性环境条件的影响。存在各种不同的半导体封装类型,以满足不同的应用要求。一般而言,基于封装引线和/或包封主体的构造来区分半导体封装类型。不同的半导体封装类型的示例包括所谓的通孔封装(例如,双列直插式封装(DIP))、表面安装封装(例如,柱栅阵列(CGA)封装)、扁平封装(例如,超薄四方扁平无引线(VQFN)封装)等。
半导体封装中的一个普遍的设计目标是使封装尺寸与芯片的比率最大化,所述比率是包封物主体的横向覆盖区与半导体管芯的横向覆盖区的比率。使该比率最大化可以提供重要的性能优势。例如,在功率开关应用中,其中,半导体管芯被设计为阻挡非常大的电压(例如200伏或更大),期望半导体管芯尽可能的大以减小导通电阻(例如,RDSON)。对于给定的封装覆盖区,更大的封装尺寸与芯片的比率容纳更大的半导体管芯。
各种设计考虑因素对可行的封装尺寸与芯片的比率设置了上限。例如,包括管芯垫和多个引线的所谓的引线框架型封装限制了可以将半导体管芯提供到模制化合物主体的边缘的紧密程度。一般而言,难以实现大于0.5的封装尺寸与芯片的比率。
发明内容
公开了一种半导体封装。根据实施例,所述半导体封装包括:管芯焊盘,所述管芯焊盘包括管芯附接表面、与管芯附接表面相对的后表面以及在管芯附接表面与后表面之间延伸的外部边缘侧,所述外部边缘侧具有阶梯形轮廓,其中,管芯焊盘的上部区段横向悬垂超过管芯焊盘的下部区段;半导体管芯,所述半导体管芯安装在管芯附接表面上,并且包括在半导体管芯的背离管芯附接表面的上表面上的第一电端子;以及第一导电夹,所述第一导电夹直接电接触第一电端子,并且环绕管芯焊盘的外部边缘侧,使得第一导电夹的区段至少部分地处于这样的区域内,所述区域直接处于管芯焊盘的上部区段下方,并且直接横向邻近下部区段。
单独地或组合地,半导体封装包括包封半导体管芯的电绝缘的包封物,其中,包封物包括在半导体管芯之上延伸的顶表面、与顶表面相对的底表面,并且其中,第一导电夹的最下表面在包封物的底表面的平面处或上方。
单独地或组合地,第一导电夹的最下表面是在第一导电夹中的成角度的弯曲部与第一导电夹的外部端部之间延伸的接触表面,其中,接触表面和管芯焊盘的后表面基本上彼此共面,并且其中,接触表面和管芯焊盘的后表面从包封物暴露。
单独地或组合地,包封物的底表面与接触表面和管芯焊盘的后表面基本上共面。
单独地或组合地,半导体管芯安装在管芯焊盘上,使得半导体管芯横向悬垂超过管芯焊盘的下部区段,并且其中,第一导电夹的外部端部直接设置在半导体管芯下方。
单独地或组合地,半导体封装包括中间层,中间层设置在半导体管芯的下表面与管芯附接表面之间,其中,中间层横向悬垂超过管芯焊盘的下部区段,并且其中,第一导电夹的外部端部直接设置在中间层下方。
单独地或组合地,半导体封装还包括与管芯焊盘间隔开的导电引线,其中,半导体管芯还包括第二电端子和第三电端子,第二电端子和第三电端子设置在半导体管芯的与半导体管芯的上表面相对的下表面上,其中,第二电端子直接电接触管芯附接表面,并且其中,第三电端子直接电接触引线的上表面。
单独地或组合地,半导体管芯还包括设置在半导体管芯的上表面处的第二电端子,并且其中,半导体封装还包括第二导电夹,所述第二导电夹直接电接触第二电端子,并且环绕管芯焊盘的外部边缘侧,使得第二导电夹的外部端部至少部分地处于这样的区域内,所述区域直接处于管芯焊盘的上部区段下方,并且直接横向邻近下部区段。
单独地或组合地,第一导电夹包括中心焊盘和细长的指状部,其中,中心焊盘直接设置在第一电端子之上,其中,细长的指状部比中心焊盘窄,其中,细长的指状部与中心焊盘连接,并且伸出到包封物外,并且其中,细长的指状部的从包封物暴露的部分环绕管芯焊盘的外部边缘侧,并且延伸到第一导电夹的外部端部。
单独地或组合地,包封物完全覆盖中心焊盘。
单独地或组合地,中心焊盘延伸到包封物的顶表面,并且包括从包封物暴露的上表面。
单独地或组合地,中心焊盘的厚度大于细长的指状部的厚度,中心焊盘的厚度是在中心焊盘的上表面与中心焊盘的面对第一电端子的下表面之间测量的,细长的指状部的厚度是在与中心焊盘连接的细长的指状部的相对面对的上表面与下表面之间测量的。
单独地或组合地,第一导电夹包括多个细长的指状部,其中,每个所述细长的指状部彼此间隔开,并且与中心焊盘的同一侧相交。
公开了一种封装半导体器件的方法。根据实施例,所述方法包括:提供管芯焊盘,所述管芯焊盘包括管芯附接表面、与管芯附接表面相对的后表面以及在管芯附接表面与后表面之间延伸的外部边缘侧,外部边缘侧具有阶梯形轮廓,其中,管芯焊盘的上部区段横向悬垂超过管芯焊盘的下部区段;将半导体管芯安装在管芯附接表面上,使得半导体管芯的上表面上的第一电端子背离管芯附接表面;以及提供第一导电夹,所述第一导电夹直接电接触第一电端子,并且环绕管芯焊盘的外部边缘侧,使得第一导电夹的外部端部至少部分地处于这样的区域内,所述区域直接处于管芯焊盘的上部区段下方,并且直接横向邻近下部区段。
单独地或组合地,所述方法还包括形成包封半导体管芯的电绝缘的包封物,其中,包封物被形成为包括在半导体管芯之上延伸的顶表面、与顶表面相对的底表面,并且其中,第一导电夹的最下表面在包封物的底表面的平面处或上方。
单独地或组合地,提供第一导电夹包括:提供电接触第一端子的导电金属的平面条状物(planar strip);在提供导电金属的平面条状物之后形成包封物,使得平面条状物的暴露部分伸出到包封物外;以及弯曲平面条状物的暴露部分,使得暴露部分环绕管芯焊盘的外部边缘侧,使得第一导电夹的外部端部至少部分地处于这样的区域内,所述区域直接处于管芯焊盘的上部区段下方,并且直接横向邻近下部区段。
附图说明
附图的元素不必相对于彼此成比例。相似的附图标记表示对应的类似的部分。除非它们彼此排斥,否则可以组合各种所示的实施例的特征。在附图中描绘了实施例,并且在下面的说明书中详细描述了实施例。
包括图1A、图1B、图1C和图1D的图1描绘了根据实施例的半导体封装。图1A是具有示意性地描绘为半透明的包封物材料的半导体封装的顶侧的平面图。图1B是半导体封装的底侧的平面图。图1C是沿着图1A中所示的截面平面A-A’的半导体封装的截面图。图1D是沿着图1A中所示的截面平面B-B’的半导体封装的截面图。
图2示出了根据另一个实施例的沿着与图1A中所示的截面平面A-A’相对应的截面平面的半导体封装的截面图。
图3示出了根据另一个实施例的沿着与图1A中所示的截面平面A-A’相对应的截面平面的半导体封装的截面图。
图4示出了根据另一个实施例的沿着与图1A中所示的截面平面A-A’相对应的截面平面的半导体封装的截面图。
图5示出了根据另一个实施例的沿着与图1A中所示的截面平面A-A’相对应的截面平面的半导体封装的截面图。
包括图6A、图6B、图6C、图6D和图6E的图6描绘了根据另一个实施例的半导体封装。图6A是具有示意性地描绘为半透明的包封物材料的半导体封装的顶侧的平面图。图6B是半导体封装的底侧的平面图。图6C是半导体封装的侧视图。图6D是沿着图6A中所示的截面平面C-C’的半导体封装的截面图。图6E是沿着图6A中所示的截面平面D-D’的半导体封装的截面图。
具体实施方式
根据本文描述的实施例的半导体封装包括管芯焊盘和夹构造,所述管芯焊盘和夹构造产生了有利的高的封装尺寸与芯片的比率。半导体封装包括双规格的管芯焊盘,其中,管芯焊盘的上部区段横向悬垂超过管芯焊盘的下部区段。因此,管芯焊盘的边缘侧是阶梯形的,并且具有从管芯焊盘的后表面延伸的沟槽。半导体封装包括导电夹,所述导电夹与安装在管芯焊盘上的半导体管芯的电端子形成直接的电连接。导电夹环绕管芯焊盘,使得导电夹的端部部分横向延伸到管芯焊盘的沟槽中。导电夹的下表面为半导体管芯提供外部电接触点。通过使用管芯焊盘的沟槽区来容纳导电夹的端部,改进了空间效率。因为导电夹消除了对与管芯焊盘横向间隔开的单独的引线的需要,所以管芯焊盘和/或安装在其上的特征可以被设置为非常靠近包封物材料的边缘侧。这使得封装尺寸与芯片的比率大于0.5,包括例如高于0.6、0.7、0.8等的比率。此外,导电夹的在管芯焊盘底下的环绕构造使封装的横向覆盖区最小化。
参考图1,描绘了根据实施例的半导体封装100。半导体封装100包括管芯焊盘102。管芯焊盘102包括管芯附接表面104、与管芯附接表面104相对的后表面106、以及在管芯附接表面104与后表面106之间延伸的外部边缘侧108。管芯附接表面104和/或后表面106可以是基本上平面的表面。此外,这些表面可以基本上彼此平行。管芯焊盘102可以是导热和导电的结构。用于管芯焊盘102的示例性材料包括诸如铜、铝、镍、铁、锌等的金属及其合金。
根据实施例,管芯焊盘102的外部边缘侧108具有阶梯形轮廓110,其中,管芯焊盘102的上部区段112横向悬垂超过管芯焊盘102的下部区段114。结果,管芯焊盘102包括在外部边缘侧108处从后表面106延伸的沟槽。该构造可以被称为“双规格”的构造,其中,管芯焊盘102的上部区段112具有比下部区段114更大的厚度。可以使用所谓的半蚀刻技术来获得该构造。根据该技术,管芯焊盘102由导电材料的基本上均匀厚度的部分(例如,金属片)形成。该均匀厚度的部分被掩盖,并且在两侧上蚀刻穿过大约一半。结果,在两侧上从掩模暴露的区被完全去除,而仅在一侧上暴露的区被部分去除,即“半蚀刻”。在外部边缘侧108处从后表面106延伸的沟槽可以是半蚀刻特征。更一般地,可以使用诸如冲压、蚀刻、冲孔等的各种技术来获得阶梯形轮廓110。
半导体管芯116安装在管芯焊盘102的管芯附接表面104上。一般而言,半导体管芯116可以具有各种各样的器件构造,例如MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极型晶体管)、JFET(结型场效应晶体管)、二极管等。半导体管芯116可以包括各种各样的半导体材料中的任何一种,所述半导体材料包括IV型半导体(例如硅(Si)、硅锗(SiGe)、碳化硅(SiC)等)和III-V型半导体(例如氮化镓(GaN)、砷化镓(GaAs)等)。半导体管芯116可以被配置为:垂直器件,所述垂直器件被配置为控制在相对面对的上表面和下表面之间流动的电流;或横向器件,所述横向器件被配置为控制平行于主表面流动的电流。
在所描绘的实施例中,半导体管芯116包括第一、第二和第三电端子118、120、122。第一和第二电端子118、120设置在半导体管芯116的背离管芯附接表面104的上表面上。第三电端子122设置在半导体管芯116的面对管芯附接表面104的下表面上。第三电端子122可以直接电连接到管芯附接表面104,使得管芯焊盘102充当用于半导体封装100的外部端子。可以在两个表面之间提供诸如烧结物、焊料等的导电的中间物(未在图1中示出)以实现该连接。
根据实施例,半导体管芯116被配置为MOSFET,其中,第一电端子118是源极焊盘,第二电端子120是栅极焊盘,并且第三电端子122是漏极焊盘。根据另一个实施例,半导体被配置为IGBT,其中,第一电端子118是集电极焊盘,第二电端子120是栅极焊盘,并且第三电端子122是发射极焊盘。根据另一个实施例,半导体被配置为二极管,其中,第一电端子118是正极,第二电端子120是正极,并且第三电端子122被省略。更一般地,半导体管芯116可以包括具有设置在半导体管芯的一侧或两侧上的电端子的各种各样的器件构造。
半导体封装100包括包封物124。包封物124包括在半导体管芯116之上延伸的顶表面126、与顶表面126相对的底表面128、以及在顶表面和底表面126、128之间延伸的外部边缘表面130。包封物124包括电绝缘材料,例如陶瓷、环氧树脂材料、热固性塑料、热塑性塑料等。包封物124可以根据各种技术形成,例如注射模制、压缩模制、传递模制等。包封物124被形成以包封(即,包围和围绕)半导体管芯116以及与半导体管芯116的电端子相关联的电连接。
半导体封装100包括第一导电夹132。第一导电夹132是导电的和(可选地)导热的结构。第一导电夹132由诸如铜、铝、镍、金、银等的导电金属及其合金形成。第一导电夹132可以是单片式地形成的特征。例如,第一导电夹132可以由(例如)通过冲压、蚀刻、弯曲等处理的单个平面金属片提供,以形成本文公开的特征。替代地,第一导电夹132可以通过使用例如焊接、熔接、铆接等的已知技术将多个分立的导电结构连接在一起来形成。在实施例中,分别地提供第一导电夹132与引线框架结构,所述引线框架结构提供用于半导体封装100的管芯焊盘102和任何引线,并且作为引线框架结构具有不同的材料特性,例如厚度、材料组成等。
第一导电夹132电连接到第一电端子118。为此,第一导电夹132包括直接电接触第一电端子118的中心焊盘134。中心焊盘134直接设置在第一电端子118之上,并且被包含在包封物124的外部边缘表面130内。如图所示,中心焊盘134的部分直接在第一电端子118之上,并且部分横向悬垂超过第一电端子。可选地,中心焊盘134可以在每个方向上横向悬垂超过半导体管芯116,并且中心焊盘134的中心部分直接设置在第一电端子118之上。中心焊盘134和第一电端子118之间的电连接可以通过直接的表面对表面接触或通过导电的中间物(例如焊料、烧结物、粘合带等)来实现。
第一导电夹132包括环绕管芯焊盘102的外部边缘侧108的部分。这意味着第一导电夹132的部分从管芯附接表面104的上方横向延伸超过管芯焊盘102的最外横向侧(在所描绘的示例中是上部区段112中的外部边缘侧108),然后垂直向下延伸超过管芯附接表面104,并且然后再次横向延伸超过管芯焊盘102的最外横向侧。结果,第一导电夹132包括直接设置在管芯附接表面104上方的区段和直接设置在管芯附接表面104下方的区段。
根据实施例,第一导电夹132环绕管芯焊盘102的外部边缘侧108,使得第一导电夹132的区段至少部分地在区域136内,区域136直接处于管芯焊盘102的上部区段112下方,并且直接横向邻近管芯焊盘102的下部区段114。这意味着第一导电夹132进入区域136,区域136垂直处于管芯焊盘102的上部区段112与平行于后表面106的平面之间,并且横向处于管芯焊盘102的下部区段114中的外部边缘侧108与相切于上部区段112中的外部边缘侧108的平面之间。换句话说,第一导电夹132进入形成在管芯焊盘102的后表面106中的沟槽。在本开的意义内,如果第一导电夹132的任何部分越过区域136的边界,则第一导电夹132“至少部分地”在区域136内。根据所描绘的实施例,第一导电夹132被配置为使得延伸到第一导电夹132的外部端部138的横向段完全在该区域136内。因此,第一导电夹132的外部端部138完全在管芯焊盘102的后表面106中的沟槽内。
第一导电夹132包括接触表面140,所述接触表面140从包封物124暴露,并且为第一电端子118提供外部的电接触点。该接触表面140可以是第一导电夹132的最下表面,即,第一导电夹132的处于管芯附接表面104下方并且垂直最远离管芯附接表面104的表面。根据实施例,接触表面140是从第一导电夹132中的成角度的弯曲部横向延伸到第一导电夹132的外部端部138的基本上平面的表面。根据实施例,接触表面140设置在包封物124的底表面128的平面处或上方(即,更靠近管芯附接表面104)。根据所描绘的实施例,第一导电夹132的接触表面140、管芯焊盘102的后表面106和包封物124的底表面128均彼此共面。因此,半导体封装100可以被安装在具有提供表面安装连接性的管芯焊盘102和第一导电夹132的平面的托座上。在其他实施例中,第一导电夹132的最下表面和/或管芯焊盘102可以从包封物124的底表面128垂直偏移。
根据实施例,第一导电夹132包括细长的指状部142,细长的指状部142与中心焊盘134连接,并且伸出到包封物124外。该细长的指状部142以上述的方式环绕管芯焊盘102的外部边缘侧108。细长的指状部142比中心焊盘134窄,其中,这些元件的宽度是在相对面对的外部边缘侧之间测量的。
在所描绘的实施例中,细长的指状部142具有锐角构造,所述锐角构造具有基本上平行于包封物124的外部边缘表面130的垂直部分,和将垂直部分连接到延伸超过管芯焊盘102的外部边缘侧108的横向部分的基本上正交的成角度的弯曲部。更一般地,第一导电夹132可以包括曲面和/或一个或多个倾斜角,以实现如本文所述的环绕构造。
根据实施例,第一导电夹132包括多个(即,两个或更多个)细长的指状部142。这些细长的指状部142中的每一个可以在不同的位置处连接到中心焊盘134的同一侧,并且具有等同的如上所述的环绕构造。这些细长的指状部142可以例如以规则的分隔距离彼此间隔开。尽管所描绘的第一导电夹132包括四个细长的指状部142,均具有基本上均匀的宽度和规则的间隔,但是细长的指状部142的数量、尺寸、间隔等可以适合于满足诸如封装尺寸、电流承载能力等的各种设计考虑因素。
如所描绘的实施例中所示,包封物124被形成为使得第一导电夹132的延伸到外部端部138的部分与包封物124间隔开。在另一个实施例中,包封物124完全延伸,以至少覆盖半导体封装100的第一导电夹132的上表面的该拐角部分。
根据实施例,第一导电夹132最初被提供为导电金属的平面条状物。该平面条状物可以被结构化,以包括中心焊盘134和远离中心焊盘134延伸的平面的细长条状物的形状。在包封之前安装该平面条状物,以电接触第一导电端子118。然后可以例如以上述方式形成包封物124。在包封之后,平面条状物的暴露部分伸出到包封物124外。然后,形成该暴露部分,以环绕管芯焊盘102的外部边缘侧108,例如,如以上关于第一导电指状部142所描述的。这可以通过弯曲暴露的金属来完成。
根据实施例,半导体封装100包括第二导电夹144,例如,如图1D所示。第二导电夹144直接电接触第二电端子120,并且环绕管芯焊盘102的外部边缘侧108,使得第二导电夹144的外部端部146至少部分在区域136内,区域136直接处于管芯焊盘102的上部区段112下方,并且直接横向邻近管芯焊盘102的下部区段114。因此,第二导电夹144相应地被配置为以如先前所述的类似方式来为第二电端子120提供电接触点。在描述的实施例中,第二导电夹144从端部到端部具有均匀的宽度,所述宽度基本上等同于第一导电夹132的细长的指状部142中的一个的宽度。该宽度可以适合于承载较低的电流信号,例如在MOSFET的情况下的栅极信号。更一般地,根据上述的第一导电夹132的任何变化,第二导电夹144的几何结构可以包括多个细长的指状部,并且第一和第二导电夹132、144可以共同地被修改,以提供适当的电流承载能力。
参考图2,描绘了根据另一个实施例的半导体封装100。除了以下方式之外,图2的半导体封装100等同于图1的半导体封装100。在该实施例中,半导体管芯116安装在管芯焊盘102上,使得半导体管芯116横向悬垂超过管芯焊盘102的下部区段。换句话说,半导体管芯116横向设置为足够靠近管芯焊盘102的外部边缘侧108,使得半导体管芯116直接处于后表面106中的沟槽上方。此外,第一导电夹132的外部端部138直接设置在半导体管芯116下方。由于半导体管芯116横向延伸得非常靠近包封物124的外部边缘表面130,因此该构造使高的封装尺寸与芯片的比率成为可能。同时,由于管芯焊盘102的阶梯形的外部边缘侧108,因此第一导电夹132的接触表面140足够大以用于可靠的和低电阻的电连接。
参考图3,描绘了根据另一个实施例的半导体封装100。除了以下方式之外,图3的半导体封装100等同于图1的半导体封装100。在该实施例中,半导体封装件100包括中间层148,中间层148设置在半导体管芯116的下表面与管芯焊盘102的管芯附接表面104之间。中间层148横向悬垂超过管芯焊盘102的下部区段114。换句话说,中间层148横向设置为足够靠近管芯焊盘102的外部边缘侧108,使得半导体管芯116直接处于后表面106中的沟槽上方。在该实施例中,第一导电夹132的外部端部138直接设置在中间层148下方。
根据实施例,中间层148是在第三电端子122与管芯附接表面104之间提供导电连接的导电层。为此,中间层148可以包括以下各项中的一个或多个:烧结物、焊料、导电带(例如,管芯附接膜)、金属板(例如,DCB铜板)等。替代地,中间层148可以包括电绝缘材料,例如陶瓷、电介质、带等。
参考图4,描绘了根据另一个实施例的半导体封装100。除了以下方式之外,图4的半导体封装100等同于图1的半导体封装100。在该实施例中,第一导电夹132在包封物124的顶表面126处暴露。更具体地,第一导电夹132的包括细长的指状部142的上部部分和中心焊盘134的部分在顶表面126处暴露。第一导电夹132的该部分包括第一导电夹132的最上表面,即,第一导电夹132的在管芯附接表面104上方并且垂直最远离管芯附接表面104的表面。根据实施例,第一导电夹132的最上表面与包封物124的顶表面126基本上共面。
图4的该构造对于增强的散热能力可能是期望的,特别是如果第一电端子118在操作期间生成大量的热量时。第一导电夹132的暴露的上表面可以与外部散热器界面接合,以有效地从器件去除热量。
参考图5,描绘了根据另一个实施例的半导体封装100。除了以下方式之外,图5的半导体封装100等同于图1的半导体封装100。在该实施例中,第一导电夹132在包封物124的顶表面126处暴露。然而,与先前讨论的图4的实施例不同,图5的实施例包括具有不同厚度的区的第一导电夹132。更具体地,中心焊盘134的厚度T1大于细长的指状部142的厚度T2。中心焊盘134的厚度是在中心焊盘134的上表面与中心焊盘134的面对第一电端子118的下表面之间测量的。细长的指状部142的厚度是在与中心焊盘134连接的细长的指状部142的相对面对的上表面与下表面之间测量的。在一个示例中,中心焊盘134的厚度T1约是细长的指状部142的厚度T2的两倍。
与图4的实施例相比,因为较大尺寸的中心焊盘134提供有效的热传递,所以图5的构造对于增强的散热能力可能是期望的。此外,该实施例更容易允许其中第二导电夹144与包封物124的顶表面126绝缘的构造。例如,在该实施例中,第二导电夹144可以具有单规格的构造,并且设置在包封物124的顶表面126下方。结果,一个端子在包封物124的顶表面126处是电可触及的,然而另一个端子则不是。参考图6,描绘了根据另一个实施例的半导体封装100。除了以下方式之外,图6的半导体封装100等同于图1的半导体封装100。在该实施例中,半导体管芯116具有所谓的倒装芯片构造。根据该构造,半导体管芯116安装在载体上,半导体管芯116具有直接面对并且电连接到载体的多个I/O端子。在所描绘的实施例中,半导体管芯116被布置为仅具有设置在半导体管芯116的背离管芯焊盘102的上表面上的第一电端子218,并且具有设置在半导体管芯116的面对管芯焊盘102的下表面上的第二和第三电端子220、222。在该实施例中,第一导电夹132直接电连接到第一电端子218,并且以与先前描述类似的方式来环绕管芯焊盘102。同样地,管芯焊盘102以与先前描述类似的方式直接电连接到第二电端子220。半导体封装100包括允许外部电触及第三电端子222的导电的引线202。引线202与管芯焊盘102间隔开。如图所示,半导体管芯116被安装为使得第二电端子220面对并且直接电接触管芯附接表面104,并且第三电端子222面对并且电接触引线202的上表面。例如,根据已知技术,管芯焊盘102和引线202可以被提供为引线框架结构的部分。
上述实施例中的每一个包括:双规格的管芯焊盘102,即管芯焊盘102在一个外部边缘侧108具有阶梯形过渡;以及第一导电夹132,第一导电夹132以节省空间的方式利用管芯焊盘102的该特征作为用于第一导电夹132的端部的托座。在另一个实施例中,半导体封装100可以被配置为使得半导体管芯116(例如,以与上部区段112类似的方式)横向悬垂超过管芯焊盘102的边缘侧108(可以是或可以不是阶梯形的),并且第一导电夹132在半导体管芯116的悬垂部分底下延伸。这提供了类似的节省空间的优势。
如在本文中使用的术语“基本上”涵盖具有特定要求的绝对一致性,以及由于诸如制造工艺变化、组装和可能引起偏离目标设计目的的其他因素的因素与具有所述要求的绝对一致性的微小偏差。如果偏差在工艺公差内以便实现实际的一致性,并且本文所述的部件能够根据应用要求起作用,则术语“基本上”涵盖这些偏差中的任何一个。
如本文中所使用的术语“电连接”、“直接电连接”等描述了电连接的元件之间的永久性低阻抗连接,例如相关的元件之间的直接接触或经由金属和/或高掺杂的半导体的低阻抗连接。
为了便于描述,使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等空间相对的术语来解释一个元件相对于第二元件的位置。这些术语旨在涵盖除了与附图中描绘的器件的取向不同的取向之外的器件的不同取向。此外,诸如“第一”、“第二”等的术语也用于描述各种元件、区、区段等,并且也不旨在是限制性的。在整个说明书中,相似的术语指代相似的元件。
如本文中所使用的术语“具有”、“包含”、“包括”等是开放式术语,其指示所陈述的元件或特征的存在,但是不排除额外的元件或特征。除非上下文另外明确指出,否则冠词“一”和“所述”旨在包括复数和单数。
考虑到以上变化和应用的范围,应当理解,本发明不受前述说明书的限制,也不受附图的限制。相反,本发明仅受所附权利要求及其合法的等同物限制。
Claims (16)
1.一种半导体封装,包括:
管芯焊盘,所述管芯焊盘包括:管芯附接表面;后表面,所述后表面与所述管芯附接表面相对;以及外部边缘侧,所述外部边缘侧在所述管芯附接表面与所述后表面之间延伸,所述外部边缘侧具有阶梯形轮廓,其中,所述管芯焊盘的上部区段横向悬垂超过所述管芯焊盘的下部区段;
半导体管芯,所述半导体管芯安装在所述管芯附接表面上,并且包括处于所述半导体管芯的背离所述管芯附接表面的上表面上的第一电端子;以及
第一导电夹,所述第一导电夹直接电接触所述第一电端子,并且环绕所述管芯焊盘的所述外部边缘侧,使得所述第一导电夹的区段至少部分地处于这样的区域内,所述区域直接处于所述管芯焊盘的所述上部区段下方,并且直接横向邻近所述下部区段。
2.根据权利要求1所述的半导体封装,还包括:
包封所述半导体管芯的电绝缘的包封物,
其中,所述包封物包括在所述半导体管芯之上延伸的顶表面、与所述顶表面相对的底表面,并且
其中,所述第一导电夹的最下表面在所述包封物的所述底表面的平面处或上方。
3.根据权利要求2所述的半导体封装,其中,所述第一导电夹的所述最下表面是在所述第一导电夹中的成角度的弯曲部与所述第一导电夹的外部端部之间延伸的接触表面,其中,所述接触表面和所述管芯焊盘的所述后表面基本上彼此共面,并且其中,所述接触表面和所述管芯焊盘的所述后表面从所述包封物暴露。
4.根据权利要求3所述的半导体封装,其中,所述包封物的所述底表面与所述接触表面和所述管芯焊盘的所述后表面基本上共面。
5.根据权利要求2所述的半导体封装,其中,所述半导体管芯安装在所述管芯焊盘上,使得所述半导体管芯横向悬垂超过所述管芯焊盘的所述下部区段,并且其中,所述第一导电夹的所述外部端部直接设置在所述半导体管芯下方。
6.根据权利要求2所述的半导体封装,其中,所述半导体封装包括中间层,所述中间层设置在所述半导体管芯的下表面与所述管芯附接表面之间,其中,所述中间层横向悬垂超过所述管芯焊盘的所述下部区段,并且其中,所述第一导电夹的所述外部端部直接设置在所述中间层下方。
7.根据权利要求2所述的半导体封装,其中,所述半导体封装还包括与所述管芯焊盘间隔开的导电引线,其中,所述半导体管芯还包括第二电端子和第三电端子,所述第二电端子和所述第三电端子设置在所述半导体管芯的与所述半导体管芯的所述上表面相对的下表面上,其中,所述第二电端子直接电接触所述管芯附接表面,并且其中,所述第三电端子直接电接触所述引线的上表面。
8.根据权利要求2所述的半导体封装,其中,所述半导体管芯还包括设置在所述半导体管芯的所述上表面处的第二电端子,并且其中,所述半导体封装还包括第二导电夹,所述第二导电夹直接电接触所述第二电端子,并且环绕所述管芯焊盘的所述外部边缘侧,使得所述第二导电夹的外部端部至少部分地处于这样的区域内,所述区域直接处于所述管芯焊盘的所述上部区段下方,并且直接横向邻近所述下部区段。
9.根据权利要求2所述的半导体封装,其中,所述第一导电夹包括中心焊盘和细长的指状部,其中,所述中心焊盘直接设置在所述第一电端子之上,其中,所述细长的指状部比所述中心焊盘窄,其中,所述细长的指状部与所述中心焊盘连接,并且伸出到所述包封物外,并且其中,所述细长的指状部的从所述包封物暴露的部分环绕所述管芯焊盘的所述外部边缘侧,并且延伸到所述第一导电夹的外部端部。
10.根据权利要求9所述的半导体封装,其中,所述包封物完全覆盖所述中心焊盘。
11.根据权利要求9所述的半导体封装,其中,所述中心焊盘延伸到所述包封物的所述顶表面,并且所述中心焊盘包括从所述包封物暴露的上表面。
12.根据权利要11所述的半导体封装,其中,所述中心焊盘的厚度大于所述细长的指状部的厚度,所述中心焊盘的所述厚度是在所述中心焊盘的所述上表面与所述中心焊盘的面对所述第一电端子的下表面之间测量的,所述细长的指状部的所述厚度是在与所述中心焊盘连接的所述细长的指状部的相对面对的上表面与下表面之间测量的。
13.根据权利要求9所述的半导体封装,其中,所述第一导电夹包括多个所述细长的指状部,其中,所述细长的指状部中的每一个彼此间隔开,并且连接到所述中心焊盘的同一侧。
14.一种封装半导体器件的方法,包括:
提供管芯焊盘,所述管芯焊盘包括管芯附接表面、与所述管芯附接表面相对的后表面、以及在所述管芯附接表面与所述后表面之间延伸的外部边缘侧,所述外部边缘侧具有阶梯形轮廓,其中,所述管芯焊盘的上部区段横向悬垂超过所述管芯焊盘的下部区段;
将半导体管芯安装在所述管芯附接表面上,使得所述半导体管芯的上表面上的第一电端子背离所述管芯附接表面;以及
提供第一导电夹,所述第一导电夹直接电接触所述第一电端子,并且环绕所述管芯焊盘的所述外部边缘侧,使得所述第一导电夹的外部端部至少部分地处于这样的区域内,所述区域直接处于所述管芯焊盘的所述上部区段下方,并且直接横向邻近所述下部区段。
15.根据权利要求14所述的方法,还包括:
形成包封所述半导体管芯的电绝缘的包封物,
其中,所述包封物被形成为包括在所述半导体管芯之上延伸的顶表面、与所述顶表面相对的底表面,并且
其中,所述第一导电夹的最下表面在所述包封物的所述底表面的平面处或上方。
16.根据权利要求15所述的方法,其中,提供所述第一导电夹包括:
提供电接触所述第一端子的导电金属的平面条状物;
在提供导电金属的所述平面条状物之后形成所述包封物,使得所述平面条状物的暴露部分伸出到所述包封物外;以及
弯曲所述平面条状物的所述暴露部分,使得所述暴露部分环绕所述管芯焊盘的所述外部边缘侧,使得所述第一导电夹的外部端部至少部分地处于所述区域内,所述区域直接处于所述管芯焊盘的所述上部区段下方,并且直接横向邻近所述下部区段。
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