CN1228784C - 非易失性半导体存储装置的编程方法 - Google Patents

非易失性半导体存储装置的编程方法 Download PDF

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Publication number
CN1228784C
CN1228784C CNB021191735A CN02119173A CN1228784C CN 1228784 C CN1228784 C CN 1228784C CN B021191735 A CNB021191735 A CN B021191735A CN 02119173 A CN02119173 A CN 02119173A CN 1228784 C CN1228784 C CN 1228784C
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China
Prior art keywords
mentioned
memory cell
control gate
voltage
memory device
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Expired - Fee Related
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CNB021191735A
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English (en)
Chinese (zh)
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CN1391231A (zh
Inventor
金井正博
龟井辉彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hello Lsi Design And Installation Technology Inc
Seiko Epson Corp
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Hello Lsi Design And Installation Technology Inc
Seiko Epson Corp
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Publication of CN1391231A publication Critical patent/CN1391231A/zh
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
CNB021191735A 2001-05-11 2002-05-10 非易失性半导体存储装置的编程方法 Expired - Fee Related CN1228784C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001141616A JP2002334588A (ja) 2001-05-11 2001-05-11 不揮発性半導体記憶装置のプログラム方法
JP141616/01 2001-05-11
JP141616/2001 2001-05-11

Publications (2)

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CN1391231A CN1391231A (zh) 2003-01-15
CN1228784C true CN1228784C (zh) 2005-11-23

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CNB021191735A Expired - Fee Related CN1228784C (zh) 2001-05-11 2002-05-10 非易失性半导体存储装置的编程方法

Country Status (5)

Country Link
US (1) US6587380B2 (fr)
EP (1) EP1256959A3 (fr)
JP (1) JP2002334588A (fr)
KR (1) KR100474626B1 (fr)
CN (1) CN1228784C (fr)

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JP3821032B2 (ja) * 2002-03-20 2006-09-13 セイコーエプソン株式会社 ファイルストレージ型不揮発性半導体記憶装置
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JP3815381B2 (ja) * 2002-06-06 2006-08-30 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
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JP2004199738A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 不揮発性記憶装置
JP3587842B2 (ja) 2002-12-17 2004-11-10 沖電気工業株式会社 データ書き換え装置およびデータ書き換え方法ならびにフラッシュメモリ装置
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JP2004265508A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 不揮発性半導体記憶装置
JP3873908B2 (ja) * 2003-02-28 2007-01-31 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
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US7447077B2 (en) * 2005-08-05 2008-11-04 Halo Lsi, Inc. Referencing scheme for trap memory
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JP5311784B2 (ja) * 2006-10-11 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
US8677056B2 (en) * 2008-07-01 2014-03-18 Lsi Corporation Methods and apparatus for interfacing between a flash memory controller and a flash memory array
US8611169B2 (en) * 2011-12-09 2013-12-17 International Business Machines Corporation Fine granularity power gating
CN103778948A (zh) * 2014-01-09 2014-05-07 上海华虹宏力半导体制造有限公司 存储器阵列的控制方法
US9881683B1 (en) 2016-12-13 2018-01-30 Cypress Semiconductor Corporation Suppression of program disturb with bit line and select gate voltage regulation
JP2019057335A (ja) * 2017-09-19 2019-04-11 東芝メモリ株式会社 半導体記憶装置

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US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
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JPH07161851A (ja) 1993-12-10 1995-06-23 Sony Corp 半導体不揮発性記憶装置およびその製造方法
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JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
KR20010004269A (ko) * 1999-06-28 2001-01-15 김영환 플래쉬 메모리 셀 어레이 구조 및 데이터 기록 방법
US6255166B1 (en) 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
JP4058219B2 (ja) * 1999-09-17 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路
KR100308132B1 (ko) * 1999-10-07 2001-11-02 김영환 비휘발성 메모리소자와 그의 셀어레이 및 그의 데이타 센싱방법
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JP2001357682A (ja) * 2000-06-12 2001-12-26 Sony Corp メモリシステムおよびそのプログラム方法
JP2001357681A (ja) * 2000-06-12 2001-12-26 Sony Corp 半導体記憶装置およびその駆動方法
ATE392698T1 (de) * 2000-12-05 2008-05-15 Halo Lsi Design & Device Tech Programmier- und löschverfahren in zwilling-monos-zellenspeichern
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JP4715024B2 (ja) * 2001-05-08 2011-07-06 セイコーエプソン株式会社 不揮発性半導体記憶装置のプログラム方法

Also Published As

Publication number Publication date
KR20030009119A (ko) 2003-01-29
CN1391231A (zh) 2003-01-15
US20030002343A1 (en) 2003-01-02
EP1256959A3 (fr) 2003-10-01
JP2002334588A (ja) 2002-11-22
US6587380B2 (en) 2003-07-01
EP1256959A2 (fr) 2002-11-13
KR100474626B1 (ko) 2005-03-08

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C14 Grant of patent or utility model
GR01 Patent grant
CI01 Correction of invention patent gazette

Correction item: Patentee

Correct: Seiko Epson Corp.

False: Seiko Epson Corp.|Hello, LSI design and installation technology, Inc.

Number: 47

Page: 828

Volume: 21

CI03 Correction of invention patent

Correction item: Patentee

Correct: Seiko Epson Corp.

False: Seiko Epson Corp.|Hello, LSI design and installation technology, Inc.

Number: 47

Page: The title page

Volume: 21

COR Change of bibliographic data

Free format text: CORRECT: PATENTEE; FROM: SEIKO EPSON CORP. HARROW LSI DESIGN AND INSTALLATION TECHNOLOGY COMPANY TO: SEIKO EPSON CORP.

ERR Gazette correction

Free format text: CORRECT: PATENTEE; FROM: SEIKO EPSON CORP. HARROW LSI DESIGN AND INSTALLATION TECHNOLOGY COMPANY TO: SEIKO EPSON CORP.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20051123

Termination date: 20130510