CN114303199B - 通过限制擦除和编程之间的时间间隙来提高模拟非易失性存储器中的读取电流稳定性的方法 - Google Patents
通过限制擦除和编程之间的时间间隙来提高模拟非易失性存储器中的读取电流稳定性的方法 Download PDFInfo
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Abstract
本发明公开了一种具有非易失性存储器单元和控制器的存储器设备。响应于擦除和编程存储器单元的第一组的第一命令,该控制器确定该第一组可以在其擦除后的大致10秒内被编程,擦除该第一组,并且在其擦除后的大致10秒内对该第一组进行编程。响应于擦除和编程存储器单元的第二组的第二命令,该控制器确定该第二组无法在其擦除后的大致10秒内被编程,将该第二组分成存储器单元的子组,每个子组可以在其擦除后的大致10秒内被编程,并且针对子组中的每一个子组,擦除子组并且在其擦除后的大致10秒内对该子组进行编程。
Description
相关专利申请
本申请要求于2019年9月3日提交的美国临时申请号62/895,458和于2020年2月27日提交的美国专利申请号16/803,418的权益。
技术领域
本发明涉及非易失性存储器设备,并且更具体地涉及提高读取操作期间存储器单元电流的稳定性。
背景技术
非易失性存储器设备在本领域中是公知的。参见例如美国专利7,868,375,其公开了四栅极存储器单元配置。具体地,本申请的图1示出了具有在硅半导体衬底12中形成的间隔开的源极区14/漏极区16的分裂栅存储器单元10。源极区14可以被称为源极线SL(因为其通常连接到同一行或列中其他存储器单元的其他源极区),并且漏极区16通常通过位线触点28连接到位线。衬底的沟道区18被限定在源极区14/漏极区16之间。浮栅20设置在沟道区18的第一部分上方并且与其绝缘(并且控制其导电性)(并且部分地位于源极区14上方并且与其绝缘)。控制栅极22设置在浮栅20上方并且与其绝缘。选择栅极24设置在沟道区18的第二部分上方并且与其绝缘(并且控制其导电性)。擦除栅极26设置在源极区14上方并且与其绝缘,并且与浮栅20侧向相邻。多个此类存储器单元可以按行和列排列以形成存储器单元阵列。
将各种组合的电压施加到控制栅极22、选择栅极24、擦除栅极26和/或源极区14/漏极区16,以对存储器单元进行编程(即,将电子注入到浮栅中)、擦除存储器单元(即,从浮栅移除电子),以及读取存储器单元(即,测量或检测沟道区18的电导率以确定浮栅20的编程状态)。
存储器单元10可以数字方式操作,其中存储器单元被设置为仅两种可能的状态中的一种:编程状态和擦除状态。通过在擦除栅极26上施加高正电压并且可选地在控制栅极22上施加负电压来擦除存储器单元,以引起电子从浮栅20到擦除栅极26的隧穿(使浮栅处于带更多正电荷的状态-擦除状态)。可以通过在控制栅极22、擦除栅极26、选择栅极24和源极区14上施加正电压以及在漏极区16上施加电流来对存储器单元10进行编程。然后,电子将沿沟道区18从漏极区16流向源极区14,其中电子变得加速并且变热,由此它们中的一些通过热电子注入被注入到浮栅20上(使浮栅处于带更多负电荷的状态-编程状态)。可以通过在选择栅极24(导通选择栅极24下方的沟道区部分)和漏极区16(并且可选地在擦除栅极26和/或控制栅极22上)上施加正电压并且感测流过沟道区18的电流来读取存储器单元10。如果浮栅20带正电(存储器单元被擦除),则存储器单元将导通,并且电流将从源极区14流动到漏极区16(即,基于所感测的电流感测到存储器单元10处于其擦除的“1”状态)。如果浮栅20带负电(存储器单元被编程),则浮栅下方的沟道区被关断,从而防止任何电流(即,基于无电流而将存储器单元10感测为处于其被编程的“0”状态)。
表1提供了擦除、编程和读取电压的非限制性示例,其中Vcc是电源电压或另一个正电压,例如2.5V。
表1
WL(SG) | BL(漏极) | 源极 | EG | CG | |
擦除 | 0V | 0V | 0V | 11.5V | 0V |
编程 | 1V | 1μA | 4.5V | 4.5V | 10.5V |
读取 | Vcc | 0.6V | 0V | 0V | Vcc |
存储器单元10可以另选地以模拟方式操作,其中存储器单元的存储器状态(即,浮栅上的电荷量,诸如电子数)可以从完全擦除状态(浮栅上的电子最少)连续改变到完全编程状态(浮栅上的电子数最多),或者只是该范围的一部分。这意味着单元存储是模拟的,这允许对存储器单元阵列中的每一个存储器单元进行非常精确和单独的调整。另选地,存储器可以被操作为MLC(多级单元),其中该MLC被配置为被编程为许多离散值(诸如16或64个不同值)中的一个离散值。在模拟或MLC编程的情况下,编程电压仅在有限的时间内或作为一系列脉冲施加,直到实现期望的编程状态。在多个编程脉冲的情况下,可以使用编程脉冲之间的中间读取操作来确定期望的编程状态是否已经实现(在这种情况下编程停止)或尚未实现(在这种情况下编程继续)。
以模拟方式或作为MLC操作的存储器单元10可以对噪声和读取电流不稳定性更敏感,这会对存储器设备的准确度产生不利影响。模拟非易失性存储器设备中的读取电流不稳定性的一个来源是栅极氧化物-沟道界面上的电子阱捕获和发射电子。栅极氧化物是隔离浮栅20和衬底12的沟道区18的绝缘层。当电子在界面阱上被捕获时,它会降低读取操作期间的沟道电导率,从而增加存储器单元的阈值电压Vt(即,导通存储器单元的沟道区以产生一定水平的电流所需的控制栅极上的最小电压,例如1μA)。当控制栅极电压等于或高于阈值电压时,在源极区和漏极区之间形成导电路径。当控制栅极电压低于阈值电压时,不会产生导电路径,并且任何源极/漏极电流都被视为子阈值或漏电流。在界面阱上捕获的电子可以从阱发射,这降低了存储器单元的Vt,从而增加了读取操作期间的沟道电导率。这些电子捕获和发射的单电子事件导致1)随机电报噪声(RTN)和2)单向Vt偏移(还导致读取电流的单向变化),这被称为弛豫或CCI-单元电流不稳定性。
在存储器单元长时间保持在室温下或者在一种状态下在高温下烘烤然后改变为不同状态之后,已经检测到这种弛豫。弛豫表现为存储器单元新状态向前一状态的小的有限漂移。例如,如果存储器单元在其擦除状态下保持一段时间(其特征在于读取操作期间的低Vt和高沟道电流),随后被编程到其编程状态(其特征在于读取操作期间的高Vt和低沟道电流),则在相同的读取条件下,随着时间的推移,发现Vt略微下降,并且发现读取操作期间的读取电流略微增加。当与以数字方式操作的存储器单元的“1”和“0”状态之间的典型单元电流操作窗口相比时,Vt和读取电流偏移相对较小。然而,对于作为MLC(多级单元)或以模拟方式操作的存储器单元,这些偏移可能不可忽略。
需要减少非易失性存储器设备中的读取电流不稳定性。
发明内容
具有多个非易失性存储器单元和控制器的存储器设备解决了上述问题和需求。控制器被配置为接收用于擦除和编程存储器单元的第一组的第一命令,确定存储器单元的第一组可以在擦除存储器单元的第一组后的大致10秒内被编程,在组擦除操作中擦除存储器单元的第一组,在组擦除操作后的大致10秒内对存储器单元的第一组进行编程,接收用于擦除和编程存储器单元的第二组的第二命令,确定无法在擦除存储器单元的第二组后的大致10秒内对存储器单元的第二组进行编程,将存储器单元的第二组分成存储器单元的多个子组,其中每个子组可以在擦除存储器单元的相应的一个子组后的大致10秒内被编程,并且针对存储器单元的子组中的每一个子组,在子组擦除操作中擦除存储器单元的子组,并且在子组擦除操作后的大致10秒内对存储器单元的子组进行编程。
一种操作具有多个非易失性存储器单元的存储器设备的方法包括:接收用于擦除和编程存储器单元的第一组的第一命令,确定存储器单元的第一组可以在擦除存储器单元的第一组后的大致10秒内被编程,在组擦除操作中擦除存储器单元的第一组,在组擦除操作后的大致10秒内对存储器单元的第一组进行编程,接收用于擦除和编程存储器单元的第二组的第二命令,确定无法在擦除存储器单元的第二组后的大致10秒内对存储器单元的第二组进行编程,将存储器单元的第二组分成存储器单元的多个子组,其中每个子组可以在擦除存储器单元的相应的一个子组后的大致10秒内被编程,并且针对存储器单元的子组中的每一个子组,在子组擦除操作中擦除存储器单元的子组,并且在子组擦除操作后的大致10秒内对存储器单元的子组进行编程。
通过查看说明书、权利要求书和附图,本发明的其他目的和特征将变得显而易见。
附图说明
图1是现有存储器单元的侧面剖视图。
图2是示出存储器设备的部件的图。
图3是示出擦除和编程存储器单元的步骤的流程图。
具体实施方式
本发明是一种用于稳定图1的类型的非易失性存储器单元,优选的是以模拟方式操作的非易失性存储器单元的读取电流的技术,以提高读取操作的准确性和存储器保持寿命。以模拟方式操作的存储器单元可以仅使用编程状态的模拟操作范围,该模拟操作范围仅是完全擦除(浮栅上的电子数最小)(在本文中定义为在编程状态的模拟操作范围之外)和完全编程(浮栅上的电子数最大)之间编程状态的完整操作范围的一部分,如上所述。即,在存储器设备的使用寿命期间,存储器设备可以被配置为使得存储器单元主要保持在该模拟操作范围内。在模拟编程之前,存储器单元阵列被擦除,使得擦除的存储器单元的Vt远低于模拟操作范围。然后通过对每个存储器单元的单独调整来对存储器单元进行编程,使得经过编程的存储器单元的Vt在模拟操作范围内。读取稳定技术涉及配置存储器设备的控制器,使得在正常操作期间,每当擦除存储器单元,然后将其编程为模拟操作范围内的Vt值时,存储器单元擦除和存储器单元编程之间的时间被限制为大致10秒或更短。本发明人已经确定,如果擦除存储器单元和编程存储器单元之间的延迟为大致10秒或更短,则将减少或消除后续读取操作期间沟道电流的不期望的偏移(弛豫)。
从如图2所示的示例性存储器设备的架构可以更好地理解存储器阵列的擦除和编程。存储器设备包括非易失性存储器单元10的阵列50,该阵列可以被分隔成两个单独的平面(平面A 52a和平面B 52b)。存储器单元10可以是图1中所示的类型的存储器单元,可以形成在单个芯片上,可以在半导体衬底12中按多行和多列布置。与非易失性存储器单元阵列相邻的是地址解码器(例如,XDEC 54)、源极线驱动器(例如,SLDRV 56)、列解码器(例如,YMUX 58)、高压行解码器(例如,HVDEC 60)和位线控制器(例如,BLINHCTL 62),它们用于在所选择的存储器单元的读取、编程和擦除操作期间对地址进行解码并且向各种存储器单元栅极和区提供各种电压。列解码器58包括读出放大器,该读出放大器包含用于在读取操作期间测量位线上的电流的电路。控制器66(包含控制电路)控制各种设备元件以实施目标存储器单元上的每个操作(编程、擦除、读取)。电荷泵CHRGPMP 64提供用于在控制器66的控制下读取、编程和擦除存储器单元的各种电压。控制器66被配置为操作存储器设备以对存储器单元10进行编程、擦除和读取。作为这些操作的一部分,控制器66被提供对传入数据的访问,该传入数据是待编程到存储器单元的数据(并且可以包括在提供数据之前、期间或之后在相同或不同行上提供的擦除/编程命令)。还可以提供单独的读取和擦除命令。从存储器阵列读取的数据被提供为传出数据。
为了效率,存储器设备优选地被配置为在单个擦除操作中同时擦除多个存储器单元。例如,可以同时擦除存储器单元的整行或列。或者,可以同时擦除整个块的行和列。因此,控制器66被配置为针对任何给定的擦除/编程操作选择要同时擦除的存储器单元的数量,使得那些擦除的存储器单元的后续编程可以在擦除后的大致10秒内完成。例如,对于任何一组被同时擦除的存储器单元,从该存储器单元的组的擦除完成到该组中最后一个存储器单元的编程完成,测量到10秒。如果特定的擦除/编程操作涉及无法在10秒内擦除和编程的给定数量的存储器单元,则控制器66被配置为一次一组地对这些存储器单元的组进行操作(擦除和编程),以确保所有存储器单元在从它们被擦除之时起大致10秒或更短的时间内被编程。
例如,如果控制器66在擦除操作之后对X存储器单元进行编程大致需要10秒,则涉及Y(其中Y大于X)存储器单元的任何擦除/编程操作将导致控制器将Y存储器单元分成两组或更多个组,每一组不超过X存储器单元,从而一次一组地对每一组应用擦除/编程操作,使得每一组中的所有存储器单元的编程可以在该存储器单元的组被擦除后的大致10秒或更短的时间内完成。因此,对于每个擦除/编程操作,控制器执行该操作,使得任何给定数量的存储器单元的所有编程在那些相同存储器单元的擦除完成后的大致10秒内完成。
图3示出了本发明的步骤。在步骤1中,控制器66接收(第一)命令以对在组中具有Y存储器单元的存储器单元的组进行擦除和编程。在步骤2中,控制器66确定Y是否大于X,其中X是可以在擦除完成后的大致10秒内编程的存储器单元的最高数量(即,最大限值)。该步骤确定是否可以在擦除Y存储器单元后的大致10秒内对Y存储器单元进行编程。如果Y不大于X,则可以在擦除Y数量的存储器单元后的大致10秒内对Y数量的存储器单元进行编程,并且因此在步骤3中,控制器66(优选地,但不一定同时)擦除组中的所有Y数量的存储器单元,并且在步骤4中,控制器66在擦除后的大致10秒内对组中的Y数量的存储器单元进行编程。然而,如果在步骤2中确定Y大于X,则无法在擦除Y数量的存储器单元后的大致10秒内对Y数量的存储器单元进行编程,并且因此在步骤5中,控制器将Y存储器单元的组分成存储器单元的多个子组,每个子组不超过X。然后,控制器66在步骤6中(优选地,但不一定同时)擦除存储器单元的第一子组,并且在步骤7中在擦除后的大致10秒内对存储器单元的第一子组进行编程。然后,在步骤8中,控制器66针对存储器单元的其他子组中的每一个子组重复步骤6和步骤7。每次接收到擦除/编程命令(即,第二命令、第三命令等)时,重复该过程。利用这种技术,无论擦除和编程命令针对多少个存储器单元,所有存储器单元都在被擦除后的大致10秒内被编程。
为了说明上述技术,非限制性示例可以为8Mbit数字NOR闪存存储器设备,其中每个字节(8位)由具有10μs持续时间的单个脉冲以数字方式编程。在该示例中,该设备的总编程时间至少需要10秒。然而,数据的精确模拟编程可能需要较长的时间来在编程算法中包括多个编程和读取验证步骤。例如,满足模拟编程所需的精度可能需要100个编程脉冲,每个脉冲为0.9μs,并且编程脉冲之间的读取验证持续时间为0.1μs。在该示例中,100万字节的总模拟编程时间至少需要100秒。因此,在这种情况下,模拟编程之前执行的擦除操作不会对整个闪存存储器设备执行,而是仅针对闪存存储器设备内的阵列的最多十分之一的存储器单元块执行,使得用于刚擦除的块的编程时间将不超过大致10秒。
应当注意,通过防止任何存储器单元停留在其擦除状态超过大致10秒来实现本发明的优点。因此,根据本发明,对于被擦除的任何存储器单元的组,该组中的每个存储器单元在大致10秒内经历至少一些编程,但存储器单元中的一些存储器单元不打算利用数据进行编程。例如,如果被擦除的单元组中的存储器单元不打算利用任何数据进行编程,则存储器单元可以被完全编程或深度过度编程以便在模拟操作范围之外,从而有效地最小化在读取同一位线上的其他存储器单元时该存储器单元可能增加到位线电流的任何贡献。因此,无论什么数据被编程到经历擦除的存储器单元的组,该组中的所有存储器单元都被编程为使得不存在处于擦除状态超过大致10秒的存储器单元(参见图3的步骤4或步骤7至步骤8)。如本文所用,对一组或多个存储器单元进行编程意味着该组或多个存储器单元中的每一个存储器单元经历至少一些编程(即,至少一些电子注入到浮栅上)。
应当理解,本发明不限于上述的和在本文中示出的实施方案,而是涵盖在任何权利要求书的范围内的任何和所有变型形式。例如,本文中对本发明的提及并不意在限制任何权利要求书或权利要求术语的范围,而是仅与可由这些权利要求中的一项或多项权利要求涵盖的一个或多个特征相关。上文所述的材料、工艺和数值的示例仅为示例性的,而不应视为限制权利要求书。另外,如从权利要求和说明书中显而易见的,除非另有说明,否则并非所有方法步骤都需要按所示或所要求的具体顺序执行。
Claims (12)
1.一种存储器设备,所述存储器设备包括:
多个非易失性存储器单元;
控制器,所述控制器被配置为:
接收用于擦除和编程所述存储器单元的第一组的第一命令,
确定所述存储器单元的所述第一组能够在擦除所述存储器单元的所述第一组后的大致10秒内被编程,
在组擦除操作中擦除存储器单元的所述第一组,
在所述组擦除操作后的大致10秒内对存储器单元的所述第一组进行编程,
接收用于擦除和编程所述存储器单元的第二组的第二命令,
确定所述存储器单元的所述第二组无法在擦除所述存储器单元的所述第二组后的大致10秒内被编程,
将所述存储器单元的所述第二组分成所述存储器单元的多个子组,其中所述子组中的每一个子组能够在擦除所述存储器单元的相应的一个子组后的大致10秒内被编程,以及
针对所述存储器单元的所述子组中的每一个子组:
在子组擦除操作中擦除存储器单元的所述子组,以及
在所述子组擦除操作后的大致10秒内对存储器单元的所述子组进行编程。
2.根据权利要求1所述的设备,其中所述控制器被进一步配置为在所述组擦除操作中同时擦除所述存储器单元的所述第一组中的至少所有所述存储器单元。
3.根据权利要求1所述的设备,其中针对所述存储器单元的所述子组中的每一个子组,所述控制器被进一步配置为在所述子组擦除操作中同时擦除所述存储器单元的所述子组中的至少所有所述存储器单元。
4.根据权利要求1所述的设备,其中所述控制器被配置为基于所述存储器单元的所述第一组中的所述存储器单元的数量不超过预先确定的数量,确定所述存储器单元的所述第一组能够在擦除所述存储器单元的所述第一组后的大致10秒内被编程,并且基于所述存储器单元的所述第二组中的所述存储器单元的数量确实超过所述预先确定的数量,确定无法在擦除所述存储器单元的所述第二组后的大致10秒内对所述存储器单元的所述第二组进行编程。
5.根据权利要求1所述的设备,其中所述存储器单元中的每一个存储器单元包括:
间隔开的源极区和漏极区,所述间隔开的源极区和漏极区形成于半导体衬底中,其中所述衬底的沟道区在所述源极区和所述漏极区之间延伸,
浮栅,所述浮栅竖直地设置在所述沟道区的第一部分上方并且与其绝缘,
选择栅极,所述选择栅极竖直地设置在所述沟道区的第二部分上方并且与其绝缘,以及
控制栅极,所述控制栅极竖直地设置在所述浮栅上方并且与其绝缘。
6.根据权利要求5所述的设备,其中所述存储器单元中的每一个存储器单元还包括:
设置在所述源极区上方并且与其绝缘的擦除栅。
7.一种操作具有多个非易失性存储器单元的存储器设备的方法,所述方法包括:
接收用于擦除和编程所述存储器单元的第一组的第一命令,
确定所述存储器单元的所述第一组能够在擦除所述存储器单元的所述第一组后的大致10秒内被编程,
在组擦除操作中擦除存储器单元的所述第一组,
在所述组擦除操作的大致10秒内对存储器单元的所述第一组进行编程,
接收用于擦除和编程所述存储器单元的第二组的第二命令,
确定所述存储器单元的所述第二组无法在擦除所述存储器单元的所述第二组后的大致10秒内被编程,
将所述存储器单元的所述第二组分成所述存储器单元的多个子组,其中所述子组中的每一个子组能够在擦除所述存储器单元的相应的一个子组后的大致10秒内被编程,以及
针对所述存储器单元的所述子组中的每一个子组:
在子组擦除操作中擦除存储器单元的所述子组,以及
在所述子组擦除操作后的大致10秒内对存储器单元的所述子组进行编程。
8.根据权利要求7所述的方法,其中所述擦除存储器单元的所述第一组还包括同时擦除所述存储器单元的所述第一组中的至少所有所述存储器单元。
9.根据权利要求7所述的方法,其中针对所述存储器单元的所述子组中的每一个子组,所述擦除所述存储器单元的所述子组还包括同时擦除所述存储器单元的所述子组中的至少所有所述存储器单元。
10.根据权利要求7所述的方法,其中确定所述存储器单元的所述第一组能够在擦除所述存储器单元的所述第一组后的大致10秒内被编程是基于所述存储器单元的所述第一组中的所述存储器单元的数量不超过预先确定的数量,并且确定无法在擦除所述存储器单元的所述第二组后的大致10秒内对所述存储器单元的所述第二组进行编程是基于所述存储器单元的所述第二组中的所述存储器单元的数量确实超过所述预先确定的数量。
11.根据权利要求7所述的方法,其中所述存储器单元中的每一个存储器单元包括:
间隔开的源极区和漏极区,所述间隔开的源极区和漏极区形成于半导体衬底中,其中所述衬底的沟道区在所述源极区和所述漏极区之间延伸,
浮栅,所述浮栅竖直地设置在所述沟道区的第一部分上方并且与其绝缘,
选择栅极,所述选择栅极竖直地设置在所述沟道区的第二部分上方并且与其绝缘,以及
控制栅极,所述控制栅极竖直地设置在所述浮栅上方并且与其绝缘。
12.根据权利要求11所述的方法,其中所述存储器单元中的每一个存储器单元还包括:
设置在所述源极区上方并且与其绝缘的擦除栅。
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