CN114287037A - 在预先确定的编程状态下使用最终烘烤来提高模拟非易失性存储器中读取电流稳定性的方法 - Google Patents

在预先确定的编程状态下使用最终烘烤来提高模拟非易失性存储器中读取电流稳定性的方法 Download PDF

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CN114287037A
CN114287037A CN202080060960.0A CN202080060960A CN114287037A CN 114287037 A CN114287037 A CN 114287037A CN 202080060960 A CN202080060960 A CN 202080060960A CN 114287037 A CN114287037 A CN 114287037A
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programmed
memory cells
state
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memory cell
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V·马克夫
A·柯多夫
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Silicon Storage Technology Inc
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Abstract

一种提高存储器设备稳定性的方法，该存储器设备具有控制器，该控制器被配置成在由最小编程状态和最大编程状态界定的编程状态范围内对多个非易失性存储器单元中的每个非易失性存储器单元进行编程。该方法包括测试存储器单元以确认存储器单元是可操作的，将存储器单元中的每一个存储器单元编程为中间编程状态，以及在将存储器单元编程为该中间编程状态时在高温下烘烤该存储器设备。每个存储器单元在该最小编程状态下编程时具有第一阈值电压，在该最大编程状态下编程时具有第二阈值电压，并且在该中间编程状态下编程时具有第三阈值电压。该第三阈值电压基本上处于该第一阈值电压和该第二阈值电压之间的中点，并且对应于读取电流的实际的对数中点。

Description

在预先确定的编程状态下使用最终烘烤来提高模拟非易失性 存储器中读取电流稳定性的方法
相关专利申请
本申请要求于2019年9月3日提交的美国临时申请号62/895,458和于2020年2月27日提交的美国专利申请号16/803,401的权益。
技术领域
本发明涉及非易失性存储器设备，并且更具体地涉及提高读取操作期间存储器单元电流的稳定性。
背景技术
非易失性存储器设备在本领域中是公知的。参见例如美国专利7,868,375，公开了四栅极存储器单元配置。具体地，本申请的图1示出了具有在硅半导体衬底12中形成的间隔开的源极区14和漏极区16的分裂栅存储器单元10。源极区14可以被称为源极线SL(因为其通常连接到同一行或列中其他存储器单元的其他源极区)，并且漏极区16通常通过位线触点28连接到位线。衬底的沟道区18被限定在源极区14/漏极区16之间。浮栅20设置在沟道区18的第一部分上方并且与该第一部分绝缘(并且控制其导电性)(并且部分地位于源极区14上方并且与其绝缘)。控制栅极22设置在浮栅20上方并且与其绝缘。选择栅极24设置在沟道区18的第二部分上方并且与该第二部分绝缘(并且控制其导电性)。擦除栅极26设置在源极区14上方并且与其绝缘，并且与浮栅20侧向相邻。多个此类存储器单元可以按行和列排列以形成存储器单元阵列。
将各种组合的电压施加到控制栅极22、选择栅极24、擦除栅极26和/或源极区14/漏极区16，以对存储器单元进行编程(即，将电子注入到浮栅中)、擦除存储器单元(即，从浮栅移除电子)，以及读取存储器单元(即，测量或检测沟道区18的电导率以确定浮栅20的编程状态)。
存储器单元10可以数字方式操作，其中存储器单元被设置为仅两种可能的状态中的一种：编程状态和擦除状态。通过在擦除栅极26上施加高正电压并且可选地在控制栅极22上施加负电压来擦除存储器单元，以引起电子从浮栅20到擦除栅极26的隧穿(使浮栅处于带更多正电荷的状态-擦除状态)。可以通过在控制栅极22、擦除栅极26、选择栅极24和源极区14上施加正电压以及在漏极区16上施加电流来对存储器单元10进行编程。然后，电子将沿沟道区18从漏极区16流向源极区14，其中一些电子变得加速并且变热，由此它们通过热电子注入被注入到浮栅20上(使浮栅处于带更多负电荷的状态-编程状态)。可以通过在选择栅极24(导通选择栅极24下方的沟道区部分)和漏极区16(并且可选地在擦除栅极26和/或控制栅极22上)上施加正电压并且感测流过沟道区18的电流来读取存储器单元10。如果浮栅20带正电(被擦除)，则存储器单元将导通，并且电流将从源极区14流动到漏极区16(即，基于所感测的电流感测到存储器单元10处于其擦除“1”状态)。如果浮栅20带负电(被编程)，则浮栅下方的沟道区被关断，从而阻止任何电流流动(即，基于无电流而将存储器单元10感测为处于其被编程的“0”状态)。
下表提供了擦除、编程和读取电压的非限制性示例：
表1
WL(SG) BL(漏极) 源极 EG CG
擦除 0V 0V 0V 11.5V 0V
编程 1V 1μA 4.5V 4.5V 10.5V
读取 Vcc 0.6V 0V 0V Vcc
存储器单元10可以另选地以模拟方式操作，其中存储器单元的存储器状态(即，浮栅上的电荷量，诸如电子数)可以从完全擦除状态(浮栅上的电子最少)连续改变到完全编程状态(浮栅上的电子数最多)，或者只是该范围的一部分。这意味着单元存储是模拟的，这允许对存储器单元阵列中的每一个存储器单元进行非常精确和单独的调整。另选地，存储器可以被操作为MLC(多级单元)，其中该MLC被配置成被编程为许多离散值(诸如16或64个不同值)中的一个离散值。在模拟或MLC编程的情况下，编程电压仅在有限的时间内或作为一系列脉冲施加，直到实现期望的编程状态。在多个编程脉冲的情况下，可以使用编程脉冲之间的中间读取操作来确定期望的编程状态是否已经实现(在这种情况下编程停止)或尚未实现(在这种情况下编程继续)。
以模拟方式或作为MLC操作的存储器单元10可以对噪声和读取电流不稳定性更敏感，这会对存储器设备的准确度产生不利影响。模拟非易失性存储器设备中的读取电流不稳定性的一个来源是栅极氧化物-沟道界面上的电子阱捕获和发射电子。该栅极氧化物是隔离浮栅20和衬底12的沟道区18的绝缘层。当电子在界面阱上被捕获时，它会降低读取操作期间的沟道电导率，从而增加存储器单元的阈值电压Vt(即，导通存储器单元的沟道区以产生一定水平的电流所需的控制栅极上的最小电压，例如1μA)。当控制栅极电压等于或高于阈值电压时，在源极区和漏极区之间形成导电路径。当控制栅极电压低于阈值电压时，不会产生导电路径，并且任何源极/漏极电流都被视为子阈值或漏电流。电子阱再充电的这些单个事件导致1)随机电报噪声(RTN)和2)单向阈值电压(Vt)偏移(还引起读取操作沟道电流的变化)，这被称为弛豫或CCI-单元电流不稳定性。
在存储器单元长时间保持在室温下或者在一种状态下在高温下烘烤然后改变为不同状态之后，已经检测到这种弛豫。弛豫表现为存储器单元新状态向前一状态的小的漂移。例如，如果存储器单元在其擦除状态下保持一段时间(其特征在于读取操作期间的低阈值电压Vt和高沟道电流)，随后被编程到其编程状态(其特征在于读取操作期间的高阈值电压Vt和低沟道电流)，则在相同的读取条件下，随着时间的推移，发现阈值电压Vt略微下降，并且发现读取操作期间的读取电流略微增加。当与以数字方式操作的存储器单元的1和0状态之间的典型单元电流操作窗口相比时，Vt和读取电流偏移相对较小。然而，对于作为MLC(多级单元)或以模拟方式操作的存储器单元，这些偏移可能不可忽略。
需要减少非易失性存储器设备中的读取电流不稳定性。
发明内容
上述问题和需求通过提高存储器设备稳定性的方法来解决，该存储器设备包括多个非易失性存储器单元和控制器，该控制器被配置成在由最小编程状态和最大编程状态界定的编程状态范围内对存储器单元中的每一个存储器单元进行编程。该方法包括测试存储器单元以确认存储器单元是可操作的，将存储器单元中的每一个存储器单元编程为中间编程状态，以及在将存储器单元编程为中间编程状态时在高温下烘烤存储器设备。对于存储器单元中的每一个存储器单元，当在最小编程状态下编程时存储器单元具有第一阈值电压，当在最大编程状态下编程时存储器单元具有第二阈值电压，并且当在中间编程状态下编程时存储器单元具有第三阈值电压，其中该第三阈值电压基本上处于第一阈值电压和第二阈值电压之间的中点。
一种提高存储器设备稳定性的方法，该存储器设备包括多个非易失性存储器单元和控制器，每个非易失性存储器单元至少包括设置在半导体衬底的沟道区上方并且与其绝缘的浮栅和设置在浮栅上方并且与其绝缘的控制栅极，该控制器被配置成在由最小编程状态和最大编程状态界定的编程状态范围内对存储器单元中的每一个存储器单元进行编程，并且使用施加到控制栅极的读取电压来读取存储器单元中的每一个存储器单元。该方法包括测试存储器单元以确认存储器单元是可操作的，将存储器单元中的每一个存储器单元编程为中间编程状态，以及在将存储器单元编程为中间编程状态时在高温下烘烤存储器设备。对于存储器单元中的每一个存储器单元，当在最小编程状态下编程时，存储器单元使用施加到控制栅极的读取电压在读取操作期间产生第一读取电流，当在最大编程状态下编程时，存储器单元使用施加到控制栅极的读取电压在读取操作期间产生第二读取电流，并且当在中间编程状态下编程时，存储器单元使用施加到控制栅极的读取电压在读取操作期间产生第三读取电流，其中该第三读取电流基本上处于第一读取电流和第二读取电流之间的对数中点。
通过查看说明书、权利要求书和附图，本发明的其他目的和特征将变得显而易见。
附图说明
图1是现有存储器单元的侧面剖视图。
图2是示出存储器设备的部件的图。
图3是示出在子阈值操作范围内关于读取电流和阈值电压Vt的存储器单元操作范围的图。
图4是示出对存储器单元进行编程和烘烤的步骤的流程图。
图5是示出操作范围内的存储器单元的I-V特性的示例的图。
具体实施方式
本发明是一种用于稳定图1的类型的非易失性存储器单元的读取电流以提高读取操作准确度和存储器保持寿命的技术。读取稳定技术涉及在执行最终高温烘烤过程之前将完成的和可操作的存储器单元编程为预先确定的编程状态。具体地，在存储器设备测试过程中，设备中的存储器阵列可以各种数据模式经历许多热操作。然而，一旦存储器设备测试完成，所有存储器单元随后就被编程为预先确定的中间编程状态，然后对存储器设备进行最终的高温烘烤。已经发现，通过在存储器单元被编程为中间编程状态时执行该最终的高温烘烤，存储器单元阈值电压(Vt)随时间推移而偏移，从而减小读取操作电流随时间推移的漂移。
期望的中间编程状态是存储器阵列的控制器配置的函数，从图2所示的示例性存储器设备的架构可以更好地理解这一点。存储器设备包括非易失性存储器单元10的阵列50，该阵列可以被分隔成两个单独的平面(平面A 52a和平面B 52b)。存储器单元10可以是图1中所示的类型的存储器单元，可以形成在单个芯片上，可以在半导体衬底12中按多行和多列布置。与非易失性存储器单元阵列相邻的是地址解码器(例如，XDEC 54)、源极线驱动器(例如，SLDRV 56)、列解码器(例如，YMUX 58)、高压行解码器(例如，HVDEC 60)和位线控制器(BLINHCTL 62)，它们用于在所选择的存储器单元的读取、编程和擦除操作期间对地址进行解码并且向各种存储器单元栅极和区提供各种电压。列解码器58包括读出放大器，该读出放大器包含用于在读取操作期间测量位线上的电流的电路。控制器66(包含控制电路)控制各种设备元件以实施目标存储器单元上的每个操作(编程、擦除、读取)。电荷泵CHRGPMP 64提供用于在控制器66的控制下读取、编程和擦除存储器单元的各种电压。控制器66被配置成操作存储器设备以对存储器单元10进行编程、擦除和读取。
正是控制器66指定了在正常用户操作期间可用的存储器单元的最小编程状态和最大编程状态。最小编程状态是存储器单元中的每一个存储器单元在正常用户操作期间在控制器66的控制下可被编程到的编程状态(即，最多擦除状态)，对于该编程状态，最低数量的电子位于浮栅20上并且存储器单元在正常读取操作期间产生最高(最大)源极/漏极电流。最大编程状态是存储器单元中的每一个存储器单元在正常用户操作期间在控制器66的控制下可以被编程到的编程状态，对于该编程状态，最高数量的电子位于浮栅20上并且存储器单元在正常读取操作期间产生最低(最小)源极/漏极电流。
在最终的设备高温烘烤操作期间使用的中间编程状态优选地是这样一种编程状态，其中在读取操作期间产生读取电流，该读取电流是由控制器66指定的定义的编程操作范围的最大编程状态和最小编程状态分别的最小读取电流和最大读取电流之间的对数实际中点。可以通过阈值电压Vt或读取电流作为参数来确定中间编程状态。存储器单元是MOSFET晶体管，并且因此Vt和读取电流经由基本晶体管方程直接相关，因此，可以根据读取电流或Vt来确定存储器单元的操作范围。表明Vt和读取电流之间的关系的存储器单元电流-电压(I-V)特性的示例如图3所示，其中两条曲线分别表示存储器单元的最小编程状态和最大编程状态的I-V特性。在该非限制性示例中，在控制栅极上施加等于或高于阈值电压的电压将导致读取操作期间的读取电流(在源极区和漏极区之间)为1μA或更大，在该示例中，这被认为是指示在源极区/漏极区之间形成导电路径的电流量。图3中电流-电压(I-V)曲线在1μA处的向右拐点指示这是在控制栅极上的电压达到阈值电压Vt时实现的读取电流。
在图3的示例中，右侧曲线(曲线A)是示例性存储器单元在其模拟操作范围的最大编程状态下的I-V曲线，并且左侧曲线(曲线B)是示例性存储器单元在其模拟操作范围的最小编程状态下的I-V曲线。该存储器单元的控制器被配置成使用1.2V的控制栅极上的读取电压，这意味着该存储器单元在子阈值状态下被读取(即，使用子阈值电流来检测存储器单元的编程状态)。考虑到最大编程状态和最小编程状态的两条I-V曲线，控制器操作的该存储器单元的读取电流的操作范围介于100nA和100pA之间。编程状态的范围对应于约0.3V的Vt范围(介于约1.3V和约1.6V之间)。经编程的存储器单元的读取不稳定性可以用Vt变化或读取操作期间的读取电流变化来表示。如下所述，Vt或读取电流可用作量化读取电流波动降低的解决方案的参数。因此，中间编程状态被定义为关于在正常操作期间可实现的最小编程状态和最大编程状态的Vt基本上对应于其一半的编程状态，并且对应于最大编程状态和最小编程状态分别的最小读取电流和最大读取电流之间的对数实际中点。
实现这种读取稳定技术分为三个主要阶段，如图4所示。首先(步骤1)，包括存储器单元10和它们的控制器66的存储器设备被测试到它们是可操作的并且不需要进一步的高温烘烤操作来完成设备的测试。其次(步骤2)，所有存储器单元10被编程为基本上中间编程状态。最后(步骤3)，包括被编程为中间编程状态的所有存储器单元10的存储器设备经历最终的高温烘烤过程。图5示出了上文关于图3描述的被编程为基本上中间编程状态的存储器单元的存储器单元I-V特性曲线(曲线C)的示例。其阈值电压Vt为约1.48V，基本上处于最小编程状态和最大编程状态分别的Vt_min和Vt_max之间的中点(即，中点阈值电压基本上在Vt_min和Vt_max的中间)。类似地，在读取操作期间将1.2V的读取电压施加在控制栅极上时，存储器单元的读取电流为约3nA，这是最小编程状态和最大编程状态分别的100nA和100pA之间的对数实际中点(即，中点读取电流在对数标度上基本上在100nA和100pA之间)。
高烘烤温度是超过存储器设备在正常使用期间所承受的最高操作温度的升高的温度。例如，如果产品在用户条件下的最高操作温度规范为150℃，则最终的高温烘烤过程可以包括在175℃下烘烤存储器设备24小时。最小烘烤时间取决于烘烤温度，并且在较高温度下可能较短。优选地，对于图1所示的存储器单元，在175℃的烘烤温度下烘烤时间可长达24小时。一般来讲，烘烤时间越长，对降低读取不稳定性的改善效果越好。作为实际示例，如果所选择的封装允许此类高温处理，则可以将组装好的零件设置为在175℃下烘烤一天。一旦存储器设备、封装和最终测试和烘烤完成，存储器设备就将在用户条件下以更高的读取稳定性操作。
应当理解，本发明不限于上述的和在本文中示出的实施方案，而是涵盖在任何权利要求书的范围内的任何和所有变型形式。举例来说，本文中对本发明的提及并不意在限制任何权利要求书或权利要求术语的范围，而是仅参考可由这些权利要求中的一项或多项权利要求涵盖的一个或多个特征。上文所述的材料、工艺和数值的示例仅为示例性的，而不应视为限制权利要求书。另外，如从权利要求和说明书中显而易见的，除非另有说明，否则并非所有方法步骤都可能需要按所示或所要求的具体顺序执行。

Claims (6)

1.一种提高存储器设备稳定性的方法，所述存储器设备包括多个非易失性存储器单元和控制器，所述控制器被配置成在由最小编程状态和最大编程状态界定的编程状态范围内对所述存储器单元中的每一个存储器单元进行编程，所述方法包括：
测试所述存储器单元以确认所述存储器单元是可操作的；
将所述存储器单元中的每一个存储器单元编程为中间编程状态；以及
当所述存储器单元被编程为所述中间编程状态时，在高温下烘烤所述存储器设备；
其中，对于所述存储器单元中的每一个存储器单元：
当在所述最小编程状态下编程时，所述存储器单元具有第一阈值电压，
当在所述最大编程状态下编程时，所述存储器单元具有第二阈值电压，并且
当在所述中间编程状态下编程时，所述存储器单元具有第三阈值电压，
其中所述第三阈值电压基本上处于所述第一阈值电压与所述第二阈值电压之间的中点。
2.根据权利要求1所述的方法，其中所述存储器单元中的每一个存储器单元包括：
间隔开的源极区和漏极区，所述间隔开的源极区和漏极区形成于半导体衬底中，其中所述衬底的沟道区在所述源极区和所述漏极区之间延伸，
浮栅，所述浮栅竖直地设置在所述沟道区的第一部分上方并且与所述第一部分绝缘，
选择栅极，所述选择栅极竖直地设置在所述沟道区的第二部分上方并且与所述第二部分绝缘，以及
控制栅极，所述控制栅极竖直地设置在所述浮栅上方并且与其绝缘。
3.根据权利要求2所述的方法，其中所述存储器单元中的每一个存储器单元还包括：
设置在所述源极区上方并且与其绝缘的擦除栅。
4.一种提高存储器设备稳定性的方法，所述存储器设备包括多个非易失性存储器单元和控制器，每个非易失性存储器单元至少包括设置在半导体衬底的沟道区上方并且与其绝缘的浮栅和设置在所述浮栅上方并且与其绝缘的控制栅极，所述控制器被配置成在由最小编程状态和最大编程状态界定的编程状态范围内对所述存储器单元中的每一个存储器单元进行编程，并且使用施加到所述控制栅极的读取电压来读取所述存储器单元中的每一个存储器单元，所述方法包括：
测试所述存储器单元以确认所述存储器单元是可操作的；
将所述存储器单元中的每一个存储器单元编程为中间编程状态；以及
当所述存储器单元被编程为所述中间编程状态时，在高温下烘烤所述存储器设备；
其中，对于所述存储器单元中的每一个存储器单元：
当在所述最小编程状态下编程时，所述存储器单元使用施加到所述控制栅极的所述读取电压在读取操作期间产生第一读取电流，
当在所述最大编程状态下编程时，所述存储器单元使用施加到所述控制栅极的所述读取电压在读取操作期间产生第二读取电流，并且
当在所述中间编程状态下编程时，所述存储器单元使用施加到所述控制栅极的所述读取电压在读取操作期间产生第三读取电流，
其中所述第三读取电流基本上处于所述第一读取电流和所述第二读取电流之间的对数中点。
5.根据权利要求4所述的方法，其中所述存储器单元中的每一个存储器单元包括：
间隔开的源极区和漏极区，所述间隔开的源极区和漏极区形成于半导体衬底中，其中所述衬底的所述沟道区在所述源极区和所述漏极区之间延伸，
浮栅，所述浮栅竖直地设置在所述沟道区的第一部分上方并且与所述第一部分绝缘，
选择栅极，所述选择栅极竖直地设置在所述沟道区的第二部分上方并且与所述第二部分绝缘。
6.根据权利要求5所述的方法，其中所述存储器单元中的每一个存储器单元还包括：
设置在所述源极区上方并且与其绝缘的擦除栅。
CN202080060960.0A 2019-09-03 2020-03-11 在预先确定的编程状态下使用最终烘烤来提高模拟非易失性存储器中读取电流稳定性的方法 Pending CN114287037A (zh)

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