TWI273600B - Integrated circuit and manufacturing method thereof, memory cell and manufacturing method thereof, method for programming memory cell and method for programming memory array multiple times - Google Patents

Abstract

An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode, and a layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Description

1273 6iM) twf.d〇c/〇〇6 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to an electrically programmable non-volatile memory and an integrated circuit including the same. In particular, it relates to a memory cell structure, an operation method for inducing a programmable resistance according to a progressive breakdown of an ultra-thin dielectric layer and related structures. [Prior Art] 4 The electrically programmable non-volatile memory technology has been used in many applications. These various techniques vary with the number of times the memory cells can be programmed, the voltage required to achieve the programming, and the number of bits of data stored in each memory cell. Moreover, an important consideration is whether the particular memory technology provided can meet the needs of the memory cell and the auxiliary circuit during the manufacturing steps. "The hidden technology is built on a floating gate (such as a standard electrically erasable and programmable read-only memory (EEPROM)) or on a charge trapping layer (eg, yttrium oxide yttrium nitride - yttrium oxide) The memory cells can usually be programmed several times. However, these techniques require complex stylization and erasing circuitry and use complex charge pump techniques to achieve the voltages required for stylization and erasing. Moreover, when storing more than one bit of data in a mother cell, complex stylization and sensing techniques are required. Thus, for these types of flash memory, the steps required to fabricate the flash memory typically include the formation of standard logic circuits (such as complementary metal oxide semiconductor (CMOS) circuits) on the same integrated circuit. The generally required steps, and these steps become cost increases. De·Graaf et al. at a Novel High-Density Low-Cost 1273 60^twf.doc/006

Diode Programmble Read-only Memory IEDM 1996, page 7·6·1~7·6·4 discloses a simple readable memory cell. According to Graaf et al., a one-time programmable high-density memory can be borrowed. This is achieved by using a diode-anti-dissolved wire (Diode-antifuse) which is composed of a first n-type polysilicon electrode, a second p-type diffusion electrode, and A dielectric layer between the electrodes, the dielectric layer having a thickness of about 60 angstroms, and the material being a dioxide dioxide formed by a thermal growth method. In this structure, the memory cell is programmed by applying about 13 volts. The high voltage initiates the collapse of the dielectric layer, thereby forming a physical connection between the electrodes of the stylized memory cell. Although the structure disclosed by de Graaf et al. is relatively compact and easy to manufacture, such memory cells are only It can be programmed once and requires high voltage operation. Therefore, there is a need to provide an electrically programmable non-volatile memory technology that can operate at low voltages and is compatible with standard CM〇s logic circuit fabrication techniques. ,and also To provide a non-volatile sibling cell technology, a plurality of stylized operations can be performed on a memory cell and/or more than one bit of data can be stored in a single memory cell. SUMMARY OF THE INVENTION The object of the present invention is to provide a An electrically programmable non-volatile memory cell and a method of fabricating the same, the memory cell comprising a first electrode, a second electrode, and a material layer between the two electrodes, characterized in that the material layer has a measurable characteristic of substantially progressive change, For example, the resistance, reactance, magnetism, polarity, element arrangement, etc. of the material layer, by means of the progressive amount of stress, represent the stored data to create a programmable property. This material layer comprises an ultra-thin material, here 2736ββ twf.doc/ 006 The condition a is that the thickness of the material layer is so thin that the thickness f of the thicker material layer that is stable in normal operation will be added to the mine with the amount of control. Including J with a mosquito thickness; this § recalled cell is characterized by a low voltage across the dielectric sound for a period of time 'and the resistance progressive change caused by the stress progression to establish a resistance, to represent Data stored in - a selected memory cell can be repeated stylized towel does not need to "erase", and can be provided - a multiple programmable memorized body. Of course, by using more money (4) to establish a stylized state in a single-domain memory cell, the multi-programmed state is in accordance with multi-bit data or a corresponding multi-programming cycle. Therefore, the memory cell can be referred to as a programmable resistance erase memory. In the embodiment of the present invention, the memory cell can store multi-bit data in a single memory cell; More than one stylization operation is performed without erasing the operation; multi-bit data can be stored in a single memory cell at the same time and more than one stylized operation can be performed without erasing the operation. Moreover, this memory cell can also store analog data. ^ It has been revealed in the literature that the progressive collapse of ultra-thin oxide layers is related to the limits of the scalability of the dielectric layer used for the gate of the electro-crystal. Such as

Hosoi et al. "A New Model of Time Evolution of Gate

Leakage Current after Soft Breakdown in Ultra-Thin Jake

Oxides,” IEDM, 2002; Wang et al. “Negative Substrate Bias

Enhanced Breakdown Hardness in Ultra-Thin Oxide pMOSFETs,’’ 41st Annual International Reliability Physics 1273

Symposium, Dallas, Texas 2003; and Under et al., "Grower and Scaling of Oxide Conduction after Breakdown,,, 41st

Annual International Reliability Physics Symposium, Dallas Texas 2003. The phenomenon of progressive collapse is expressed in the literature of Hosoi et al. as "Soft breakdown", which is expressed in the literature of Wang et al. as a "degressive way". The literature of Linder et al. discloses that the progressive collapse characteristics of ultra-thin oxide layers are characterized by "degradatiation rate" which is determined by the applied voltage, the thickness of the oxide layer, the doped region of the substrate, and the length of the channel. In this fortune, the progressive collapse phenomenon is based on the establishment of a deductible resistance value in the single-memory cell structure. As a result, the cell structure can be made compacter and can be easily fabricated using standard CMOS processes with low voltage operation. ^ 疋 疋 'An embodiment of the present invention provides a memory cell comprising a first electrode two: an electrode and a material layer between the two electrodes. Responsibility is caused by stress, for example, the voltage is crossed across the material: Layer: The reality of the invention _ the ship is lightly crossed over # 特^丄, volts. In some embodiments, the process i if "adds a positive voltage to the first electrode and applies a -negative voltage to the ^ electrode" which causes the absolute value of the positive negative voltage to be less than 2 volts to form a memory cell. The manufacturing method comprises a layer of material on the substrate, and the oil is formed on the electrode (the inter_electrode). The ship of the simple material has the characteristic of progressively changing corresponding to the stress of Ι2736α〇twf.doc/006. Then, forming a second 2° first electrode on the inter-electrode material layer is formed by providing a substrate, then implanting an n-type or a-type, and forming a conductive region in the substrate. The first electrode may also be formed on the substrate by a growth or deposition layer or a plurality of layers of conductor layers. The interelectrode material layer may be formed on the first electrode by using a layer of grown or deposited material. In the embodiment, The material of the electrode layer is a dioxotomy or oxynitride formed by a thermal growth process on an electrode formed by doping the wire. The second electrode is used in the inter-electrode material layer in the practical example of the present invention. Growing or depositing one or more layers of conductor The present invention provides a method for manufacturing a seed, comprising the steps of: forming a plurality of first wires on a substrate, the first turns extending in parallel in a first direction; forming a plurality of first wires on the first wires And - the direction perpendicular to one of the second directions extending in parallel; and; the parent array; forming an inter-electrode layer between the first wire and the second wire - the electrical layer is characterized by progressive stress Changing characteristics, forming memory cells in the intersecting regions; and forming circuits on the substrate to supply stress and sensing characteristics of the memory cells. In an embodiment of the invention, such as shallow trench isolation processes or cos isolation processes are A plurality of first-wires are formed with trenches filled with dielectric material 1273604: twf.doc/〇〇6 $. Thus, an isolation structure is formed between the memory columns. Formed before the wire. Then, a plurality of the -f lines are formed in the region of the trench, for example, by doping the semiconductor base wire. ^Implementation is made after the deposited wire is finer than the first wire layer. In this case In the step of forming a plurality of trenches, the material layer is divided into a plurality of wires. In one embodiment of the invention, the memory cells are formed by the following steps: 撼: -7 kinsin doped f to form the first conductive a conductive diffusion region of the type; forming a oxidized stone layer on the conductive diffusion region, the thickness of the oxidized stone layer being less than 15 angstroms; and forming a polycrystalline polycrystalline stone having a second conductivity type on the oxidized stone layer In the case of the material selected by the process of the second wire and the inter-electrode material layer and the thickness of the material used, the ultra-thin layer used in the invention includes oxygen cutting, nitrogen oxidizing dream and undoped Oxidation dreams 'the thickness of the first and second conductors; in another embodiment, it has a thickness of less than 15 angstroms between the first guides g , . _ Oxygen cleavage or its degree of characterization in the lower saki has a characteristic change and the memory - too = the ability to progressively change the amount according to stylization and sensing characteristics. The material of the ultra-thin layer of the bright layer includes nitrogen cut, such as oxygen cut nitrogen nitride, multi-layer stack structure of 4 layers of =(10)Q stack, oxidized material such as Al2〇3, YTa2〇5, Hf〇2, ΥΑ, Ce〇 2, Ti〇 electricity,

HfS_, HfA10x, TaOxNy, Zr〇2, ZrSi ο 2 1χ y, 2 must be ix〇y, La2〇3, etc. tw twf.doc/006 can be used as the material of the above ultrathin layer of memory cells. The composition of the first electrode and the second electrode may vary depending on the environment in which the present invention is applied. In one embodiment of the invention, the first electrode includes a polysilicon layer and the second electrode includes a conductive diffusion region of the semiconductor substrate. In another embodiment, the polysilicon layer and the conductive diffusion region have opposite conductivity patterns to form a type of diode-like resistive memory cell. In another embodiment, the first electrode and the second electrode may comprise a conductor combination comprising a metal such as copper, aluminum, tungsten, titanium, an alloy, and combinations thereof, p-type and n-type polysilicon, p-type and n-type diffusion regions, Metal halides, semi-metals, and the like. In some embodiments, the material of the electrode comprises a material containing an element, and the material of the inter-electrode material layer between the electrodes comprises a compound of the same element. For example, the materials of the first and second electrodes include Shi Xi, such as amorphous stone, single crystal, polycrystalline germanium, metal telluride and the like, between the electrodes between the first electrode and the second electrode. The material layer includes a ruthenium-containing compound such as ruthenium oxide or nitriding. The present invention also provides an integrated circuit comprising the memory cell array as described above, which utilizes the surface of the dielectric layer to compensate for the memory cells, and uses the sensing circuit to sense the progressive collapse of the memory cells in the array. the amount. In the present embodiment, the amount of the mask is indicated by the change in the resistance of the memory cell. The octave is established in a single memory cell by multi-step changes in stylization and sensing characteristics. For example, in one embodiment, the stylized logic is operated and the _ bias is applied to the -selected & memory cells, and then the bias is determined to be the expected amount of progressive change. If it is confirmed that the operation has failed, then retry the voltage and confirm the operation and repeat the remainder until the memory cell is successful or the limit of the retry is reached. The sensing circuit of the embodiment of the invention includes a reference current source and a circuit for comparing the current from the memory cell with the current from the reference current source. In an embodiment for sensing a single memory cell multi-bit or multi-order characteristic progressive change, the sensing circuit can include a plurality of reference current sources, and the circuit is configured to compare the current from the memory cell with the plurality of reference current sources One or more reference currents. The present invention further provides a stylized method of memory cells, including supplying a stress to the inter-electrode material layer to cause a progressive change in the characteristics of the layer during programming. Because of the progressive changes in characteristics, multi-level programming can be achieved. This stylization can be applied to multiple programming a memory cell without the need for an erase operation, but can program multiple bits in a single memory cell, and Can be combined with multiple bits and multiple stylization. According to an embodiment of the invention, the process of supplying a stress to the memory cell during programming includes using a continuous current pulse and a confirmation step, which is described as follows: ^ Supplying a first programmed pulse to have a first pulse height and a pulse width of the memory cell; measuring whether the memory cell is programmed against the first stylized pulse; and, if not supplying a stylized retry pulse to the memory cell; measuring whether the memory cell corresponds to a programmatic retry a pulse is programmed; and, if it is not repeatedly supplied another stylized retry pulse to the memory cell and measuring whether the memory is programmed, the system measures the cell age The number of times of refinement or retries reaches a maximum value; wherein, the stylized retry pulses each have a pulse width and a pulse height, which are changed according to a mode in which at least one stylized retry pulse has the same mode as the other The stylized retry pulse of the towel has a different pulse width or pulse height. In an embodiment of the invention, the stylized method includes a confirmation step. This confirmation step includes generating a signal ', such as a reference current, which can represent the characteristic value in the selected memory cell. This signal is then compared to the reference signal to confirm the stylization of the expected data. In embodiments where a single S memory cell is programmed multiple times, the stylized method includes maintaining a record of the number of programmed cycles applied to the memory cell array using, for example, a state machine, other data store, or logic circuit configuration. The reference signal used in determining the step or sensing the memory data is selected from a plurality of reference signal sources corresponding to the plurality of stylized cycles, respectively, based on the number of programmed cycles executed. The invention allows the data stored in the memory cell column to be reset by simply changing the reference level, wherein the data stored in the memory cell column is set higher or lower than the reference bit by setting the characteristics of the memory cell in the array. The standard value is indicated. The above term "reset" refers to setting all memory cells to standard values, usually "0" for a single bit memory cell or "〇〇" for a binary bit memory cell, and so on. This method of resetting makes it possible to program the array multiple times to store one or more bits of data in a single memory cell. The program according to an embodiment of the present invention includes first changing the reference level by changing the reference level to the unit cell memory or changing the reference bit to the multi-bit _ so that all the memory cells in the array have Cell array 'This level is higher than the reference scale characteristic of Qian Qi, after the reset reference level is reset, so that the array can be stressed by the above-mentioned method by changing; select: = . Thus, the present invention performs a reset two = where the erase operation is designed to characterize the memory cells that have been sensed by applying stress to the cryptographic cell. Under this theory, the program finance method of the present invention is characterized by "* need to be erased". In some embodiments, a multi-bit is stored in a single memory cell, and the method of programming includes providing a value for the stylized to memory location data. The reference signal used in the confirmation step or sensing the multi-bit data in the memory cell is selected from a plurality of reference signals corresponding to a plurality of values for the multi-bit data. The present invention also provides an integrated circuit including a logic circuit such as a general purpose processor or a dedicated logic circuit, a high speed memory such as a static random access memory and a programmable resistor according to a progressive collapse caused by a dielectric layer as described above. PREM memory cell array. In some embodiments, the logic circuitry for the stylized memory cell array includes instructions executed by the on-board general purpose processor to make the above and other objects, features and advantages of the present invention more apparent. A preferred embodiment, in conjunction with the drawings, is described in detail below. [Embodiment] Ι 2736 〇 α__ Please refer to Figs. 1 to 36 for explaining a preferred embodiment of the present invention. Fig. 1 to Fig. 3 are diagrams showing the basic memory cell structure of the present invention. As shown in Fig. 1, the memory cell includes a conductor 10, a progressive collapse dielectric layer 11 and a conductor 12. The conductor 10 serves as a first electrode. The conductor 12 is used as a second electrode. The dielectric layer 11 has a thickness or structural characteristic such that it undergoes a progressive change in accordance with stress. Typical dielectric materials have progressive collapse characteristics that cause progressive changes in electrical resistance, including ultra-thin oxide layers, such as oxynitride having a thickness of less than about 20 angstroms, preferably less than about 15 angstroms. The method for forming bismuth oxynitride includes using a cerium oxide thermal growth process, and performing a nitridation reaction under exposure to NO or krypton 20 during or after the process, which may be performed together with a thermal oxidation process of a peripheral circuit region outside the memory cell array. . The dielectric layer 11 may also use other cerium oxide which has been subjected to a nitridation process or a non-nitridation process. The dielectric layer 11 may also include oxidation formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (pecvd), TEOSCVD, high density plasma chemical vapor deposition (HPCVD), or other processes.矽 or other materials. The material used for the dielectric layer 11 may also include oxides formed by sputtering, pulse vapor deposition (PVD), jet vapor deposition (JVD), atomic layer deposition (ALD). For various applicable deposition techniques, reference is made to R0ssnagel, S. Μ. et al., '·Ριόπι PVD to CVD to ALD for interconnects and related applications,丨' Interconnect Technology Conference, 2001· Proceedings of the IEEE 2001 International, 4- 6 June 2001

Page(s): 3- 5 ; Jelinek, M. et al., "Hybrid PLD technique 15 I2736ftQ twf.doc/006 for nitrogen rich CN, layers/1 Lasers and Electro-Optics Europe, 2000, Conference Digest 2000, Conference on 10-15 Sept 2000, Page(s): 1 ρρ· ; Wang, X, W· et al. ''Ultra-thin silicon nitride films on Si by jet vapor deposition,,, VLSI Technology, Systems, and Applications, 1995· Proceedings of Technical Papers” 1995 International Symposium pn, 3 1 May-2 June 1995, Page(s): 49-52· et al. In addition, other dielectrics with progressive collapse characteristics can be used in the present invention. Materials, including multilayer stacked dielectric layers such as yttria-tantalum nitride-yttria QNO or alumina, etc. Dielectric materials such as Al2〇3, YTa205, Hf02, Y2〇3, Ce02, Ti02, HfSixOy, HfSiON, HfA10x , TaOxNy,

Zr〇2, ZrSixOy 'La2〇3, etc. may also be used as the material of the dielectric layer 11 of the memory cell. The conductor 10 and the conductor 12 comprise a conductor material, but are not limited to metal, semi-metal or conductive doped semiconductors. The conductor 1 and the conductor 12 do not need to be composed of the same material, but it is preferable to use a material which has been prepared in the manufacturing process. Therefore, the material of the conductor and the conductor 12 can be doped semiconductor, such as p-type and n-type polysilicon, doped gallium arsenide, etc.; metal, such as Shao, copper, crane, titanium, group, etc.; semi-metal, such as Tiw, TiN Etc.; metal lithology, such as WSix, TiSix. Figure 2 is a pictorial representation - a preferred embodiment, including The first electrode I3 of the type polycrystalline stone, the progressive electrode layer composed of the nitrogen oxide (4) having a thickness of I5 Å, and the second electrode 15 composed of the n-type diffusion region of the semiconductor substrate. FIG. 3 is a view showing another preferred embodiment, including a first electrode 16 composed of a ^16 itwf.doc/006 type polycrystalline material, a bulk dielectric layer 7 and a p-type diffusion in a semiconductor substrate. The conductive electrode of the second electrode 18 formed by the region for forming the dopant used in the conductor (p-type or n-type) of the first electrode and the second electrode may be the same or different, and the selection may depend on Process convenience or different component design. Fig. 4 is a view showing the strict (four) collapse characteristics of the above-mentioned 25 angstrom thick oxynitride layer used by the conventional memory cells proposed by de Graaf et al. As shown in Fig. 4, after 35 seconds between the stresses, the stylized current suddenly rises from about 〇 to about 3 mA, indicating a serious breakdown of the dielectric layer. Referring to Fig. 5, the application of the dielectric layer of the present invention with progressive collapse characteristics will gradually increase with the stylization. Moreover, there are p ^ polycrystals; ^ 15 electrodes of the upper electrode and the n-type buried gas diffusion electrode are oxidized (4), when a voltage of 1.8 volts is applied to the upper electrode and the voltage of -υ volts to the lower electrode When stylized, the stylized time, from around $second to around 14=', the stylized current will be approximately linear from 丨 milliamperes: to I female. When the dice memory cell such as the dice is renewed, the voltage is applied, for example, to apply 13 volts to the upper electrode and 0 volt to the lower electrode. As shown in Figure 6, when the read voltage is 13 volts applied to the upper electrode and the volts to the lower electrode, the read current will be applied to the upper electrode with a voltage of 15 volts to the next 15 volts. The electrode is increased in the course of the process, and the time is increased. It can be seen from Fig. 6 that the read current is basically progressive, and when the stylized time is from about 15 seconds to about 15 sec, the current will rise from less than 1 microamperes to approximately 0.25 17 itwf.doc /006 milliamps. As shown in Fig. 6A, in the case where the reading voltage is the application of the i-pole and the volt-volt to the lower electrode, the magnitude of the voltage is applied to the voltage, and the age of the spine is applied with the different stylized application bar marking lines of the program (four). 2.5 volts increase and increase. 1st..,._ _ package to the main elementary line (upper electrode) disk-2 3 mate special electrical test read (upper electrode) and ^ bar mark _ secret plus 2.5 volts = pressure = 2 electrodes) and _ A voltage of 1.7 volts to the bit line (lower electrode). Article 4 The line meter does not apply a voltage of 2.5 volts to the word line (upper electrode) and the voltage of _14 to the bit line (lower electrode). It can be seen from Figure 6 that for different stylized f-pressure values, the read current is basically tiring and corresponds to the increase in the program time. The higher the test, the shorter the time interval required to reach the same resistance progressive change. The programmed voltage value is 4·8 volts (2.5 volts minus 2·3 volts) stylized 100 milliseconds (0 After 1 second, the resulting read current is about 95 microamps. For a stylized voltage value of 4.5 volts (2.5 volts minus -2 volts), the programming time takes 1 second. A read current of about 95 microamperes can be obtained. σ Fig. 7 is a diagram of the read current vs. stylized time relationship of Fig. 6 plus the data level start value and the reference current value. Thus, by setting the reference current Ref_l.l at 8 microamperes, stylizes data representing 1 bit into memory cells. In the memory cell programming operation, in order to store the data value equal to "L, it is necessary to apply low voltage stylized stress." About seconds. For the 18 12736 problem - store the data value equal to "〇" without applying any stylized stress. Figure 8 is a diagram of the read current vs. stylized time relationship of Figure 6 plus the data level start value and the reference current value for storing the binary data in a single memory cell. In order to store data values equal to "〇〇", no stylized stress is required. In order to store the data value equal to "01", it is necessary to apply a low voltage stylized stress for about 75 seconds. In order to store data values equal to "1", it is necessary to apply a low voltage stylized stress of about 11 sec. In order to store a data value equal to a wide 11", it is necessary to apply a low voltage stylized stress of about 15 sec. The reference current source is set for the purpose of sensing the data value. The reference current Ref-1.1 is set to 4 microamperes in this embodiment. The reference current Ref-1.2 is set to 12 microamperes in this embodiment. The reference current Ref-U is set to 21 microamperes in this embodiment. The data value can be detected by comparing the read current with the reference current. The second figure is the read current vs. stylized time relationship diagram of Figure 6 plus 2 data level starting values and test current values for storing four pairs of materials in a single-memory cell. As shown in Figure 9, the stylized time is set more closely with the reference current level in order to achieve single-cell multi-bit storage. When the difference between the time and the reference current can be used, a conventional sensing technique can be used, for example, a sensing technique that has been applied to the town level _ face to achieve a multi-bit storage such as a single self-concealed body. * Money bribery reading or single-memory cell, the programmable resistance of the cell is not required to erase the memory structure chart. This structure includes isolation trenches 30, 3b, 32, 33, - extending on a line perpendicular to the page. The lower electrode conductors 34, 35 extending in parallel lines are disposed between the isolation trenches (10), Μ, 3 ► twf.doc/006. The lower electrode conductors 34, 35, 36 are formed on the insulating substrate to be doped and diffused to form a semiconductor substrate. Ultrathin oxide layers 37, 38, 39 are formed on the lower electrode conductors 34, 35, 36. In one embodiment, the ultra-thin oxide layers 37, 38, 39 utilize a single deposition step to form a full film over the entire array area of the wafer. In another embodiment, the ultra-thin oxide layer is patterned to conform to the layout of the memory cells. The upper electrode conductor, including the conductor 40, covers the ultra-thin oxide layer 37, 38, %, including a plurality of wires that are perpendicular to the lower electrode conductor, and forms a memory cell where the two intersect. The lower electrode conductors 34, 35, 36 are one of the scale contact line and the word line. Similarly, the upper electrode conductor (e.g., conductor 40) is one of the word and bit lines of the array. Figure 11 is a cross-sectional view of the memory cell array structure similar to that shown in Fig. 1 'the upper electrode conductor 45 is composed of p-type polycrystal (4)', and the lower electrode conductor 46 is diffused by n-type buried structure. The formation of the well area. In some embodiments, the 11-type buried diffusion well region is formed in a deep η-type well region (not shown): a type of diffusion isolation well region for supplying a 贞 voltage to the lower electrode guide 11 In the structure, other components that are the same as those in FIG. 10 will not be described again. Figure 12 is a cross-sectional view of a memory cell array structure similar to that shown in Figure 12, in which the upper electrode conductor 47 is composed of n-type polycrystalline glaze, and the power-off is performed by a p-type buried diffusion well region. Composition. The "Medium" and the 1g___members shown in Fig. 12 are not described here. I3 Figure 7C The programmable resistor of the present invention does not need to erase the base of the memory cell 20 12736· twf.doc/006. The process includes forming a lower electrode conductor 5A, a lowering of the dielectric layer 51, the dielectric layer 51 having a low voltage, and a top electrode conductor 52 formed on the dielectric layer 51. Before the dielectric layer is formed, it is necessary to make the lower electrode conductor 50, especially the emulsion layer or other dielectric layer. For example, the conductor layer 'lower electrode conductor 5' includes the formation of the auxiliary S-positive I a nucleation layer or a crystalline layer. The lower electrode conductor may also include a row of electrons to prevent diffusion of the material to the dielectric layer to protect the progressive collapse dopant process that will occur, wherein the implanted n-type is then used in the lower-step region. The lower scale body 55 is formed. The dielectric layer 58 is characterized by a low electrical axis dielectric layer 58 and an electric layer. After that, a dielectric layer: 1 is formed on the dielectric layer: 1 by the p-type polysilicon. The process shown in the figure has a germanium conductor 2: a diffusion region of the semiconductor substrate 62 to form a lower electrode conductor 3 electric /:=, forming a second layer on the lower electrode guide 6°, = the electric layer 63 is low Electrical a has a characteristic electrical layer of progressive collapse ^ ^ Formation 之上 is composed of n-type polycrystalline slabs of upper electrode conductor 64 Figure 16 . Thai flowchart for producing electrically programmable structure, such as a column of ": note = + conductor base note gall, for example with a pole forming isolation trenches 101_10 _: =;:. In the second embodiment of the substrate, the formation of the 21 ►twf.doc/006 method is, for example, a shallow trench isolation process (STI). In another embodiment, the LOCOS oxidation process can also be used to form the isolation structure. Then, an N-type dopant 106 is implanted to form a buried diffusion region 107-110 between the isolation trenches 10M05. In some embodiments, a deep η-type well region is formed, followed by a p-type isolation well region in the deep η-type well region, and then an n-type buried diffusion region is formed in the p-type isolation well region. The deep η well zone and the ρ type isolation well zone are formed before or after the formation of the isolation trenches 101-105. After the formation of the n-type buried diffusion regions 107-110, ultra-thin dielectric layers 111-114 are formed on the surface of the n-type buried diffusion regions 107-110. In the present embodiment, the surface of the n-type buried diffusion region 107-110 in the single crystal germanium is a good surface which can form niobium oxynitride suitable for the memory cell. In other embodiments, the surface can also be treated to prepare a dielectric layer. * Thereafter, a p-type polysilicon 115 is deposited on the substrate 100, and then the p-type polysilicon 115 is patterned to form a word line perpendicularly intersecting the bit line formed by the n-type buried diffusion regions 107-110. Forming a diode-like programmable resistor at the intersection of the word line and the bit line does not require erasing the memory cell, which can be accessed using conventional word line and bit line coding structures. In an embodiment of the invention, the upper and lower electrodes respectively comprise a bit line and a portion of the word line' and the upper and lower electrodes are in contact with the word line and the bit line, respectively. In another embodiment, the upper and lower electrodes further comprise an additional layer of material in the intersection region, the material layers being in contact with the word lines and the bit lines, respectively. Figure 17 is a flow chart showing the manufacturing process of an array structure according to another embodiment of the present invention. The components are similar to those given in Figure 16. As shown in Fig. 17, 22 f.doc/006 No, a semiconductor substrate 100 is provided first. The array region is defined by lithography on the surface of the substrate 1 or the dopant is implanted on the surface of the substrate to form an n-type diffusion region 12 to form an isolation trench 122_126 in the substrate 1 to intercept the n-type diffusion. The region 121 is filled with a dielectric material to form a buried diffusion bit line 127_130. After this process, the manufacturing process is the same as the manufacturing process of Fig. 16 above. According to the manufacturing flow of FIG. 16 and FIG. 17, an array structure can be fabricated. The top view of the array structure is as shown in FIG. 18, and the array structure has buried diffusion bit lines 200-202 and polycrystalline characters. Line 2 〇Hong 205, and the two intersect perpendicularly to each other. The memory cells are formed in areas where the two intersect, such as the intersection area 206. Fig. 19 and Fig. 20 are schematic views showing the structure of the sensing circuit of the memory cell array of the present invention. In Fig. 19 and Fig. 2, the array 25 代表 represents a memory cell array which is composed of a plurality of word lines arranged horizontally in the drawing and a plurality of bit lines arranged vertically. The memory cell is a diode symbol to indicate that the diode-like private resistor manufactured by the processes of Figs. 16 to 18 does not need to erase the memory cell. One of the bit lines is connected to the data output line 251 using standard encoding techniques. The data output line 251 is coupled to current mode sense amplifiers 252-254, which are used to measure data stored in a single memory cell as shown in FIG. Each current mode sense amplifier is connected to a reference current source. Thus, current mode sense amplifier 252 is coupled to a reference current source that supplies reference current Ref-L3. The current mode sense amplifier 253 is connected to a reference current source that supplies a reference current Ref_1.2. The current mode sense amplifier 254 is connected to 23 I2736i) 4Q twf.doc/006 to the reference current source supplying the reference current Ref_1. The output of the sense amplifier is then decoded on conductors 255-257 to calculate the value of the two bits stored in the selected memory cell. Figure 20 is a diagram showing the structure of a sensing circuit of another memory cell array of the present invention. Data output line 251 from array 250 is coupled to a single current mode sense amplifier 260. The reference current supplied to the sense amplifier on conductor 265 is selected by switches 261-263 which are respectively coupled to reference current sources supplying reference currents Ref-1.3, Ref-1.2, Ref-l.l. In other embodiments, digital sense amplifiers are not used, and data stored in the memory cells are sent out as analog output. Figure 21 is a block diagram showing the simple composition of a memory element that uses a programmable resistor without erasing the memory cell pREM array 270. The memory elements include a row decoder 271 and a column decoder 272, and a row decoder 271 and a column decoder 272 are connected to the address bus 273. The supply voltage from voltage source 275 for reading and programming operations is supplied to selected memory cells in the array via column decoder 272 and row decoder 271. The sense amplifier and input data structure 276 is coupled to the output of column decoder 272, input data bus 280 and output data bus 281. Each component that is connected to the stylized state device 277 is connected to the e-memory component. The state device can be executed by dedicated logic, a programmable logic array structure, a general purpose processor execution instruction, or a combination of these. As described above, the programmable resistor does not need to erase the memory cell array and can also be used to store multi-bit data in a single memory cell. In other embodiments, such an array of cells is suitable for multiple stylized cycles. Referring to Figures 22 through 24 ltwf.doc/006, Figure 25, a first stylized loop is executed to set a reference current for sensing a single bit at level Ref_1 (as shown in Figure 22). A second stylized loop is executed to set a reference current for sensing a single bit at level Ref_2 (as shown in Figure 23). A third stylized loop is executed to set a reference current for sensing a single bit at level Ref_3 (as shown in Figure 24). A fourth stylized loop is executed to set a reference current for sensing a single bit at level Ref_4 (as shown in Figure 25). The number of memory cells is programmed for a particular execution. This number is determined by the ability to reliably change the number of resistors that are progressively changed, and the level of current that can be clearly distinguished when accessing the memory. The read and stylized status device (shown as reference numeral 277 in Figure 21) is set to find the number of programmed cycles to be executed so that the appropriate reference current can be supplied to the sensing circuit. Figure 26 is a basic stylization rule for the programmable resistor of the present invention without erasing the memory cell. For the first stylized cycle 3, a first current value for sensing and verification is set (block 301). Then, a stress/stylization operation is performed to induce a progressive collapse amount so that the programmed memory cell can generate an output current greater than the first reference current value when reading (block 3 〇 2). In another embodiment, a stress is applied during the staging operation, and a continuous short pulse is used to gradually cause a progressive change in the resistance, such as a wavelength and/or voltage level that may change, or a fixed wavelength and The voltage level makes the memory cell characteristics have a variety of progressive collapse control totals. Then, the assertion and insertion are performed to determine the successful stylization (block 303). If the confirmation fails, then the following stress pulse retry the stress stylization operation. If the validation is successful, the first stylized loop is completed (block 304). As shown in Fig. 26, 25 ltwf.doc/006 can also use the same basic program as long as the progressive reference current is set, the second stylized loop 31〇, the third stylized loop 320, the fourth stylized loop 320, and the like. To execute. Three typical stylized operations are useful in which successive pulses are applied to establish a selected progressive change in memory cell characteristics, and each pulse is executed by a program rule, wherein the retry rule includes ··, ( 1) A confirmation step to measure whether the selected level is reached, if the rush is supplied with equal pulse voltage and equal pulse length (2) in each cycle - a confirmation step to measure whether the selected level is reached, if Otherwise, a pulse having an increased pulse voltage of the pulse length of the pulse is supplied in the mother-in-one cycle. 〃 (3)—Confirmation step to measure whether the selected position is reached. If no, the pulse with the increased pulse length of the pulse voltage is supplied in the parent-continuous cycle. And (4) a confirmation step to measure whether the selected level is reached, and if no, a pulse is supplied in the successive cycle, the pulse being during one or more steps of the continuous successive cycle One or both of the pulse width and the pulse length will change. In a preferred embodiment according to the structure shown in Fig. 2, the stylization program includes a fixed n-type diffusion electrode at a voltage of about -2 volts, and a p-type multi= 矽 electrode stepwise application of about 5 volts to about 2 volts. The voltage is applied at a fixed pulse width (eg, lms or i〇ms) at a voltage of 1 volt at each step, using a confirmation step between each pulse, and when 26 rf.doc/006 memory cells pass Stop after confirming the steps. In another constant voltage operation that is not structured according to Fig. 2, the stylization procedure includes fixing the voltage of the n-type diffusion electrode at about -2 volts, and applying a voltage of about 2 volts to the p-type polysilicon electrode to supply an equal pulse height. And supplying a pulse having an equal pulse width (for example, lms or l〇ms), using a confirmation step between each pulse, and stopping when the memory cell passes the confirmation step. Of course, the pulse height and pulse width can vary depending on the needs of the particular system. The programmable resistor of the present invention does not need to erase the memory cells to exhibit excellent program disturb and read performance. The performance of stylized interference can be explained by referring to Figures 27a to 27D. Figure 27A shows a schematic view of the array portion showing the word lines 400-403 and the bit lines 410-413. The memory cell A in the interleaved region between the word line 401 and the bit line 411 is applied by applying a voltage of 18 volts to the electrode on the word line 401 and applying a voltage of volts to the electrode on the bit line 411. Stylized. The memory cell B in the interleaved region of the word line 4〇1 and the adjacent bit line 412 receives a voltage of 18 volts from the word line, but the bit line is grounded. The memory cell c in the interleaved region between the bit line 411 and the adjacent word line 402 receives a voltage of _15 volts from the bit line, but the word line is grounded. Figure 27B shows the selected memory cell a, wherein the upper electrode 42 is composed of p-type polysilicon, the lower electrode 421 is composed of an n-type buried diffusion (or well) region, and the inter-electrode dielectric layer 422 is composed of 15 It is composed of arsenic oxynitride. A stylized potential of around 3. 3 volts across the two electrodes contributes to a bias mode for the Ρ_η junction of the component, the absolute value of the supply voltage is less than 2 volts, and 27 12736 QAtwf.doc/006 causes a progressive reduction in resistance across the two electrodes, This results in a progressive increase in read current as shown in Figure 6. Figure 27C shows the unselected memory cell C, wherein the upper electrode 423 is composed of P-type polysilicon, the lower electrode 424 is composed of an n-type buried diffusion (or well) region, and the inter-electrode dielectric layer 425 is composed of 15 It is composed of arsenic oxynitride. A voltage of -L5 volts is received from the bit line, but the word line is grounded. The ρ-η junction of the component is in a reverse bias mode. Figure 27D shows the unselected memory cell β, wherein the upper electrode 426 is composed of erbium-type polysilicon, the lower electrode 427 is composed of an n-type buried diffusion (or well) region, and the inter-electrode dielectric layer 428 is composed of 15 It is composed of arsenic oxynitride. A voltage of 1·8 volts is received from the word line, but the bit line is grounded. Figure 28 shows that the bias voltage applied to the memory cell β causes the memory cell to still have a low stylized current after 10,000 seconds of stylized stress. Figure 29 shows the application of a bias voltage such as memory cell c, so that the programmed current of the memory cell after 10,000 seconds of stylized stress is still very low. And 'the stylized interference is not seen from the scale of the graph. Diagrams 30 to 30D are diagrams of the memory cell array read and read interference states of the present invention. The readability of the programmable resistor of the present invention without erasing the memory cell can be explained with reference to Figs. 30 to 30D. Figure 30 shows a schematic diagram of the array portion Illustrating the word line 5〇〇-5〇3 and the bit line 5〇4-5〇7. The memory cell a in the interleaved region between the word line 502 and the bit line 505 is applied by applying a voltage of 1·3 volt to the electrode on the word line 5〇2, and grounding the electrode on the bit line 507. Read. The memory cell Bi in the interleaved region between the word line 5〇2 and the adjacent bit 28 12736· twf.doc/006 line 506 receives a voltage of ι·3 volt from the word line, but the bit line is set in a The suppression voltage is around 13 volts. The memory cell 2 in the interleaved area between the word line 503 and the adjacent bit line 5〇5 receives the voltage of the volts from the word line and receives the ground potential from the bit line. The memory cell C in the interleaved region between the bit line 506 and the adjacent word line 5〇3 receives the ground potential from the word line, and receives a suppression voltage of about 13 volts from the bit line. The 30th panel shows the selected memory cell, wherein the upper electrode 52 is composed of p-type polycrystalline asmatte, and the lower electrode 521 is composed of an n-type buried diffusion (or well) region, and the interelectrode dielectric layer 522 It is composed of 15 angstroms of arsenic oxide. In the memory cell as shown in Fig. 30, the dielectric layer is programmed to a low resistance state. A read potential of about 1/3 volts across the two electrodes contributes to a bias mode for the pn-n junction of the component, while inducing a current that can be sensed in the component. Figure 30C shows the selected memory cell, wherein the upper electrode 523 is composed of p-type polysilicon and the lower electrode 524 is composed of an n-type buried diffusion (or well) region. The interelectrode dielectric layer 525 is 15 angstroms. Nitrous oxide is formed by the evening. In the memory cell as shown in Fig. 30C, the dielectric layer is not programmed to a low resistance state. A read potential of around L3 volts across the two electrodes into a bias mode for the pn-n junction of the component, but induces a current in the component. , ' ^ Figure 30D shows the unselected memory cells in a stylized state, where the upper electrode 527 is composed of p-type polycrystalline shi, and the lower electrode seems to be composed of an η-type buried diffusion (or well) region. The inter-electrode dielectric layer 529 is composed of 29 Ι27360β^15 Å of arsenic oxynitride. The lower electrode receives a suppression bias of about 3 volts, and the upper electrode ground ◊ is in the reverse bias mode for the ρ-η junction of the element, and there is substantially no current. Similarly, as in the 30th, neither the memory cell 2 nor the memory cell C generate current, whether it is, a programmed low resistance state or an unprogrammed high resistance state. Figure 31 is a plot of read current vs. gate voltage, where mark line 550 represents a stylized memory cell and line 551 represents an unprogrammed memory cell ("unused"). As shown, when the memory cell is reverse biased (Vg < 〇), there is substantially no current. Before the bias state, Vg is less than one tenth of a volt, with a small amount of current in both the private and unprogrammed memory cells. However, in this embodiment, Vg is about 13 volts (line 552), and the programmed singular cells show a higher current than the unprogrammed memory cells. Fig. 32 shows the durability of the memory cell of the present invention. For stylized memory cells (markers 56〇 and 561) and unprogrammed memory cells (marker line 562) at different stylized levels, the read current remains close to a fixed value for long read times. . Moreover, as shown in Fig. 33, the data retention characteristics are also good. In the case of long-term warm baking, the read current remains close to a fixed value for the stylized memory cells (markers 565 and 566) and unprogrammed memory cells (marker 567) with different stylized levels. . Because the memory cell of the present invention has good stability, durability and retention, the memory cell can be programmed multiple times to be applied to a memory cell array of a single memory cell. Figure 34 is the diagram of the read current vs. stylized time in Figure 6, plus the data for the single memory cell binary storage I2736IAQ itwf.doc/006 ^ quasi-start value and reference current, ^ can also support The reference current values of the embodiment of the f-stylized, single-memory multi-bits of the present invention are not considered. In the first cycle, it is not necessary to apply any stylized voltage (stress) in order to store the value equal to "00". In order to store the value of the material equal to οι", it is necessary to apply a low voltage stylized voltage (stress) for about 25 seconds. The storage is equal to the "1G" (four) material value and the low voltage programming voltage (stress) needs to be applied for about 35 seconds. In order to store the data value equal to "u", it is necessary to apply a low voltage stylized voltage (stress (4) seconds or so. The reference current source is set for the purpose of sensing the data value. The reference current is not determined in this example. 1 〇 microamperes. The reference electric current, flow Ref_12 is 22 microamperes in the present embodiment. The reference current RefL1.3 is set to 35 microamperes in this embodiment. By comparing the read money with the reference f current, The data value can be detected. For the second stylized cycle, the data value can be detected by comparing the read current with the reference currents Ref_2j, Ref-2; 2, Ref-2 3. For the third stylization The loop can detect the data value by comparing the read current with the reference currents Ref-3·:, Ref-3.2, and Ref_3.3. Figures 35 and 36 show the programmable resistor of the present invention. There is no need to erase the embodiment of the "SyStein On a Chip (SOC)". The process of programmable resistors without the need to erase the memory cell (PREM) is completely compatible with the standard complementary metal oxide semiconductor (CM). 〇s) process compatibility, in the embodiment only need to add a mask, so It is suitable for the production of tight non-volatile memory in SOC products. For the p-type polycrystalline upper electrode 31 Ι 2736βα twf.doc/006 and the η+ type buried diffusion lower electrode, the additional H-structure only needs to be increased by one. , Beb (four) cover 'for the η + type buried step, while other STI process, dielectric sound expansion (four) of the implant stone (four) accounted for 0 u ▲ Dianguang chemical formation process and P + type polycrystalline The formation process of the CMOS structure is achieved by the Xiacheng system. The low voltage operation makes this kind of discussion low; ^ Bu == A good choice. A low power %楗 to the integrated circuit drawn in Figure 35 Array 601, logic circuit 6〇3, such as dedicated or known gate array logic circuit, and static random access memory ^M) 602 4REM array can be used to store more & For example, the information can be (4) gate _ _ _ _ (four) program specifications. Figure 36, which can be used to store logic circuitry's operations, is an embodiment of another system wafer of the present invention. The integrated circuit drawn in Fig. 36 includes programmable residuals, with (pREM) array 7 (U, logic circuit 7G3 such as dedicated logic circuit or programmable gate array logic circuit, static random access memory (SRAM) And the general purpose processor 704. The PREM array 701 can be used to store the deduction program executed by the general purpose processor 7〇4, and is stored by the external controller in the SRAM7〇2 or from the PREM array 701 to the SRAM 7〇2. The instructions can be supplied to the processor and executed by the processor to control the stylization of the pREM array 7.1. In summary, the present invention provides a program called pREM (Programmable Resistor With Erase-less 32) 1273· twf.doc/006

Memory)) A non-volatile memory whose electrical properties change between stresses due to stress. In one embodiment, the PREM memory cell has a P+ type polycrystalline slab gate, an ultrathin oxide layer, and an n+ type diffusion region, wherein progressive collapse using an ultrathin oxide layer is characteristic of data storage. pREM components can be fully compatible with CMOS processes, multi-time programming, multi-level memory (multi-level 11), etc. Logic circuits, S-discussion and non-swing == = The integration of the SOC is not good. The memory cell data storage performance is not good. And the memory cell is not detected. The stylized interference phenomenon takes the interference phenomenon. Although the present invention has been disclosed in the preferred embodiment, the second Anyone skilled in the art will be able to make some changes and refinements without departing from the spirit of the present invention. Therefore, the protection of the hair of the month is defined by the scope of the patent application attached [simplified description] Memory The programmable voltage limit imr diode of the progressive collapse dielectric layer of the present invention can be programmed to be electrically-remembered == the 4-layered diode of the pole-like resistor has a progressive crash dielectric. Figure 4 is deGraaf The catastrophic 33 >c/006 crash behavior diagram of the dielectric layer is shown in Figure 5. Figure 5 is a stylized current vs. stylized time diagram of the progressive crash memory cell in Figure 2. Figure 6 2 picture of progressive crash memory cell reading The flow-to-stylized time relationship diagram. Figure 6A is a diagram showing the four types of progressive crash memory cells in Fig. 2 with four different stylized, voltage-valued read current versus stylized time relationships. Figure 7 is a diagram of the application of the present invention. A reference current value Ref-U relationship diagram for measuring data stored in a memory cell. One = 8 Figure 疋 The present invention is applicable to measuring a reference current value relationship diagram of a two-bit material in a memory cell. Figure 9 is a diagram showing the relationship between the reference current values of the present invention for measuring the data stored in the memory cells. The first diagram is a basic array structure diagram of the memory cell array of the present invention. Fig. 12 is a basic array structure diagram of an array of memory cells shown in Fig. 2. Fig. 13 is a basic array structure of an array of memory cells of the present invention. Fig. 14 is a basic manufacturing flow chart of the memory cell shown in Fig. 2 of the present invention. Fig. 5 is a basic manufacturing flow chart of the memory cell shown in Fig. 3 of the present invention. Fig. 16 is a flowchart of the present invention. The basic structure of the array structure shown in Figure 11 34 ltwf.doc/006 Flowchart. A base Figure 17 is a manufacturing flow chart of the array shown in the first embodiment of the present invention. Figure 17 is a top view of the array structure manufactured by the manufacturing process. 19 is the Ling Wan of the present invention|Cong μ

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 18 is a view showing the sixteenth, seventeenth and twentyth aspects of the present invention in accordance with the present invention. Composition Figure 21 Figure 22 is a diagram of a reference current level relationship for sensing a bit of metadata after the first stylization of the multi-stylized embodiment of the present invention. > Fig. 23 is a diagram showing a reference current level relationship for sensing a bit of metadata after the second stylization of the multiple stylized embodiment of the present invention. Figure 24 is a diagram of a reference current level relationship for sensing a bit of metadata after a third stylization of the multiple stylized embodiment of the present invention. Figure 25 is a diagram showing the reference current level relationship for sensing a bit of metadata after the fourth stylization of the multiple stylized embodiment of the present invention. Figure 26 is a diagram of a plurality of stylized patterns of the present invention. Figures 27A through 27D are diagrams showing the stylized and stylized interference states of the memory cell array of the present invention. Fig. 28 is a diagram showing the stylized interference state of unselected memory cells shown in Fig. 27C of Figs. 27A to 27D. Fig. 29 is a diagram showing the stylized interference state of unselected memory cells of 35 itwf.doc/006 shown in Fig. 27D to Fig. 27D of Fig. 27A to Fig. 27D. Fig. 30A to Fig. 30D are diagrams showing the state of reading and reading interference of the memory cell array of the present invention.

Figure 31 is a graph showing the relationship between the read current and the gate voltage of the selected unprogrammed memory cell in the selected memory cell and the 30B and 30C. >

Figure 32 is a graph showing the read current versus read time for the selected memory cells and the unselected unprogrammed memory cells shown in Figure 30B and Figure 30C.

Figure 33 is a graph showing the read current versus hold time for selecting a non-stylized memory cell as shown in Figure 30B and Figure 3C. Figure 34 is a schematic diagram of reference current values for an embodiment of the multi-programmed, single memory cell multi-bit of the present invention. Fig. 35 is a block diagram showing the recording circuit of the present invention having a programmable resistor without erasing a memory cell array, a dedicated logic circuit, and a static random access memory. Figure 36 is a block diagram showing the recording circuit of the present invention having a programmable resistor without erasing the memory cell array, a general purpose processor, a dedicated logic circuit, and a static random access memory. ^ [Illustration description] 10, 12, 40 ·• Conductor 1 Bu 14, 17, 51, 58, 63: Dielectric layer 13, 16: First electrode 36 Ι 2736 〇 α twf. doc / 006 15, 18: Second electrode 30, 31, 32, 33, 100, 1 (U, 102, 103, 104, 105, 122, 123, 124, 125, 126: isolation trenches 34, 35, 36, 46, 48, 50, 55 60: lower electrode conductors 37, 38, 39: ultra-thin oxide layers 45, 47, 52, 59, 64: upper electrode conductors > 56, 61, 106, 120: dopants 57, 62, 100: substrate 107, 108, 119, 110: buried diffusion regions 111, 112, 113, 114: ultra-thin dielectric layer 115: polysilicon 121: diffusion region, 127, 128, 129, 130, 200, 201, 202: buried diffusion Bit lines 203, 204, 205: polycrystalline word line 206: intersecting areas 250, 270, 601, 701: PREM array 251: data output lines 252, 253, 254, 260: sense amplifiers 255, 256, 257, 265 : Wires 261, 263, 263: Switch 271: Row Decoder 272: Column Decoder 273: Address Bus 37 37736 twf.doc/006 275: Voltage Source 276: Sense Amplifier and Input Data Structure 277: Read and stylized state loading 280: input data bus 281: output data bus 300, 301, 302, 303, 304, 310, 320, 330 blocks 400, 401, 402, 403, 500, 5 (U, 502, 503: word line 410 411, 412, 413, 504, 505, 506, 507: bit lines 420, 423, 426, 520, 523, 527 · upper electrodes 421, 424, 427, 521, 524, 528: lower electrodes 422, 425 428, 522, 525, 529: inter-electrode dielectric layers 550, 551, 560, 56 562, 565, 566, 567: marking line 552: line ·.

602, 702: SRAM 603, 703: logic circuit 704: processor A, B, B, B2, C: memory cell 38

Claims (1)

1273600 11418twfl.doc/006 Amendment to the scope of Patent No. 93121700........................... P Year/Month Day Repair (More) Positive replacement page 94.11.30 X. Patent application scope: 1. An integrated circuit, including: - memory cell _, memory of the touch &amp; electrode, a second electrode, a thunder &quot; In the interlayer layer, the inter-electrode material layer is disposed on the 一-electrode pin Γ1, and the inter-electrode material layer has a C-force and a change characteristic; One of the memory cells, the logic circuit, generates the memory cells in the memory cell array by generating the I force; and the sensing circuit is responsible for the progressive change in the memory cell characteristics. The second layer of the cell in which the electricity is the electricity, wherein the electricity is the electricity therein, wherein the electricity is the electricity therein. The integrated circuit material layer of the integrated circuit of claim 1 includes a thickness of less than 20 angstroms. Yttrium oxide. 3. The integrated circuit layer according to item 1 of the patent application scope includes an arsenic oxynitride having a thickness of less than 20 angstroms. 4. The integrated circuit layer as described in claim i of the scope of the patent includes an oxide stone having a thickness of less than 15 angstroms. 5. The integrated circuit layer according to item 1 of the patent application scope includes an inter-electrode material layer having a thickness of less than 15 angstroms. 6. The integrated circuit layer as described in claim i of the scope of the patent includes an ultra-thin material. 7. The integrated body as described in claim 1 of the patent scope. The circuit inter-electrode material layer comprises nitride rock. &amp;, as described in the patent scope, the inter-electrode material layer is selected from the group consisting of Al2〇3, YTa2〇5, Hf〇2, Y2〇3:C 39 1273, _ 94.11, 30 No. 93121700 Patent scope amendments to at least one of the groups of Ding 1, 2, HfSix〇y, Qingyi N, Zu 1〇 and 1&amp; 2〇3, xy, Zr〇2, ZrSix〇y, 9· The logic circuit ii of the memory cells is programmed to be sufficient for the memory cells to be sufficient; the characteristic of the layer produces a progressive change. The logic circuit of the inter-electrode material 10. The program of the memory cells as described in claim 1 includes: - wherein the voltage is applied across the first electrode of the memory cells - The programmed time, the stylized voltage is less than 5 volts. /, the two electrodes of the two brothers, please the integrated circuit described in the i-th patent of the patent range, the logic circuit of the memory cells includes -, and the voltage is drawn to the first electrode of the memory cells: Supply = voltage to e hai some of the memory cells of the second _ - period, ;:: The absolute value of the voltage and the negative stylized voltage are less than 2 volts.王^电a as in the application of the scope of the patent range i, according to item i, Α中二: Γ, the second electrode comprises - semiconductor substrate 13. As described in the scope of claim i a circuit in which the -electrode comprises a material layer containing an element, and (4) a second layer comprising a layer containing an element comprising a chemical element containing the element. The basin-electrode comprises a plurality of layers having a first conductivity type, the second electrode being included in the semiconductor substrate having a second conductivity type - conductive diffusion 40 127361 .doc/006 94.11.30 No. 93121700 The scope is revised in this area. 15. The integrated circuit of claim 1, wherein the first electrode comprises a p-type polysilicon layer, and the second electrode comprises an n-type conductive diffusion region in a semiconductor substrate. 16. The integrated circuit of claim 1, wherein the first electrode comprises a semiconductor material having a first conductivity type, and the second electrode comprises a semiconductor material having a second conductivity type. 17. The integrated circuit of claim 1, wherein the first electrode comprises a first polycrystalline layer and the second electrode comprises a second polysilicon layer. 18. The integrated circuit of claim 1, wherein the first electrode comprises a metal layer, and the second electrode comprises a conductive diffusion region in a semiconductor substrate. 19. The integrated circuit of claim 1, wherein the first electrode comprises a metal layer and the second electrode comprises a polycrystalline layer. 20. The integrated circuit of claim 1, wherein the first electrode comprises a first metal layer and the second electrode comprises a second metal layer. 21. The integrated circuit of claim 1, wherein the sensing circuit includes a circuit for supplying a read voltage across the selected one of the memory cells selected in the array and the brother The two electrodes 'and sense this characteristic. 22. The integrated circuit of claim 1, wherein the sensing circuit comprises a circuit for supplying a read voltage of less than 2 volts across the first of the selected ones of the memory cells in the array An electrode and the second electrode, and sensing the characteristic. 41 I2736lQlQwfl.doc/006 Patent No. 9312Π00 Amendment 94.11.30 23·If the scope of the patent application is included, the circuit includes a circuit for supplying an integrated circuit of the first and second senses, wherein the memory cells of the sense The first two-two takes the voltage across the four levels selected in the array to represent the data of the _^ pole and the second electrode, and senses the characteristic. 24, as claimed in the patent scope. The item measurement circuit includes one way of "supply path, wherein the first electrode of the memory cells of the sense 蛊 / = 3⁄4 inverse % over the eight quantity gammas selected in the array represents the third electrode of the third position, jt Sensing the characteristic 25· The fourth measuring circuit of the patent scope includes a circuit, 77 integrated circuit, wherein the first reading electric house of the memory cells of the sense crosses the ten selected in the array The six magnitudes are in the table ^_ and the second electrode' and sense the characteristic 0, Λ 不 不 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 · · · · · · · · · · · · · · · · · · · · · · · · · · · The logic circuit of the cell is wrapped, in which the stress is used to select the cell, and the path is used to supply When a set amount is reached, such as ^ 疋 5 5 5 亥 亥 亥 5 5 5 5 5 5 5 5 5 5 5 5 亥 5 5 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥The integrated circuit of claim 1, the current source in the basin and a circuit, the circuit supplying - or a plurality of; the current from the selected memory cell - including the integrated circuit described in claim 1 of the patent scope, It is advisable to include a phase random access memory array and a logic circuit. The logic 42 !2736〇〇11418twfl.d〇c/006 94.ll·30 93〗 2] Taking the data stored in the memory cell array and the SRAM array. " 29. As described in claim 1, the integrated circuit, the package = state random access memory array and - Processor &lt;execution = access to the instructions stored in the memory cell array and the static random port: the data in the array. #括一静·』"申机二: The integrated circuit described in item 1 of the dry circumference, in which the package instruction includes a two-body array and a processor, and the processor &quot;^ accesses the memory array The logic circuit of the memory cell array and the static random cell array refers to: and is used to program the memory 31 memory cells, including: 曰7 a brother-electrode; a second electrode; - an inter-electrode material layer, the strip and the second electrode, the inter-ply material layer is disposed on the first electrode to change a characteristic. The inter-electrode material layer has a stress associated with a 32. The patent scope force includes, in addition to, the 忆 胞 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The memory cell described in #Item, wherein the electricity is 34. For example, the bismuth oxide layer of the patent application range includes the thickness of the small work, the memory cell of the fan, wherein the electricity, the arsenic oxyhydroxide. 43 1273600 94.11.30 11418twfl.doc/0〇6 Amendment of Patent Scope No. 931217 For example, in the patent application, the electrode includes a memory cell as described in item 31 of the thickness of less than 15 Å, and wherein the electricity 7: 丄 小于 小于 小于 小于 小于 。 。 。 。 。 。 。 。 。 。 。 。 。 The memory cell of the range *31, wherein the electrical material layer comprises a dielectric material. The memory cell described in item 31 of the circumference is (4) the inter-electrode material layer comprises an ultra-thin material. The memory cell of item 31, wherein the inter-electrode material layer comprises tantalum nitride. The memory cell described in the first paragraph of the patent, wherein the material layer is selected from the group consisting of Al2〇3 At least one of the groups of YTa2〇5, γ2〇3, (10), 1-2, HfSlxOy, HfSiON, HfA10x, Ta〇xNy, Zr〇2, ZrSixOy human La2〇3. The memory cell of claim 31, wherein the third electrode comprises a material layer containing an element, the second electrode comprises a material layer containing the element, and the inter-electrode material layer comprises a compound containing the element. _Please refer to the memory cell described in item 31 of the patent scope, wherein the oxygen Including a polycrystalline layer, the electrode is included in the semi-conducting I--the conductive diffusion region. And the soil is as described in claim 31, as in the memory cell described in claim 31, i The polar package is reduced by a polycrystalline layer of a first conductivity type, and (4) a second dielectric is coated on the semiconductor substrate, and has a conductive diffusion of a second conductivity type [πσ 〇 44 94.11.30 I2736lQL, oc/〇 The memory cell of claim 31, wherein the first electrode comprises a p-type polysilicon layer, and the second electrode comprises an n-type conductivity in a semiconductor substrate. Diffusion zone. 45. The memory cell of claim 31, wherein the first electrode comprises a semiconductor material having a first conductivity type and the second electrode comprises a semiconductor material having a second conductivity type. 46. The memory cell of claim 31, wherein the first electrode comprises a first polycrystalline layer and the second electrode comprises a second polycrystalline layer. 47. The memory cell of claim 31, wherein the first electrode comprises a metal layer, and the second electrode comprises a conductive diffusion region in a semiconductor substrate. 48. The memory cell of claim 31, wherein the first electrode comprises a metal layer and the second electrode comprises a polycrystalline layer. 49. The memory cell of claim 31, wherein the first electrode comprises a first metal layer and the second electrode comprises a second metal layer. 50. The memory cell of claim 31, wherein the progressive change of the characteristic is by supplying a positive stylized voltage to the first electrode and supplying a negative programmed voltage to the second electrode for a period of time The absolute value of the positive stylized voltage and the negative stylized voltage is less than 2 volts, respectively. 51. A memory cell, comprising: a first electrode; a second electrode; and an inter-electrode material layer. The inter-electrode material layer is disposed on the younger brother ^^45 1273600 H418twfl.d〇c/〇〇6 In the scope of the modification of the patent of No. 21700, the material between the electrode and the second electrode having a thickness of less than 15 angstroms is made less than 5 volts, and the second electrode is electrically driven to induce a progressive change of the resistance; And a memory cell comprising: a first electrode comprising a semiconductor having a first conductivity type; a second electrode comprising a semiconductor having a second conductivity type; and an inter-electrode material layer, the inter-electrode material layer comprising It is assumed that a gas layer having a thickness of less than 15 angstroms between the second electrodes causes a progressive change in resistance by causing a voltage of less than 5 volts to cross the first-electrode = 5 hai-d-pole. 53. An integrated circuit disposed on a single substrate comprises: (4) the memory cell array includes a plurality of rows and columns of U cells, each of the memory cells in the array including a first electrode, a pole and a material layer between the electrodes, wherein the material layer between the electrodes is disposed between the first electrode and the second electrode, and the material layer between the electrodes has a characteristic of changing in a second direction; the plurality of word lines are arranged in the knife In the memory cell array, the first electrode of the memory cells connected to each row in the memory cell array; a plurality of bit lines disposed in the memory cell array to connect the memories of the columns in the memory cell array The second electrode of the cell is configured to program a logic circuit of the memory cells, and connect the word lines to the bit lines, and program the selected memory cells by selecting the memory cell to generate the stress; And a sensing circuit connecting the bit lines to sense the progressiveness of the selected memory cell of the memory cell array in the memory cell array of 46 ^ 600 |l418twfl.doc/006 94.11.30 No. 9312 mo Change the amount. The second inter-electrode material layer includes an oxidized 2-night limb path having a thickness of less than 2 angstroms, wherein the 55. The inter-electrode material layer as described in claim 53 includes a thickness less than 2 〇 相 相 四 四 四 四 四 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 The inter-electrode material layer includes a nitrogen oxide having a thickness of less than angstroms. The 58. The inter-electrode material layer as described in claim 53 of the patent application includes an ultra-thin material, a circuit, wherein the application is 59. The inter-electrode material layer described in item 53 of the patent scope includes nitriding stones. ^The limb road, wherein the Τ1〇2, H_y, 〇Ν, HfA1〇x, Ta〇N 2, 〇3, Ce 〇2 And at least yr〇2, ZrSixOy 61 of the group of La2〇3. The logic circuit of the 53rd item of the patent application includes a circuit for supplying a stylized=turn, wherein the change is made. This characteristic of the material layer between the electrodes is generated. 62. Patent application The logic circuit of the 53rd item includes a Thunder Field, and a circuit for concentrating the heart and the heart, wherein the memory cell has enough time gates to materialize the power to the selected ones to make This characteristic of the inter-electrode material layer produces a change in the range of the patent scope of the invention, which is less than 5 volts. 63. The product described in claim 53 a circuit, wherein the logic circuit includes a circuit for supplying a normalized voltage to one of the word lines and supplying a negative programmed voltage to a bit line of the bit lines for a period of time, The absolute value of the positive stylized voltage and the negative stylized voltage are less than 2 volts, respectively. 64. The integrated circuit of claim 53, further comprising a negative voltage generator disposed in the substrate. 65. The integrated circuit of claim 53, wherein the word lines comprise polysilicon layers comprising respective conductive diffusion regions in a semiconductor substrate. 66. The integrated circuit of claim 53, wherein the first electrode comprises a material layer containing an element, and the second electrode comprises a material layer containing the element, the inter-electrode material layer comprising the element compound of. 67. The integrated circuit of claim 53, wherein the word suspension lines comprise a polysilicon layer having a first conductivity type, the bit lines comprising a second conductivity type in a semiconductor substrate Each conductive diffusion region of the state. 68. The integrated circuit of claim 53, wherein the word lines comprise p-type polysilicon layers, each of the n-type conductive diffusion regions in a semiconductor substrate. 69. The integrated circuit of claim 53, wherein the first electrode comprises a semiconductor material having a first conductivity type, the second battery 48 1273600 94.11.30 H418twfl.doc/〇〇6 table 121700 The patented range correction pole includes a semiconductor material having a second conductivity type. The integrated circuit of claim 53, wherein the electrode comprises a first-polycrystalline hard layer, and the second electrode comprises a second plurality of layers of the word The integrated circuit, wherein the layer of the plurality of lines includes respective conductive diffusion regions in a semiconductor substrate. In the W substrate, the sub-reads described in item % of the patent application include a metal layer, and the bit lines include a polycrystalline egg/, an integrated circuit described in item 53 of the 7-yuan range of the word, Wherein, the first layer includes a layer of surplus, and the bit lines comprise a metal layer. ^ In the patent range, the integral line of the word line is described, and the characteristic is sensed from the voltage line of the ^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ π, 目1 declares the integrated circuit described in the 53nd J patent range, 1 sense of 9: _ a circuit for supplying small-character line-word lines, and from these bit lines -: The characteristic is as follows: The sensing circuit of claim 53 includes a circuit W and a circuit, wherein the level is a four-dimensional memory of the facet. For example, please refer to the patent Fan Weibei, the integrated body 1 sense packet includes a circuit, a circuit, wherein the magnitude is expressed in three bits... Recalling the characteristics of the characteristics of the eight 49 12736 rules 'doc/ 006 No. 9312, Patent Revision No. 700.11.30, 78. The integrated sensing circuit according to item 53 of the cap patent scope includes a circuit for selecting from four, to represent four digits. The material of the M package senses the characteristic. The logic circuit of the cell as described in item % of the patent application includes "logic = road = two should - stress to - Shout the memory cell and confirm whether it is used to change the amount of arrival to a set value. If the A force makes the - segment of the characteristic sufficient 0f (four), the electrical system (4) = stress and confirmation operation change. This characteristic of the ray electrode material layer produces a progressive change. 80. The sensing circuit of the S3th sensing circuit includes a plurality of reference current source mussels::, where the voltage is taken to the selected memory cell, and the circuit is derived from the circuit. Supply one-time or a plurality of these reference current sources for comparison. 5 疋 疋 疋 疋 疋 疋 81 81 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 体 体= Array of random access memory arrays and processors, the process of crying = instructions, including instructions for accessing data stored in the array of memory cells and the static memory access memory array. 83. The integrated circuit of claim 53, wherein the gamma-static random access memory array and the processor further process the crying executable instructions, including storing the persimmon in the memory cell _ and the static g 50 12736 胤 gas 94.11.30 Patent No. 93,921,700 modifies the instructions for accessing data in the memory array by the local device, and the instructions included in the logic circuit of the memory array. 84. The method of manufacturing an integrated circuit, comprising: the following steps: forming a plurality of first wires on the substrate, the first directions extending in parallel; Forming a plurality of second wires on the first wires, the second wires extending in parallel in a second direction perpendicular to the first direction; and the second wires and the second wires a plurality of intersecting regions of the wire form an inter-electrode material layer, the inter-electrode material layer has a variability-characteristic, and in the intersecting regions, a shape is recorded (4), and a circuit is formed on the bottom of the cell. To supply the stress and to sense the manufacturing of the integrated circuit as described in the above-mentioned Patent No. 4 (4), wherein the material of the material layer between the electrodes includes an oxidation team having a thickness of less than 2 angstroms. Patent application scope 帛 84 The material of the material layer between the electrodes includes the thickness of the two methods of the special fiber (four) 84 items of the frequency only _ manufacturing square 41; the formation of the material layer between the electrodes includes the use of thermal oxidation method 51 12736 _006 94. Ll·30 No. 9312!7〇0 Patent scope revision 88. The method of claim 84, wherein the inter-electrode material layer cutting method comprises: 9:2: claiming the method for manufacturing an integrated circuit according to claim 84, wherein the electrode is The material; the outer layer: ^ - as in the patent application range 8 ==;; == method, 9 the formation method of the 2 electrode material layer includes the ruthenium plating method. Method of manufacturing, straight-cut red-frequency _ method of manufacturing method The package is exposed during or after the dioxo-second thermal oxidation method 94. As claimed in the 84th item 95. If the patent application scope is 84th, the emulsifying stone eve. The method wherein the inter-electrode material layer comprises a manufacturer having a thickness smaller than that of the road. 96. The method is further included in the manufacturing structure of the first-wire. A plurality of 97 are formed in the substrate, and the method of the method of claim 84 is further included in the manufacturing trench of the first-conductor circuit, and the dielectric material is filled in the trenches. . A plurality of 52 I2736lQQtwf are formed in the 5 hai substrate, and oc/006 sings 93121700 5 Tiger Patent Range Revision 94.13.30 98. For example, the 84th method of the patent application scope, which further includes: Cutting the substrate into the dielectric material to extend in parallel in the first direction; and the groove, the trenches, in the step of forming the first wires, doping the substrate to form a conductive diffusion region . Between the 4 ditch and the ditch 99. As described in claim 84 of the patent application scope, the circuit for supplying the stress includes the manufacturer's private voltage to the memory cells - sufficient phase supply - Progressive collapse of the material layer. The electrode between the electrodes K):: the party mentioned in claim 84: to: the voltage of the circuit pack for supplying the stress spans from the first wire and the second wire Sufficient time, the stylized voltage is less than 5 volts. ^ U) = Patent application No. 84 of the patent application scope - Positive: The circuit for supplying the stress includes - a circuit for supplying - negative Hi to the first conductor - the first selection conductor The absolute value of the '4 normalized voltage and the negatively stylized voltage is less than 2 volts, respectively, when the voltage is supplied to one of the second conductors. 1. The manufacture of an integrated circuit as described in claim 84, wherein the substrate comprises a semiconductor substrate, and the step of forming the first conductive springs includes patterning in the substrate And doping a conductive diffusion region 'and in the step of forming the second wires includes depositing and patterning 53 1273600 11418 twfl.doc / 〇〇 6 94.11.3 〇 (4) sub-number, the patent scope corrects the polycrystalline rafter Shape. 103. The method of claim 84, wherein the substrate comprises a semiconductor substrate, the step of forming a line in the form of a manufacturing line comprises: forming a conductive diffusion region in the substrate. And forming the first-child-conductive deposition and patterning the second conductivity type (four) = the first package 1 〇 4. The product _ as described in claim 84. a method, wherein the substrate comprises a semiconductor substrate, the step of fabricating, including patterning and doping regions in the substrate; and diffusing the n-type polycrystalline germanium in the step of forming the second wires . The method of claim 84, wherein the substrate comprises a semiconductor substrate, including: patterning and doping in the substrate in the step of manufacturing the line The first-conducting region, and the step of forming the second wires, electrically diffuse out of the metal strip.沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积4 product and pattern deposition and patterning of metal strips. The method of claim 84, wherein the method of claim 84, wherein the domain measurement circuit comprises: circuit manufacturing, the selected first wire and the second conductive read voltage cross the same The selected memory cell in the memory cell column, and senses the amount of the accumulated memory, 54 1273 boots __ Patent No. 93,921,700 patent scope revision 94.11.30, 108. If the patent application scope is 84 The integrated method, wherein the sensing circuit includes a circuit for supplying a small=?-reading electric-selective--the first-wire and the second second-breaking 3 to select the selected memory in the memory cell array ', i sensation = as in the manufacturing method of the integrated circuit described in claim 84, the steps of forming the first-wires in the eight steps and the formation and patterning in the formation of the line At least half of the gold = one of the things. The method of claim 7, wherein the material layer between the electrodes is selected from the group consisting of Al2〇3, peach, tear, plus 2, Cong, Cong reading, ancestor, Zr 〇2, at least one of the groups of ZrSix〇y and U2〇3, xy U1. A method for fabricating a memory cell, comprising the steps of: forming a first electrode; forming a first pole on the β-mesh a material layer, a material layer between the electrodes, having a characteristic of progressive change of Ik: stress; and forming a second electrode 0 on the inter-electrode material layer on the first electrode to eliminate the The manufacturing cell t of the memory cell, wherein the material of the material layer includes a oxidized oxide eve 0 method having a thickness of less than 20 angstroms, a manufacturing method of the memory cell described in the item 111, and a village material having a thickness of less than 20 A gas of oxygen 55 12736 (10) twfl .doc / 006 12736 (10) twfl .doc / 006 94.11.3 ° No. 93121700 patent scope to amend this fossil eve. 114. The method of manufacturing a memory cell according to the patent application scope of the invention, wherein the inter-electrode material layer comprises an oxidized stone having a thickness of less than 15 angstroms. 115. The method of manufacturing a memory cell according to the scope of the patent application (1), wherein the inter-electrode material layer comprises less oxynitride having a thickness of less than 15 angstroms. 116. The method of fabricating a memory cell according to claim ln, wherein the inter-electrode material layer is selected from the group consisting of Al2〇3, YTa2〇5, Hf〇2, Y2〇3, Ce02, Τι〇2, HfSix. At least one of the groups of 〇y, HfSiON, HfA10x, TaOxNy, Zr〇2, ZrSix〇y and hO3. , the method for manufacturing a memory cell as described in claim 1 (1), in the step of opening the first electrode of the first step, comprising doping a half of the reference substrate to form a conductive diffusion region; The lesser steps of forming the second electrodes include depositing polysilicon. The method for manufacturing the memory cell described in the patent application scope of the invention includes the doping of the first electrode and the doping of the first electrode to form the first conductive type. a diffusion zone; and a step of forming the plurality of steps includes depositing a polycrystalline spine having a second conductivity type. , soil 1 Gan 19 2: Ming, patent dry 11 111th household account of the production of the memory cell and the second, # into some of the Ang - electrode steps include the deposition of polycrystalline stone eve; division including sedimentary polycrystalline Shi Xi. The target substrate of the memory cell described in item 111 is formed to form a conductive diffusion electrode comprising doping-semiconducting:, and, in the formation of the second electrodes, 56 I2736P49stwfl, 〇c /〇06 94.11.30 Amendment to Patent Range No. 93121700 This step includes depositing metals. 121. The method of claim 1, wherein the step of forming a metal pole of the memory cell described in the first pole 2 comprises the step of depositing a metal crucible and forming the second electricity 122. The first method, wherein the step of forming the first electrode comprises the step of depositing and patterning one of the "half electrodes". The v. genus and the metal lithium compound are 123. Method, wherein the stress is supplied by the supply-positive process - the negatively stylized electric second electric electrode and the voltage and the negative stylized voltage are absolutely; two = 2: method two 24: "1 Fan Yuan The manufacturing method of the memory cell described in item 111 is the second step:: the electric current is straddled between the first electrode and the second electrode 125. As claimed in claim 111, the method of applying the stress It is produced by the manufacturing f of less than 5 volts and the second electrode-stage time. a method for manufacturing an electric house spanning the first electrode, the 126 memory cell, the printed conductor substrate comprising the following steps: σ k is formed on the + implant doped on the semiconductor substrate to form a conductive diffusion a region; a / a younger conductor is electrically formed on the conductive diffusion region to form an inter-electrode tantalum layer, the electrode material 57 I273_tw fl .doc / 006 I273_tw fl .doc / 006 94.11.30 Patent No. 93121700 Correcting that the layer has a progressive change in electrical resistance by causing a voltage of less than 5 volts across the inter-electrode material layer; and forming a doped semiconductor layer having a second conductivity type on the inter-electrode material layer. 127. A method of fabricating a memory cell formed on a substrate, comprising the steps of: implanting I on the germanium substrate to form a conductive diffusion region having a first conductivity type; A ruthenium oxide layer is formed on the conductive diffusion region, the ruthenium oxide layer having a thickness of less than 15 angstroms; and a doped polysilicon layer having a second conductivity type is formed on the ruthenium oxide layer. The manufacturer of the memory cell described in the 127 patent 巳 巳 巳 Γ Γ 帛 帛 帛 帛 帛 帛 氧化 氧化 氧化 氧化 氧化 氧化Or after exposure to 5 虱 虱 虱 in a nitrogen-containing environment. A stylized method of an electrode cell comprising a -first-order electrode-to-electrode material layer, the method comprising: supplying a stress to the inter-electrode material layer to induce a progressive change of the layer-characteristic . g 极 间 枓 方法 方法 Method: 3:. 2: 1~ Patentization of the memory cell described in item 129 (3) The γ-electrode material layer includes a dielectric material, which is a resistance. The method, the stylized/middle (four) interpolar material layer of the memory cell described in item 129 of the benefit range includes an ultrathin material. 58 127361 fl.doc/006 127361 fl.doc/006 94.11.30 Patent No. 93121700 Scope Correction This is a stylized method for the memory cell described in item 129 of the patent scope of the patent application, Includes a dioxide dioxide thickness of less than 2 angstroms. 133. A stylized method of a memory cell as described in the applicant's patent application. The layer of the material of the towel comprises an oxynitride having a thickness of less than % angstrom. 134. The method of staging a memory cell according to claim 129, wherein the inter-electrode material layer comprises cerium oxide having a thickness of less than 15 angstroms. 135. The method of staging a memory cell according to claim 129, wherein the inter-electrode material layer comprises oxynitride having a thickness of less than 15 angstroms. 136. The method of staging a memory cell according to claim 129, wherein the inter-electrode material layer is selected from the group consisting of Al2〇3, YTa2〇5, Hf〇2, Y2〇3, Ce02, Ti〇2. At least one of the groups of HfSixOy, HfSiON, HfA10x, TaOxNy, Zr〇2, ZrSixOy and La2〇3. 137. The method of staging a memory cell according to claim 129, further comprising: generating a signal to display the characteristic after supplying the stress to induce the progressive change of the characteristic, and combining the signal with a reference Signals are compared to confirm the stylized requirements. 138. The method of staging a memory cell according to claim 129, further comprising: after supplying the stress to induce the progressive change of the characteristic, generating a signal to display the characteristic and correlating the signal with a reference The signals are compared to confirm the stylized requirements; and if the validation fails, a stress is applied to cause additional changes to the characteristic. 59 127361., c/006 Patent No. 9312 Π00, rev. 94.11.30, 139. The patented method of memory cells described in pp. 129J, where the memory cell comprises a memory cell array A basic component 'a plurality of levels of the characteristic is related to a number of programmed cycles supplied to the memory cell array, the method comprising maintaining a record of the number of programmed cycles supplied to the memory cell array; generating a conformity to the stylization The number of cycles - the reference signal; and the stress that should be stressed to initiate the characteristic change, produces the number 1 display characteristic, and compares the signal with the reference letter to confirm the stylized requirements. W0. The stylized method of the memory cell as described in claim 129, wherein the memory cell comprises a basic component in a memory cell array and a stylized cycle for the memory cell array In relation to the number, the method includes recording a number of programmed cycles supplied to the array of memory cells; providing a source of two reference signals that conform to a first programmed number of cycles and a second programmed number of cycles; After the edge stress is supplied to induce the progressive change of the characteristic, a two-signal display is generated, and the characteristic is compared with a reference signal that matches the programmed number of cycles and the reference signal of one of the two reference signs to confirm the stylization requirement. data of. 141. The stylized method of the memory cell as described in claim 29, wherein the memory cell comprises a basic element in a memory cell array, a plurality of levels of 4 inches, and a supply Corresponding to the number of stylized cycles of the memory cell array, the method includes 60 I2736 MWfu 〇c/006 94.1130 Patent No. 93121700, the scope of the correction == f to the record of the number of programmed cycles of the memory cell array; virtual-stylized The number of loops, the source of the three reference signals of the second stylized loop number and the number of private loops; 丄 The supply of the accumulate one of the accumulates shows the characteristic, #々作白#二4 Tuya 舲唬 付 付 付 彡彳 彡彳 彡彳 彡彳 彡彳 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 帛 帛 帛 帛 帛 帛 帛 帛 帛 帛The stylized I/22 in the 5H memory cell includes a basic element in a memory cell array: the level of 14 is related to the number of stylized cycles supplied to the memory cell array, the method includes ^ should be recorded in the memory cell array - the number of programmed cycles; a source of multiple reference currents that conform to the number of programmed cycles; a 丄 supply of the stress to induce the progressive change of the characteristic, the generation, and the staging of the money current:: ^ Select one of the reference currents for comparison to confirm the stylized requirements. 143. The method of programming a memory cell as described in claim 129, wherein the plurality of levels of the characteristic are related to respective magnitudes of the multi-bit data in the memory cell, the method comprising: Providing a value of the multi-bit data that is programmed in the memory cell; generating a reference signal that conforms to the value; after supplying the stress to induce the progressive change of the characteristic, generating a signal indicating the characteristic and The signal is compared with the reference signal to confirm that the value of the patent range is correct. 61 I2736p4QtwfJd〇c/〇〇6 94.11.30 No. 93] It is expected that the plurality of levels of the 夂^θ° of the memory cell of the memory cell described in the 129th patent are related to the respective quantities of the multi-bit family in the memory cell, and the financial method includes: a value of the multi-bit data in the memory cell; source; the sum of the plurality of reference signals of each of the values of the multi-bit data of 4 bits should be stressed to cause the progressive change of the characteristic to be generated The characteristic is shown, and the signal current is selected according to the value, and the McCaw red-selective reference f-flow is compared to confirm the stylized gamma of the memory cell described in the 129th patent range of the ancient patent. Ir towel turn _ 乡 准 准 is related to the various values of the memory of the multi-bit ,, the method includes: stylized in the memory cell - a value of multi-bit data; mention i, match a bit One of the values of the three sources of the reference signal; _丄================================================================================ Selecting one of the three reference currents to select the reference current for comparison 3 Hai stylized recognized value. 146. The stylization method of a memory cell as described in claim 129, wherein the plurality of levels of the characteristic are related to respective magnitudes of the multi-bit data in the memory cell, the method comprising: providing a value that is stylized in one of the multi-bit data in the memory cell; 62 c/006 Patent No. 93121700, Amendment 94.11.30 provides a source of seven reference signals for each of the three-dimensional values; After stressing to induce the progressive change of the characteristic, a sigma current is generated to indicate the characteristic, and the signal current is compared with a selected reference current selected from the seven reference currents in accordance with the value to confirm the stylization. The value. 147. The method of staging a memory cell according to claim 129, wherein after the stress is supplied, sensing whether the characteristic exceeds a second test level to indicate a first stored value, and then supplying the The stress is for a further period of time to induce an additional progressive change of the characteristic to change the first stored value, and then to sense whether the characteristic exceeds a second reference level to represent a second stored value. 148. The method of staging a memory cell according to claim 129, wherein supplying the stress comprises: supplying a first stylized pulse to the memory cell having a first pulse height and a sigma width; Test 1 if the memory cell is programmed against the first stylized pulse; if = no 'supply—the programmatic retry pulse is sent to the memory cell; whether the program should be programmed to retry the program The cell is a retry pulse until the memory is measured as a word until the memory cell is measured, and the stylized pulses have their respective pulse widths and pulse heights. 63 127361 fl .doc/006 brother 93121700 5 tiger patent range correction 94. U.3〇, these pulse heights and pulse widths are changed according to a mode in which at least one of the stylized retry pulses has a different pulse width or pulse height than the other modes in the moded retry pulse. . % 149. A method for multi-programming a memory array, the memory cell array, each of the memory cells respectively comprising a first electrode and an inter-electrode material layer, the inter-electrode material layer having a thermal extension A feature of the method includes: μ 累% change supply-stress to the _--the characteristic value of the selected memory cell; and 疋Θ埯== to the memory cell array--the number of stylized cycles Corresponding to the continuous material tilting ring and μ changes; ^, the cup test field after the supply of the stress 'generates' the signal display is programmed to the value of the selectivity, and the signal is compared with the reference signal, the sensing is stored in The data in the selected memory cell. Φ W. The method of claim 149, wherein providing the reference signal comprises formulating the two stylized cycles of the stylized cycle and the second stylized cycle; Selecting the second quiz cycle of the two reference signals for the presentation loop and selecting the r-array == of the fine reference signal, the multi-programmed memory described in the 149th patent range and the rut The method of i, wherein the reference signal is provided includes: · 64 12736]· ; twfl .doc / 006 Patent No. 93121700 Scope Correction 94.11.30 provides a source of - a set of reference signals and a second set of reference signals, The first group reference money and the _ second group reference money comply with the first stylized cycle, and the second stylized cycle, the (four)-group reference signal and the second group of the wheat test number respectively include the storage in the selected memory cell a plurality of reference signals of values of the plurality of bits; and corresponding to the first stylized cycle and selecting a 5 test from the first set of reference signals, and from the second stylized The second set of reference signals selects a reference signal 152. The method of claim 1, wherein the layer of electrical material comprises super-compacting: ί= the inter-electrode material layer comprises a body array of thickness less than 20 angstroms, item 149 The plurality of stylized memory dioxotomy, wherein the material layer between the electrodes comprises a body enthalpy having a thickness of less than 15 angstroms === tearing the multi-cut memory nitrous oxide 156 of less than 20 angstroms. For example, the method of applying for a 4-well array of patents, wherein the medium-to-electrode material layer comprises a thickness of less than 15 angstroms stored in a memory array. The resetting of the data is used for the memory cell array, and each of the memory cells includes - ^ 65 I2736P4Q twfl .doc / 〇〇 6 I2736P4Q twfl .doc / 〇〇 6 94.11.30 Patent No. 93121700 a material layer between the second electrode and the electrode, the material layer between the electrodes having a characteristic that changes progressively with stress, and storing the data in the memory array is high by the memory cells not in the memory array. At or below a reference level to indicate a data value, the method includes: changing the reference level. 158. The method of storing in a memory array according to claim 157, wherein the reference level is changed to reset data stored in the memory array, and the memory does not need to be changed. This property of memory cells in the array. The method for resetting the data stored in the column I of the case of claim 157, the anger of the reference scale is changed to the level of the characteristic of the sensory memory cell. The storage method described in item 157 of the paste value is stored in the memory |, shell;, reset method, wherein the characteristic includes resistance, and the change is made. 2=g= is used to sense the memory in the memory array Cell resistance In the column ==^梅_157 赖述的新娘 in the memory 丨 reset method, wherein the inter-electrode material layer includes ultra-thin; the column described in item 157 is stored in the memory 0 丨 in % angstrom In 彳i, the thickness of the layer includes the thickness of the column: 163: The information stored in the traitor column as described in item 157 of the patent application scope is resetting the scorpion scorpion f to i5 Å cerium oxide The middle and middle material layers include a thickness of ^ 66 12736 twfld. — 94.11.30 Amendment to the scope of the patent No. 93121700 is to be stored in the memory array a, ', , and the method, wherein the inter-electrode material layer comprises arsenic oxide having a thickness of less than 20 angstroms. The scope of the patent application is 157. The storage of the replacement branch, which is read in the array, is smear of arsenic oxynitride at 15 angstroms. The method of spatially storing the data stored in the memory array is adapted to the memory cell array, and each of the memory cells includes two first electrodes, a layer of electrodes and an electrode material layer. The material layer between the electrodes has a characteristic that changes progressively with stress, and the method includes: setting the characteristic of the memory cell in the memory array higher or lower than a first reference level to indicate in the memory cell The data value in the column; the reference level is up to the second reference level to reset the memory array. In addition, the characteristic of the cell is higher or lower than the second reference level to indicate the data value in the memory cell. 167. A method of plurality of stylized data stored in a memory array as described in claim 166, comprising changing a reference value for sensing a level of the characteristic of the memory cell in the memory array. . 168. The method of storing a plurality of materials in a memory array as described in claim 166, wherein the characteristic comprises a resistance, and changing the reference level comprises changing a memory for sensing the memory array. The reference current of the resistance of the cell. ~ 169·Multiple stylized storage as described in claim 166 of the patent application 67 i2736i_6 94.11.30 Patent No. 93,921,700 The method of modifying the data in a memory array, wherein the electrical ultrathin layer. The material layer comprises 170. The method of data in the memory array as described in claim 166, wherein the electrode has a thickness of less than 20 angstroms. The __ layer includes 171. The method of applying the data in the array of 166, as described in item 166, wherein the electrical thickness is less than 15 angstroms. The Shield is included in the method of 166, which is stored in a cut-off type, wherein the electrode has a thickness of less than 20 Å. </ RTI> </ RTI> 173. A method of multiple times in a memory array as described in claim 166, wherein the inter-electrode material layer has a thickness of less than 15 angstroms. 174. A method for programmatically storing data stored in a memory array is applied to a δ 彳 彳 cell array, each of the memory cells including a first electrode, a second electrode, and an inter-electrode material layer. The inter-electrode material layer has a _ characteristic that changes progressively with stress, and the method includes: &quot; further, the characteristic of the memory cell in the memory array is higher or lower than a first group reference to indicate Multi-bit data in the memory cell; modifies the first set of reference levels to a second set of reference levels to reset the memory array; and μ yi ^ memory cells in the memory array The characteristics are higher or lower than the first group of meals to indicate the multi-bit data in the memory cell. 68 12736· twfJ .doc/006 12736· twfJ .doc/006 94.11.30 No. 93] Patent No. 21700 Revision 175. Multiple stylized storage as described in claim 174 of the patent application in memory array order The method of data, wherein changing the first set of reference levels to a second set of reference levels comprises changing a reference value for sensing a level of the characteristic of the memory cells in the memory array. 176. A method for programmatically storing data stored in a memory array as described in claim 174, wherein the memory array comprises an array of memory cells, each of the memory cells comprising a first electrode a material layer between the second electrode and the electrode, the characteristic comprising a resistance, changing the first group == quasi-to-the second set of reference levels includes changing (4) sensing the level of the resistance of the memory cell in the memory array Reference current. 177. A method of multiple times in a memory array as described in claim 174, wherein I, an ultrathin layer. /, ^ ^ Hai inter-electrode material layer includes 178. For example, the method of claim 174 in the body, the body array of the method, the thickness of less than 20 angstroms of dioxide. 179. A method of applying data in the memory array of claim 174, a cerium oxide having a thickness of less than 15 angstroms. 180. A method of applying the data of the 174th specification in the FP array, the bismuth oxynitride having a thickness of less than 20 angstroms. The plurality of stylized storages, wherein the inter-electrode material layer comprises a plurality of stylized storages as described in the item, wherein the inter-electrode material layer comprises a plurality of stylized storages, wherein the inter-electrode material layer comprises 181. A method of applying the data in the memory array of claim 174 in a memory array, having a thickness of less than 15 angstroms. Multiple stylized storage as described in the item wherein the inter-electrode material layer includes 69