TW202111694A - 在預定程式狀態中使用最終烘烤來改善類比非揮發性記憶體中之讀取電流穩定性的方法 - Google Patents
在預定程式狀態中使用最終烘烤來改善類比非揮發性記憶體中之讀取電流穩定性的方法 Download PDFInfo
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Abstract
一種改善記憶體裝置的穩定性之方法,該記憶體裝置具有一個控制器,該控制器配置成在由最小程式狀態與最大程式狀態界定之程式化狀態範圍內對複數個非揮發性記憶體單元中之每一者進行程式化。該方法包括測試該等記憶體單元,以確認該等記憶體單元係可操作的;程式化每個記憶體單元至一中間程式狀態;以及在該等記憶體單元被程式化至該中間程式狀態的同時,在高溫下烘烤該記憶體裝置。當以該最小程式狀態來程式化時,每個記憶體單元具有一第一臨界電壓;當以該最大程式狀態來程式化時,每個記憶體單元具有一第二臨界電壓;以及當以該中間程式狀態來程式化時,每個記憶體單元具有一第三臨界電壓。該第三臨界電壓實質上在該第一臨界電壓與該第二臨界電壓之間的中點,並且對應於讀取電流的實質對數中點。
Description
[相關申請案]本申請案主張2019年9月3日所提出之美國臨時申請案第62/895,458號及2020年2月27日所提出之美國專利申請案第16/803,401號之優先權。
本發明係有關於非揮發性記憶體裝置,以及更具體地,係有關於改善在讀取操作期間記憶體單元電流的穩定性。
非揮發性記憶體裝置在本技藝中係眾所周知的。參見例如美國專利第7,868,375號,其揭露四-閘極記憶體單元配置。具體地,本申請案的圖1說明分離式閘極記憶體單元10,其中間隔開的源極及汲極區域14/16形成在矽半導體基板12中。源極區域14可以稱為源極線SL(因為它通常連接至同一列或行中之其它記憶體單元的其它源極區域),而汲極區域16通常藉由位元線接點28連接至位元線。在源極/汲極區域14/16之間界定基板的通道區域18。浮動閘極20配置在通道區域18的第一部分上方且與其絕緣(並控制其導電性)(以及部分配置在源極區域14上方且與其絕緣)。控制閘極22配置在浮動閘極20上方且與其絕緣。選擇閘極24配置在通道區域18的第二部分上方且與其絕緣(並控制其導電性)。抹除閘極26配置在源極區域14上方且與其絕緣,並且在側面相鄰於浮動閘極20。複數個這樣的記憶體單元可以排列成列與行,以形成記憶體單元陣列。
將各種組合的電壓施加至控制閘極22、選擇閘極24、抹除閘極26及/或源極及汲極區域14/16,以程式化記憶體單元(亦即,將電子注入至浮動閘極上)、抹除記憶體單元(亦即,從浮動閘極移除電子)以及讀取記憶體單元(亦即,測量或偵測通道區域18的導電性,以判定浮動閘極20的程式化狀態)。
記憶體單元10可以以數位方式來操作,其中將記憶體單元設定為只有兩個可能狀態中之一:程式化狀態及抹除狀態。記憶體單元藉由在抹除閘極26上施加高正電壓或任選地在控制閘極22上施加負電壓以使電子從浮動閘極20隧穿至抹除閘極26來進行抹除(使浮動閘極處於帶正電狀態-抹除狀態)。記憶體單元10可以藉由在控制閘極22、抹除閘極26、選擇閘極24及源極區域14上施加正電壓並且在汲極區域16上提供電流來進行程式化。電子接著將從汲極區域16沿著通道區域18流向源極區域14,其中一些電子被加速及加熱,藉以將電子藉由熱電子注入而注入浮動閘極20(使浮動閘極處於帶負電狀態-程式化狀態)。記憶體單元10可以藉由在選擇閘極24上施加正電壓(使選擇閘極24下方的通道區域部分導通)且在汲極區域16(並且任選地,在抹除閘極26及/或控制閘極22上)施加正電壓以及感測流經通道區域18的電流來進行讀取。如果浮動閘極20帶正電(被抹除),則會導通記憶體單元,並且電流會從源極區域14流至汲極區域16(亦即,根據感測電流流動而感測到記憶體單元10處於抹除狀態「1」)。如果浮動閘極20帶負電(被程式化),則關斷在浮動閘極下方的通道區域,藉以防止任何電流流動(亦即,根據沒有電流流動而感測到記憶體單元10處於程式化狀態「0」)。
下表提供抹除、程式化及讀取電壓的非限制實例:
表1
WL(SG) | BL(汲極) | 源極 | EG | CG | |
抹除 | 0V | 0V | 0V | 11.5V | 0V |
程式化 | 1V | 1A | 4.5V | 4.5V | 10.5V |
讀取 | Vcc | 0.6V | 0V | 0V | Vcc |
記憶體單元10可以替代地以類比方式來操作,其中記憶體單元的記憶體狀態(亦即,在浮動閘極上的電荷量,例如,電子數量)可以在任何程度上連續地從完全抹除狀態(在浮動閘極上有最少的電子)變成完全程式化狀態(在浮動閘極上有最多數量的電子)或只是這個範圍的一部分。這表示單元儲存器係類比的,其允許記憶體單元陣列中之每個記憶體單元的非常精確及個別調整。或者,記憶體可以作為MLC(多階單元)來操作,其中它配置成被程式化至許多離散值(例如,16或64個不同值)中之一。在類比或MLC程式化的情況下,程式化電壓僅在有限的時間內或作為一系列脈衝來施加,直到達到期望程式化狀態為止。在多個程式化脈衝的情況下,可以使用程式化脈衝之間的介入讀取操作來判定已達到期望程式化狀態(在此情況下,程式化停止)或尚未達到期望程式化狀態(在此情況下,程式化繼續)。
以類比方式或作為MLC操作之記憶體單元10可能更易受雜訊及讀取電流不穩定性影響,這會不利地影響記憶體裝置的準確度。類比非揮發性記憶體裝置之讀取電流不穩定性的一個來源是在閘極氧化物-通道介面上之電子陷阱所造成之電子的捕獲及發射。閘極氧化物係使浮動閘極20與基板12的通道區域18分離之絕緣層。當在介面陷阱上捕獲電子時,電子在讀取操作期間減少通道導電性,因而,增加記憶體單元的臨界電壓Vt(亦即,使記憶體單元的通道區域導通以產生一定程度的電流(例如,1A)所需之控制閘極上的最小電壓)。控制閘極電壓處於臨界電壓或高於臨界電壓時,在源極區域與汲極區域之間產生導電路徑。當控制閘極電壓低於臨界電壓時,不產生導電路徑,並且將任何源極/汲極電流視為次臨界或洩漏電流。電子陷阱再充電的這些單一事件導致1)隨機電報雜訊(RTN)及2)單向臨界電壓(Vt)移位(亦使讀取操作通道電流改變),這稱為鬆弛(relaxation)或CCI-單元電流不穩定性。
在記憶體單元保持在室溫下一段長時間或在一個狀態中以高溫烘烤及然後改變至一個不同狀態之後,偵測到這樣的鬆弛。所述鬆弛似乎是記憶體單元新狀態朝向先前狀態的小漂移。例如,如果記憶體單元保抹在其抹除狀態(其特徵在於在讀取操作期間的低臨界電壓Vt及高通道電流)一段時間及接著程式化為其程式化狀態(其特徵在於在讀取操作期間的高臨界電壓Vt及低通道電流),則發現臨界電壓Vt稍微下降,並且發現在讀取操作期間的讀取電流在相同讀取條件下隨著時間稍微增加。當與以數位方式操作之記憶體單元的1與0之間的典型單元電流操作範圍相較,Vt及讀取電流移位相對較小。然而,這些位移對於作為MLC(多階單元)或以類比方式操作的記憶體單元來說可能是不可忽略的。
有必要減少非揮發性記憶體裝置中之讀取電流不穩定性。
藉由一種改善記憶體裝置的穩定性之方法來解決上述問題及需求,該記憶體裝置包括複數個非揮發性記憶體單元及一個控制器,該控制器配置成在由最小程式狀態與最大程式狀態界定之程式化狀態範圍內對每個記憶體單元進行程式化。該方法包括測試該等記憶體單元,以確認該等記憶體單元係可操作的;程式化每個記憶體單元至一中間程式狀態;以及在該等記憶體單元被程式化至該中間程式狀態的同時,在高溫下烘烤該記憶體裝置。對於每個記憶體單元,當以該最小程式狀態來程式化時,該記憶體單元具有一第一臨界電壓;當以該最大程式狀態來程式化時,該記憶體單元具有一第二臨界電壓;以及當以該中間程式狀態來程式化時,該記憶體單元具有一第三臨界電壓,其中該第三臨界電壓實質上在該第一臨界電壓與該第二臨界電壓之間的中點。
一種改善記憶體裝置的穩定性之方法,該記憶體裝置包括複數個非揮發性記憶體單元及一控制器,每個記憶體單元包括至少一個浮動閘極,其配置在一半導體基板的一通道區域上方且與該半導體基板的該通道區域絕緣,及一控制閘極,其配置在該浮動閘極上方且與該浮動閘極絕緣;該控制器配置成在由最小程式狀態與最大程式狀態界定之程式化狀態範圍內對每個記憶體單元進行程式化及使用被施加至該控制閘極的一讀取電壓來讀取每個記憶體單元。該方法包括測試該等記憶體單元,以確認該等記憶體單元係可操作的;程式化每個記憶體單元至一中間程式狀態;以及在該等記憶體單元被程式化至該中間程式狀態的同時,在高溫下烘烤該記憶體裝置。對於每個記憶體單元,當以該最小程式狀態來程式化時,該記憶體單元使用被施加至該控制閘極的該讀取電壓在一讀取操作期間產生一第一讀取電流;當以該最大程式狀態來程式化時,該記憶體單元使用被施加至該控制閘極的該讀取電壓在一讀取操作期間產生一第二讀取電流;以及當以該中間程式狀態來程式化時,該記憶體單元使用被施加至該控制閘極的該讀取電壓在一讀取操作期間產生一第三讀取電流,其中該第三讀取電流實質上在該第一讀取電流與該第二讀取電流之間的對數中點。
本發明的其它目的及特徵藉由閱讀說明書、申請專利範圍及附圖將變得顯而易知。
本發明係用於穩定圖1之類型的非揮發性記憶體單元之讀取電流以改善讀取操作準確度及記憶保持壽命的技術。讀取穩定化技術包含在執行最終高溫烘烤製程之前將完成且可操作記憶體單元程式化至一個預定程式狀態。具體地,在記憶體裝置測試製程期間,裝置中之記憶體陣列可以用各種資料型樣進行許多熱操作。然而,一旦記憶體裝置測試完成,接著將所有記憶體單元程式化至一個預定中間程式狀態,隨後執行記憶體裝置的最終高溫烘烤。已發現到,藉由在將記憶體單元程式化至中間程式狀態的同時,執行此最終高溫烘烤,可減少記憶體單元臨界電壓(Vt)隨時間的位移,因此,減少讀取操作電流隨時間的漂移。
期望的中間程式狀態取決於記憶體陣列之控制器配置,這可以從圖2所示之示例性記憶體裝置的架構獲得更佳的理解。記憶體裝置包括一個陣列50的非揮發性記憶體單元10,陣列50可以分成兩個單獨的平面(平面A 52a及平面B 52b)。記憶體單元10可以屬於圖1所示之類型,其形成在單晶片上且在半導體基板12中排列成複數列與行。相鄰於所述陣列的非揮發性記憶體單元為位址解碼器(例如,XDEC 54)、源極線驅動器(例如,SLDRV 56)、行解碼器(例如,YMUX 58)、高電壓列解碼器(例如,HVDEC 60)及位元線控制器(BLINHCTL 62),它們用於對位址進行解碼及在被選記憶體單元的讀取、程式化及抹除操作期間供應各種電壓至不同的記憶體單元閘極及區域。行解碼器58包括感測放大器,其包含用於在讀取操作期間測量位元線上的電流之電路。控制器66(包含控制電路)控制各種裝置元件,以在目標記憶體單元上實施每個操作(程式化、抹除、讀取)。電荷泵 CHRGPMP 64在控制器66的控制下提供用於讀取、程式化及抹除記憶體單元之各種電壓。控制器66配置成操作記憶體裝置,以對記憶體單元10進行程式化、抹除及讀取。
控制器66規定可在正常使用者操作期間使用之記憶體單元的最小及最大程式狀態。最小程式狀態是在正常使用者操作期間在控制器66的控制下每個記憶體單元可以程式化的程式化狀態(亦即,最擦除狀態),對於這種情況,最少數量的電子位於浮動閘極20上,並且記憶體單元在正常讀取操作期間產生最高(最大)源極/汲極電流。最大程式狀態是在正常使用者操作期間在控制器66的控制下每個記憶體單元可以程式化的程式化狀態,對於這種情況,最多數量的電子位於浮動閘極20上,並且記憶體單元在正常讀取操作期間產生最低(最小)源極/汲極電流。
在最終裝置高溫烘烤操作期間使用之中間程式狀態較佳地是在讀取操作期間產生在對數上為分別用於如控制器66所規定之程式化操作範圍的最大及最小程式狀態之最小與最大讀取電流之間的實質中點之讀取電流的程式狀態。中間程式狀態可以藉由作為參數之臨界電壓Vt或讀取電流來判定。記憶體單元係MOSFET電晶體,因此,Vt與讀取電流係透過基本電晶體方程式而直接相關的,所以記憶體單元操作範圍可以根據讀取電流或Vt來判定。在圖3中顯示記憶體單元電流-電壓(I-V)特性的一個實例,其說明Vt與讀取電流之間的關係,其中兩條曲線分別表示記憶體單元之最小及最大程式狀態的I-V特性。在此非限制實例中,在控制閘極上施加為臨界電壓或大於臨界電壓之電壓會在讀取操作期間導致1A或更大的讀取電流(在源極區域與汲極區域之間),在本實例中,這被認為是表示在源極/汲極區域之間建立導電路徑之電流量。圖3中之1A處的電流-電壓(I-V)曲線之向右彎曲表示是在控制閘極上的電壓已達到臨界電壓時獲得的讀取電流。
在圖3的實例中,右手曲線(曲線A)係示例性記憶體單元處於其類比操作範圍的最大程式化狀態之I-V曲線,而左手曲線(曲線B)係示例性記憶體單元處於其類比操作範圍的最小程式化狀態之I-V曲線。用於此記憶體單元的控制器配置成在控制閘極上使用1.2V的讀取電壓,這表示在次臨界狀態下讀取此記憶體單元(亦即,使用次臨界電流來偵測記憶體單元的程式狀態)。給定最大程式化狀態及最小程式化狀態的兩條I-V曲線,由控制器操作之記憶體單元的讀取電流之操作範圍是在100nA與100pA之間。程式化狀態的範圍對應於約0.3V的Vt範圍(在約1.3V與約1.6V之間)。程式化記憶體單元的讀取不穩定性可以根據Vt變化或根據在讀取操作期間的讀取電流變化來表示。如下所述,Vt或讀取電流可以用以作為參數,以量化讀取電流波動減少的解決方案。因此,中間程式狀態被定義為對應於在正常操作期間可達到之最小程式狀態與最大程式狀態在Vt方面的實質中點且對數地對應於分別用於最大程式狀態及最小程式狀態之最小讀取電流與最大讀取電流之間的實質中點之程式狀態 。
如圖4所示,具有用於實施這種讀取穩定化技術的三個主要步驟。第一(步驟1),測試記憶體裝置(其包括記憶體單元10及其控制器66),直到它們係可操作的且不需要另外的高溫烘烤操作來完成裝置的測試之程度。第二(步驟2),將所有記憶體單元10實質地程式化至中間程式狀態。第三(步驟3),包括程式化至中間程式狀態的所有記憶體單元10之記憶體裝置經受最終高溫烤烘製程。圖5顯示實質上程式化至中間程式狀態之上面圖3所述的記憶體單元之記憶體單元I-V特性曲線(曲線C)的一個實例。它的臨界電壓Vt為約1.48V,其實質上在分別用於最小程式化狀態及最大程式化狀態的Vt_min與Vt_max之間的中點(亦即,中點臨界電壓實質上是Vt_min與Vt_max之間的中點)。同樣地,當在讀取操作期間在控制閘極上施加1.2V的讀取電壓時,記憶體單元的讀取電流係約3nA,其在對數上為分別用於最小程式化狀態及最大程式化狀態的100nA與100pA之間的實質中點(亦即,中間讀取電流在對數尺度上實質上是100nA與100pA之間的中點)。
高烘烤溫度係超過在正常使用期間記憶體裝置可承受之最高操作溫度的高溫。例如,如果在使用者條件下產品之最高操作溫度的規格為150o
C,則最終高溫烘烤製程可以包括在175o
C下烘烤記憶體裝置24小時。最小烘烤時間取決於烘烤溫度且在較高溫度下會比較短。較佳地,對於圖1所示之記憶體單元,烘烤時間在175o
C的烘烤溫度下可以高達24小時。通常,烘烤時間越長,關於讀取不穩定性減少的改善效果越好。作為一個實際的範例,如果選擇的封裝允許這樣的高溫處理,則可以將組裝好的部件放置在175o
C下進行一天的烘烤。一旦記憶體裝置封裝以及最終測試及烘烤完成,記憶體裝置將在使用者條件下以改善的讀取穩定性操作。
將理解到,本發明並非侷限於上面所描述及在此所說明的具體例,而是包含落在任何請求項的範圍內之任何所有變化。例如,在此對本發明的提及沒有意欲限制任何請求項或請求項用語的範圍,而只是提及可能由一個或多個請求項涵蓋的一個或多個特徵。上所述之材料、製程及數值的實例只是示例性,並且不應該被視為用於限制申請專利範圍。再者,從申請專利範圍及說明書可顯而易知,除非特別說明,否則不是所有的方法步驟都需要以所說明或要求的順序來執行。
10:分離式閘極記憶體單元
12:半導體基板
14:源極區域
16:汲極區域
18:通道區域
20:浮動閘極
22:控制閘極
24:選擇閘極
26:抹除閘極
28:位元線接點
50:陣列
52a:平面A
52b:平面B
54:位址解碼器(XDEC)
56:源極線驅動器(SLDRV)
58:行解碼器(YMUX)
60:高電壓列解碼器(HVDEC)
62:位元線控制器(BLINHCTL)
64:電荷泵(CHRGPMP)
66:控制器
圖1係習知技藝的記憶體單元之側視剖面圖。
圖2係說明記憶體裝置的組件之示圖。
圖3係根據在次臨界操作範圍中之讀取電流及臨界電壓Vt說明記憶體單元操作範圍的曲線圖。
圖4係顯示程式化及烘烤記憶體單元的步驟之流程圖。
圖5係說明在操作範圍內之記憶體單元的I-V特性之一個實例的曲線圖。
Claims (6)
- 一種改善記憶體裝置的穩定性之方法,該記憶體裝置包括複數個非揮發性記憶體單元及一控制器,該控制器配置成在由一最小程式狀態與一最大程式狀態界定之程式化狀態範圍內對每個記憶體單元進行程式化,該方法包括: 測試該等記憶體單元,以確認該等記憶體單元係可操作的; 程式化每個記憶體單元至一中間程式狀態;以及 在該等記憶體單元被程式化至該中間程式狀態的同時,在高溫下烘烤該記憶體裝置, 其中,對於每個記憶體單元: 當以該最小程式狀態來程式化時,該記憶體單元具有一第一臨界電壓; 當以該最大程式狀態來程式化時,該記憶體單元具有一第二臨界電壓;以及 當以該中間程式狀態來程式化時,該記憶體單元具有一第三臨界電壓, 其中該第三臨界電壓實質上在該第一臨界電壓與該第二臨界電壓之間的中點。
- 如請求項1之方法,其中,每個記憶體單元包括: 間隔開的源極區域及汲極區域,其形成在一半導體基板中,並且該基板的一通道區域在該源極區域與該汲極區域之間延伸; 一浮動閘極,其垂直地配置在該通道區域的一第一部分上方且與該通道區域的該第一部分絕緣; 一選擇閘極,其垂直地配置在該通道區域的一第二部分上方且與該通道區域的該第二部分絕緣;以及 一控制閘極,其垂直地配置在該浮動閘極上方且與該浮動閘極絕緣。
- 如請求項2之方法,其中,每個記憶體單元進一步包括: 一抹除閘極,其配置在該源極區域上方且與該源極區域絕緣。
- 一種改善記憶體裝置的穩定性之方法,該記憶體裝置包括複數個非揮發性記憶體單元及一控制器,每個記憶體單元包括至少一個浮動閘極,其配置在一半導體基板的一通道區域上方且與該半導體基板的該通道區域絕緣,及一控制閘極,其配置在該浮動閘極上方且與該浮動閘極絕緣;該控制器配置成在由一最小程式狀態與一最大程式狀態界定之程式化狀態範圍內對每個記憶體單元進行程式化及使用被施加至該控制閘極的一讀取電壓來讀取每個記憶體單元,該方法包括: 測試該等記憶體單元,以確認該等記憶體單元係可操作的; 程式化每個記憶體單元至一中間程式狀態;以及 在該等記憶體單元被程式化至該中間程式狀態的同時,在高溫下烘烤該記憶體裝置, 其中,對於每個記憶體單元, 當以該最小程式狀態來程式化時,該記憶體單元使用被施加至該控制閘極的該讀取電壓在一讀取操作期間產生一第一讀取電流; 當以該最大程式狀態來程式化時,該記憶體單元使用被施加至該控制閘極的該讀取電壓在一讀取操作期間產生一第二讀取電流;以及 當以該中間程式狀態來程式化時,該記憶體單元使用被施加至該控制閘極的該讀取電壓在一讀取操作期間產生一第三讀取電流, 其中該第三讀取電流實質上在該第一讀取電流與該第二讀取電流之間的對數中點。
- 如請求項4之方法,其中,每個記憶體單元包括: 間隔開的源極區域及汲極區域,其形成在該半導體基板中,並且該基板的該通道區域在該源極區域與該汲極區域之間延伸; 該浮動閘極,其垂直地配置在該通道區域的一第一部分上方且與該通道區域的該第一部分絕緣; 一選擇閘極,其垂直地配置在該通道區域的一第二部分上方且與該通道區域的該第二部分絕緣。
- 如請求項5之方法,其中,每個記憶體單元進一步包括:一抹除閘極,其配置在該源極區域上方且與該源極區域絕緣。
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TW109130120A TWI750793B (zh) | 2019-09-03 | 2020-09-03 | 藉由限制抹除與程式化之間的時間間隔以提高在類比非揮發性記憶體中讀取電流穩定性之方法 |
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