CN1124647C - 半导体器件中的互连结构及其制作方法 - Google Patents

半导体器件中的互连结构及其制作方法 Download PDF

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CN1124647C
CN1124647C CN98126098A CN98126098A CN1124647C CN 1124647 C CN1124647 C CN 1124647C CN 98126098 A CN98126098 A CN 98126098A CN 98126098 A CN98126098 A CN 98126098A CN 1124647 C CN1124647 C CN 1124647C
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辛德·里德塞码·辛普森
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Abstract

在半导体衬底(10)上淀积介电层(28)在半导体器件中制作导电互连(38)。对介电层(28)进行图形化以制作互连窗口(29)。在互连窗口(29)中制作氮化钽势垒层(30)。在氮化钽势垒层(30)上制作含有钯-锡胶体的催化层(31)。在催化层(31)上淀积无电铜层(32)。在无电铜层(32)上制作电镀铜层(34)，且无电铜层(32)用作电镀铜层(34)的引晶层。清除部分电镀铜层(34)，在互连窗口(29)中形成铜互连(38)。

Description

半导体器件中的互连结构及其制作方法
技术领域
本发明一般涉及到半导体器件，更具体地说是涉及到半导体器件中的互连结构及其制作方法。
背景技术
在半导体工业中，惯常是用化学汽相淀积(CVD)和物理汽相淀积(PVD)工艺来制作导电互连。由于成本低、容易淀积以及有现成的设备，目前PVD工艺更受欢迎。但随着半导体器件临界尺寸越来越小，接触和通口的形状比增加，用PVD工艺就难以在这些窗口之中制作共形薄膜。这样，目前的PVD工艺在高形状比窗口中提供的台阶覆盖就很差，所制作的互连结构常常含有空洞。这些空洞降低了互连结构的总体导电率，对半导体器件的可靠性有不利的影响。另一方面，CVD工艺通常能够提供比PVD工艺更共形的薄膜。但CVD工艺需要更昂贵的工艺设备，要经常停机清洗，而且要使用高价低效的化学原材料。此外，用CVD方法在高形状比窗口中制作的互连结构也有形成空洞的问题，且这些薄膜对下方介电材料的粘附常常也出现问题。因此，需要有一种能够在高形状比窗口中淀积高共形薄膜并能够用来降低互连结构中空洞形成的金属化工艺。
发明内容
本发明即为达到上述目的而设计。
根据本发明的一种制作半导体器件中互连结构的方法，其特征是下列步骤：提供半导体衬底；制作介电层覆盖半导体衬底；在介电层中制作窗口，其中该窗口具有底部和侧壁；在窗口的底部和侧壁上制作导电势垒层；在窗口的底部和侧壁上制作包括钯-锡合金的催化层；用无电镀覆工艺在窗口的底部和侧壁上制作铜层，其中的铜层在已经制作催化层之后被制作在窗口的底部和侧壁上；以及制作导电金属层覆盖铜层，其中导电金属层用电镀工艺制作。
根据本发明的一种制作半导体器件中互连结构的方法，其特征是下列步骤：提供半导体衬底；制作介电层覆盖半导体衬底；在介电层中制作窗口，其中该窗口具有底部和侧壁；在窗口的底部和侧壁上制作导电势垒层；在导电势垒层上制作包括钯-锡合金的催化层；用无电镀覆工艺在窗口中共形淀积第一铜层，其覆盖所述催化层；用电镀工艺在窗口的底部和侧壁上制作第二铜层，其中第二铜层紧靠第一铜层，且第一铜层用作电镀工艺的引晶层；以及对第二铜层和第一铜层进行抛光，以便在窗口中制作导电互连。
根据本发明的一种制作半导体器件中互连结构的方法，其特征是下列步骤：提供半导体衬底；在半导体衬底中制作掺杂区；制作第一介电层覆盖半导体衬底；在第一介电层中制作第一窗口，其中第一窗口具有底部和侧壁；在第一窗口的底部和侧壁上制作第一导电势垒层；在第一窗口中包括钯-锡合金的第一催化层，其覆盖所述第一导电势垒层；用无电镀覆工艺在第一窗口的底部和侧壁上制作第一铜层，第一铜层覆盖第一导电势垒层；用电镀工艺在第一窗口的底部和侧壁上制作第二铜层，第二铜层覆盖第一铜层；对第一铜层和第二铜层进行抛光，以形成第一导电互连；制作第二介电层覆盖第一导电互连；在第二介电层中制作第二窗口以暴露部分第一导电互连，其中第二窗口具有底部和侧壁；在第二窗口的底部和侧壁上制作第二导电势垒层；在第二窗口中共形形成包括钯-锡合金的第二催化层，其覆盖第二导电势垒层；用无电镀覆工艺在第二窗口的底部和侧壁上制作第三铜层，第三铜层覆盖第二导电势垒层；用电镀工艺在第二窗口的底部和侧壁上制作第四铜层，第四铜层覆盖第三铜层；以及对第三铜层和第四铜层进行抛光，以形成第二导电互连。
根据本发明的一种制作半导体器件中互连结构的方法，其特征是下列步骤：提供半导体衬底；制作介电层覆盖半导体衬底；在介电层中制作窗口，其中该窗口具有底部和侧壁；在窗口的底部和侧壁上制作导电势垒层；在窗口中制作包括钯-锡合金的催化层，其覆盖导电势垒层；用无电镀覆工艺在窗口的底部和侧壁上制作第一铜层，其中第一铜层在已经制作催化层之后制作；用电镀工艺在窗口的底部和侧壁上制作第二铜层，其中第二铜层紧靠第一铜层，且第一铜层用作电镀工艺的引晶层；以及对第二铜层和第一铜层进行抛光，以便在窗口中形成导电互连。
根据本发明的一种半导体器件中的互连结构，其特征是：半导体衬底；覆盖半导体衬底的介电层；穿透介电层的窗口；位于窗口中的导电势垒层；导电势垒层上和窗口中的钯-锡层；位于窗口中且覆盖导电势垒层和钯-锡层的无电铜层；以及位于窗口中且覆盖无电铜层的电镀铜层。
附图说明
图1-8剖面图示出了根据本发明一个实施例的工艺步骤。
图9剖面图示出了根据本发明另一实施例的互连结构。
图10剖面图示出了根据本发明另一实施例的互连结构。
具体实施方式
图1所示的是根据本发明一个实施例的部分集成电路结构5。此集成电路结构包含半导体衬底10、场隔离区12、晶体管14、导电栓24、介电层22、腐蚀停止层26和介电层28。晶体管14包含源/漏区16、栅介电层18和栅电极20。在一个实施例中，半导体衬底10是单晶硅衬底。作为变通，半导体衬底10也可以是绝缘体上硅衬底、蓝宝石上硅衬底之类。
在一个实施例中，场隔离区12是用常规腐蚀和化学机械抛光方法制作的沟槽隔离区。作为变通，场隔离区12可以是用诸如硅局部氧化(LOCOS)、多晶缓冲LOCOS(PBL)、多晶硅包封局部氧化(PELOX)之类的常规方法制作的场氧化区。
在一个实施例中，栅介电层18是用对部分半导体衬底10进行热氧化的方法制作的热二氧化硅层。作为变通，栅介电层18可以是氮化硅层、氮氧化硅层、化学汽相淀积的二氧化硅层、氮化氧化物层、或它们的组合。
在一个实施例中，栅电极20是多晶硅层。作为变通，栅电极20可以是钨或钼之类的金属层、氮化钛或氮化钨之类的氮化金属层、或它们的组合。此外，栅电极20可以是多晶硅层上的含有诸如硅化钨、硅化钛或硅化钴之类的金属硅化物的多层结构层。
在一个实施例中，介电层22是用TEOS作为源气体制作的等离子体淀积氧化物。作为变通，介电层22可以是氮化硅层、PSG层、BPSG层、SOG层、氮氧化硅层、聚酰亚胺层、低介电常数绝缘体、或它们的组合。
在一个实施例中，导电栓24用钛/氮化钛势垒层和钨接触填充制作。在淀积钨部分之后，用常规腐蚀或化学机械抛光方法清除下方的钛/氮化钛势垒层以形成导电栓24。作为变通，导电栓24可以用多晶硅作为接触填充材料来制作。
在一个实施例中，腐蚀停止层26是用常规等离子体淀积方法制作的氮氧化硅层。作为变通，腐蚀停止层26可以是等离子体淀积的氮化硅层、氮化硼层之类。
在一个实施例中，介电层28是用TEOS作为源气体制作的等离子体淀积的氧化物层。作为变通，介电层28可以是氮化硅层、PSG层、BPSG层、SOG层、氮氧化硅层、聚酰亚胺层、低介电常数绝缘体之类。此外，前述各介电材料的组合也可以用来制作介电层28。
在图2中，部分介电层28和部分腐蚀停止层26随后被清除以暴露部分导电栓24并形成互连窗口29。然后在互连窗口29中制作导电势垒层30。在一个实施例中，导电势垒层30是氮化钽层。作为变通，导电势垒层30可以是氮化钛层、氮化钨层、钽硅氮化物层、钽层、钛-钨(TiW)层之类。导电势垒层30可以用常规溅射或化学汽相淀积方法来淀积。
然后用常规方法制作用于无电淀积工艺的催化层31覆盖导电势垒层30。在一个实施例中，催化层31包含钯-锡(Pd-Sn)胶体。在此特定实施例中，在制作含有钯-锡胶体的层之前，导电势垒层在酸性溶液中被腐蚀，以便清除可能已形成在导电势垒层30外表面上的任何氧化物。例如，若导电势垒层30含有氮化钛，则可用硫酸溶液来清除可能已形成在氮化钛势垒层顶表面上的任何氧化钛。同样，若导电势垒层30含有钽或氮化钽，则可以用氢氟酸溶液来清除形成在钽或氧化钽势垒层顶表面上的五氧化钽。已发现导电势垒层30的腐蚀会提高催化层31与下方导电势垒层30的粘附性。应该理解的是，若导电势垒层30不易形成氧化物，则可以不需要上述的腐蚀过程。作为变通，催化层31可以用铜或金之类的其它金属胶体或其它导电材料来制作。例如，可以用铂酸在导电势垒层30上制作含有铂的催化层。同样，可以用氯化钯在导电势垒层30上制作含有钯的催化层。
然后用无电淀积工艺制作导电引晶层32覆盖催化层31。如图2所示，导电引晶层32的厚度不足以填充互连窗口29，但足以传导电镀所要求的电流密度，以致能够用作电镀引晶层。在一个实施例中，导电引晶层32是厚度约为500埃的铜层。在此特定实施例中，用含有铜离子、甲醛和乙二胺四乙酸(EDTA)的无电镀覆溶液，将无电铜层镀覆到下方的催化层31上。
作为变通，也可以用其它的常规铜电镀溶液或用能够以无电工艺镀在催化层31上的其它导电材料来制作导电引晶层32。例如，导电引晶层32可以是无电镍、无电锡、无电银、无电钯或无电金。
特别需要注意的是，无电淀积工艺使导电引晶层32能够共形淀积到高形状比的窗口中，具有良好的台阶覆盖性。
在图3中，再用电镀工艺制作导电金属层34覆盖导电引晶层32。如图3所示，导电金属层34的厚度足以填充互连窗口29。在一个实施例中，导电金属层34是用含有铜(Cu)、硫酸铜(Cu2SO4)、硫酸(H2SO4)和诸如来自盐酸(HCl)的氯离子的电镀溶液所淀积的铜层。在此特定的实施例中，为了改善铜电镀的均匀性，在铜电镀工艺过程中，对半导体衬底边缘附近的电流密度进行了修正。作为变通，可以用常规电镀方法来制作导电金属层34，并可以用镍或金之类的其它导电材料来制作。特别要注意的是，导电引晶层32用作上述电镀工艺的引晶层。因此，由于能够共形淀积在高形状比窗口中的导电引晶层32使导电金属层34能够随后以高的共形性淀积在高形状比的窗口中，故具有高形状比的窗口能够被导电金属层34可靠地填充。
在图4中，清除部分导电金属层34、导电引晶层32、催化层31和导电势垒层30，以便在图2所示的互连窗口29中制作导电互连39，其中导电互连39包含导电势垒层30的剩余部分36、催化层31的剩余部分35、导电引晶层32的剩余部分37以及导电金属层34的剩余部分28。在导电金属层34和导电引晶层32是铜、催化层31包含钯且导电势垒层30包含钛、钨或钽的特定实施例中，可以用使用含有过氧化氢、柠檬酸铵、氧化铝、1，2，4-三唑和去离子水的抛光胶的化学机械抛光工艺来制作导电互连39。作为变通，可以用诸如离子束研磨、反应离子束刻蚀和等离子体刻蚀之类的常规腐蚀方法，或用腐蚀和抛光相结合的方法来制作导电互连39。应该理解的是，无电镀覆工艺与电镀工艺的结合，使低电阻的导电互连39能够在高形状比的窗口中可靠地制作。
然后制作势垒层40覆盖导电互连39。在一个实施例中，势垒层40是等离子体淀积的氮化硅层。作为变通，势垒层40也可以是等离子体淀积的氮氧化硅层、氮化硼层之类。势垒层40被用来防止导电互连39中的金属原子扩散进入随后在导电互连39上淀积的上方介电层中。例如，若导电互连39含有铜，则势垒层40用作铜的扩散势垒。
制作层间介电层48覆盖势垒层40。在一个实施例中，如图5所示，层间介电层48包含介电层42、腐蚀停止层44和介电层46。
介电层42可以是用TEOS作为源气体而淀积的等离子体淀积氧化物。作为变通，介电层42可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体之类。
腐蚀停止层44可以是等离子体淀积的氮氧化硅层。作为变通，腐蚀停止层44可以是等离子体淀积的氮化硅层、氮化硼层之类。
介电层46可以是用TEOS作为源气体而制作的等离子体淀积氧化物。作为变通，介电层46可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体之类。应该理解的是，层间介电层48不必用不同的介电材料制作。例如，层间介电层48可以用诸如等离子体淀积的氧化物、PSG、BPSG、SOG、聚酰亚胺、低介电常数绝缘体之类的单一介电材料来制作。
在图6中，部分层间介电层48和部分势垒层40被图形化，以便在层间介电层48中制作双重镶嵌的窗口50。如图6所示，双重镶嵌窗口50包含互连部分52和通道部分54，其中通道部分54暴露出一部分导电互连39。在图形化工艺过程中，腐蚀停止层44在介电层46被腐蚀以形成互连部分52时，对介电层42进行保护。
在图7中，在双重镶嵌窗口50中制作导电势垒层52。在一个实施例中，导电势垒层52是氮化钽层。作为变通，导电势垒层52可以是氮化钛层、氮化钨层、钽硅氮化物层、钽层、钛-钨(TiW)层之类。可以用常规溅射或化学汽相淀积方法来淀积导电势垒层52。
然后用常规方法制作用于无电淀积工艺的催化层53覆盖导电势垒层52。在一个实施例中，催化层53包含钯-锡(Pd-Sn)胶体。在此特定实施例中，为了清除导电势垒层52外表面上可能已经形成的任何氧化物，在制作含有钯-锡胶体的层之前，在酸溶液中对导电势垒层52进行腐蚀。例如，若导电势垒层52含有氮化钛，则可用硫酸溶液来清除可能已形成在氮化钛势垒层顶表面上的任何氧化钛。同样，若导电势垒层52含有钽或氮化钽，则可以用氢氟酸溶液来清除形成在钽或氧化钽势垒层顶表面上的任何五氧化钽。已发现导电势垒层52的腐蚀会提高催化层53与下方导电势垒层52的粘附性。应该理解的是，若导电势垒层52不易形成氧化物，则可以不需要上述的腐蚀过程。作为变通，催化层53可以用铜或金之类的其它金属胶体或其它导电材料来制作。例如，可以用铂酸在导电势垒层52上制作含有铂的催化层。同样，可以用氯化钯在导电势垒层52上制作含有钯的催化层。
然后用无电淀积工艺制作导电引晶层54覆盖催化层53。如图7所示，导电引晶层54的厚度不足以填充双重镶嵌窗口50。在一个实施例中，导电引晶层54是厚度约为500埃的铜层。在此特定实施例中，用含有铜离子、甲醛和乙二胺四乙酸(EDTA)的无电镀覆溶液，将无电铜层镀覆到下方的催化层53上。
作为变通，也可以用其它的常规铜电镀溶液或用能够以无电工艺镀在催化层53上的其它导电材料来制作导电引晶层54。例如，导电引晶层54可以是无电镍、无电锡、无电银、无电钯或无电金。
特别需要注意的是，无电淀积工艺使导电引晶层54能够共形淀积到高形状比的窗口中，具有良好的台阶覆盖性。
然后在图8中，用电镀工艺制作导电金属层覆盖导电引晶层54。导电金属层的厚度足以填充双重镶嵌窗口50。在一个实施例中，导电金属层是用含有铜(Cu)、硫酸铜(Cu2SO4)、硫酸(H2SO4)和诸如来自盐酸(HCl)的氯离子的电镀溶液所淀积的铜层。在此特定的实施例中，如先前图3所述，为了改善铜电镀的均匀性，在铜电镀工艺过程中，对半导体衬底边缘附近的电流密度进行了修正。作为变通，可以用常规电镀方法来制作导电金属层，或者可以用镍或金之类的其它导电材料来制作。特别要注意的是，导电引晶层54用作上述电镀工艺的引晶层。因此，由于能够共形淀积在高形状比窗口中的导电引晶层54使导电金属层能够随后以高的共形性淀积在高形状比的窗口中，故具有高形状比的窗口能够被导电金属层可靠地填充。
在图8中，清除掉部分导电金属层、导电引晶层54、催化层53和导电势垒层52，以便在双重镶嵌窗口50中制作导电互连62，其中导电互连62包含导电势垒层52的剩余部分57、催化层53的剩余部分58、导电引晶层54的剩余部分59以及导电金属层的剩余部分60。如先前图4所述，在导电金属层和导电引晶层54是铜、催化层53包含钯、且导电势垒层52包含钛、钨或钽的特定实施例中，可以用使用含有过氧化氢、柠檬酸铵、氧化铝、1，2，4-三唑和去离子水的抛光胶的化学机械抛光工艺来制作导电互连62。作为变通，可以用诸如离子束研磨、反应离子束刻蚀和等离子体刻蚀之类的常规腐蚀方法，或用腐蚀和抛光相结合的方法来制作导电互连62。应该理解的是，无电镀覆工艺与电镀工艺的结合使低电阻的导电互连62能够在高形状比的窗口中可靠地制作。
然后制作势垒层64覆盖导电互连62。在一个实施例中，势垒层64是等离子体淀积的氮化硅层。作为变通，势垒层64也可以是等离子体淀积的氮氧化硅层、氮化硼层之类。势垒层64被用来防止导电互连62中的金属原子扩散进入随后在导电互连62上淀积的上方介电层中。例如，若导电互连62含有铜，则势垒层64用作铜的扩散势垒。
应该理解的是，为了制造额外的导电互连层，可重复图5-8所述的各个步骤。
图9所示是根据本发明另一实施例制作的部分集成电路结构15。具体地说，图9示出了用单一镶嵌金属化制作多层互连。在本发明的这一实施例中，介电层70制作在图4所示的集成电路结构上。介电层70可以是用TEOS作为源气体而制作的等离子体淀积氧化物层。作为变通，介电层70可以是氮化硅层、PSG层、BPSG层、SOG层、氮氧化硅层、聚酰亚胺层、低介电常数绝缘体之类。此外，前述各介电材料的组合也可以用来制作介电层70。例如，介电层70可以包含等离子体淀积氧化物层上的氮氧化硅层。
然后清除部分介电层70和部分势垒层40以便制作暴露部分导电互连38的通口。再如先前图2和图3所述，在通口中制作导电势垒层、催化层、导电引晶层和导电金属层。然后如先前图4所述，清除部分导电金属层、导电引晶层、催化层和导电势垒层，以便在通口中制作导电互连76，其中导电互连76包含导电势垒层的剩余部分72、催化层的剩余部分73、导电引晶层的剩余部分74和导电金属层的剩余部分75。
然后制作腐蚀停止层78覆盖导电互连76。腐蚀停止层78可以是等离子体淀积的氮氧化硅层。作为变通，腐蚀停止层78可以是等离子体淀积的氮化硅层、氮化硼层之类。
然后制作介电层80覆盖腐蚀停止层78。介电层80可以是用TEOS作为源气体而制作的等离子体淀积氧化物层。作为变通，介电层80可以是氮化硅层、PSG层、BPSG层、SOG层、氮氧化硅层、聚酰亚胺层、低介电常数绝缘体之类。此外，前述各介电材料的组合也可以用来制作介电层80。例如，介电层80可以包含等离子体淀积氧化物层上的氮氧化硅层。
然后清除部分介电层80和部分腐蚀停止层78以便制作暴露部分导电互连76的互连窗口。然后如先前图2和图3所述，在通口中制作导电势垒层、催化层、导电引晶层和导电金属层。再如先前图4所述，清除部分导电金属层、导电引晶层、催化层和导电势垒层，以便在互连窗口中制作导电互连86，其中导电互连86包含导电势垒层的剩余部分82、催化层的剩余部分83、导电引晶层的剩余部分84和导电金属层的剩余部分85。
然后制作势垒层88覆盖导电互连86。在一个实施例中，势垒层88是等离子体淀积的氮化硅层。作为变通，势垒层88可以是等离子体淀积的氮氧化硅层、氮化硼层之类。势垒层88被用来防止导电互连86中的金属原子扩散进入随后在导电互连86上淀积的上方介电层中。例如，若导电互连86含有铜，则势垒层88用作铜的扩散势垒。
应该理解的是，为了制造额外的导电互连层，可重复上述的各个步骤。
图10所示是根据本发明另一实施例制作的部分集成电路结构17。具体地说，图10示出了用双重镶嵌金属化制作多层互连。在图10中，在制作晶体管14和场隔离区12之后，制作层间介电层90覆盖晶体管14和场隔离区12。在一个实施例中，层间介电层90包含介电层92、腐蚀停止层94和介电层96。
介电层92可以是用TEOS作为源气体而淀积的等离子体淀积氧化物层。作为变通，介电层92可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体之类。
腐蚀停止层94可以是等离子体淀积的氮氧化硅层。作为变通，腐蚀停止层94可以是等离子体淀积的氮化硅层、氮化硼层之类。
介电层96可以是用TEOS作为源气体而制作的等离子体淀积氧化物。作为变通，介电层96可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体之类。应该理解的是，层间介电层90不必用不同的介电材料制作。例如，层间介电层90可以用诸如等离子体淀积的氧化物、PSG、BPSG、SOG、聚酰亚胺、低介电常数绝缘体之类的单一介电材料来制作。
然后对部分层间介电层90进行图形化，以便在层间介电层90中制作双重镶嵌的窗口。双重镶嵌窗口包含互连部分和通道部分，其中通道部分暴露出一部分源/漏区16。在图形化工艺过程中，腐蚀停止层94在介电层96被腐蚀以形成互连部分时，对介电层92进行保护。
然后如先前图7和图8所述，在双重镶嵌窗口中制作导电势垒层、催化层、导电引晶层和导电金属层。再如先前图8所述，清除部分导电金属层、导电引晶层、催化层和导电势垒层，以便在双重镶嵌窗口中制作导电互连102，其中导电互连102包含导电势垒层的剩余部分97、催化层的剩余部分98、导电引晶层的剩余部分99和导电金属层的剩余部分100。
然后制作势垒层104覆盖导电互连102。在一个实施例中，势垒层104是等离子体淀积的氮化硅层。作为变通，势垒层104可以是等离子体淀积的氮氧化硅、氮化硼层之类。势垒层104被用来防止导电互连102中的金属原子扩散进入随后在导电互连102上淀积的上方介电层中。例如，若导电互连102含有铜，则势垒层104用作铜的扩散势垒。
再制作层间介电层112覆盖势垒层104。在一个实施例中，层间介电层112包含介电层106、腐蚀停止层108和介电层110。
介电层106可以是用TEOS作为源气体而淀积的等离子体淀积氧化物。作为变通，介电层106可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体之类。
腐蚀停止层108可以是等离子体淀积的氮氧化硅层。作为变通，腐蚀停止层108可以是等离子体淀积的氮化硅层、氮化硼层之类。
介电层110可以是用TEOS作为源气体而制作的等离子体淀积氧化物层。作为变通，介电层110可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体之类。应该理解的是，层间介电层112不必用不同的介电材料制作。例如，层间介电层112可以用诸如等离子体淀积的氧化物、PSG、BPSG、SOG、聚酰亚胺、低介电常数绝缘体之类的单一介电材料来制作。
然后对部分层间介电层112进行图形化，以便在层间介电层112中制作双重镶嵌的窗口。双重镶嵌窗口包含互连部分和通道部分，其中通道部分暴露出一部分导电互连102。在图形化工艺过程中，腐蚀停止层108在介电层110被腐蚀以形成互连部分时，对介电层106进行保护。
然后如先前图7和图8所述，在双重镶嵌窗口中制作导电势垒层、催化层、导电引晶层和导电金属层。再如先前图8所述，清除部分导电金属层、导电引晶层、催化层和导电势垒层，以便在双重镶嵌窗口中制作导电互连118，其中导电互连118包含导电势垒层的剩余部分114、催化层的剩余部分115、导电引晶层的剩余部分116和导电金属层的剩余部分117。
然后制作势垒层120覆盖导电互连118。在一个实施例中，势垒层120是等离子体淀积的氮化硅层。作为变通，势垒层120可以是等离子体淀积的氮氧化硅层、氮化硼层之类。势垒层120被用来防止导电互连118中的金属原子扩散进入随后在导电互连118上淀积的上方介电层中。例如，若导电互连118含有铜，则势垒层120用作铜的扩散势垒。
应该理解的是，为了制造额外的导电互连，可以重复所述的各个步骤。
于是，根据本发明，显然已提供了一种能够在高形状比窗口中淀积高度共形薄膜的金属化工艺，此工艺可用来在高形状比窗口中制作可靠的低电阻互连结构。虽然参照具体的实施例已描述了本发明，但本发明并不局限于这些实施例。本技术领域熟练人员将认识到，可以作出各种修正与改变而不超越本发明的构思与范围。因此意味着本发明包括所附权利要求范围内的所有改变和修正。

Claims (5)

1.一种制作半导体器件中互连结构的方法，其特征是下列步骤：
提供半导体衬底(10)；
制作介电层(28)覆盖半导体衬底；
在介电层中制作窗口(29)，其中该窗口具有底部和侧壁；
在窗口的底部和侧壁上制作导电势垒层(30)；
在窗口的底部和侧壁上制作包括钯-锡合金的催化层(31)；
用无电镀覆工艺在窗口的底部和侧壁上制作铜层(32)，其中的铜层在已经制作催化层之后被制作在窗口的底部和侧壁上；以及
制作导电金属层(34)覆盖铜层，其中导电金属层用电镀工艺制作。
2.一种制作半导体器件中互连结构的方法，其特征是下列步骤：
提供半导体衬底(10)；
制作介电层(28)覆盖半导体衬底；
在介电层中制作窗口(29)，其中该窗口具有底部和侧壁；
在窗口的底部和侧壁上制作导电势垒层(30)；
在导电势垒层(30)上制作包括钯-锡合金的催化层(31)；
用无电镀覆工艺在窗口中共形淀积第一铜层，其覆盖所述催化层(31)；
用电镀工艺在窗口的底部和侧壁上制作第二铜层(34)，其中第二铜层紧靠第一铜层，且第一铜层用作电镀工艺的引晶层；以及
对第二铜层和第一铜层进行抛光，以便在窗口中制作导电互连(39)。
3.一种制作半导体器件中互连结构的方法，其特征是下列步骤：
提供半导体衬底(10)；
在半导体衬底中制作掺杂区(16)；
制作第一介电层(28)覆盖半导体衬底；
在第一介电层中制作第一窗口(29)，其中第一窗口具有底部和侧壁；
在第一窗口的底部和侧壁上制作第一导电势垒层(30)；
在第一窗口中共形形成包括钯-锡合金的第一催化层(31)，其覆盖所述第一导电势垒层；
用无电镀覆工艺在第一窗口的底部和侧壁上制作第一铜层(32)，第一铜层覆盖第一导电势垒层；
用电镀工艺在第一窗口的底部和侧壁上制作第二铜层(34)，第二铜层覆盖第一铜层；
对第一铜层和第二铜层进行抛光，以形成第一导电互连(39)；
制作第二介电层(48)覆盖第一导电互连；
在第二介电层中制作第二窗口(50)以暴露部分第一导电互连，其中第二窗口具有底部和侧壁；
在第二窗口的底部和侧壁上制作第二导电势垒层(52)；
在第二窗口中共形形成包括钯-锡合金的第二催化层(53)，其覆盖第二导电势垒层；
用无电镀覆工艺在第二窗口的底部和侧壁上制作第三铜层(54)，第三铜层覆盖第二导电势垒层；
用电镀工艺在第二窗口的底部和侧壁上制作第四铜层(60)，第四铜层覆盖第三铜层；以及
对第三铜层和第四铜层进行抛光，以形成第二导电互连(62)。
4.一种制作半导体器件中互连结构的方法，其特征是下列步骤：
提供半导体衬底(10)；
制作介电层(28)覆盖半导体衬底；
在介电层中制作窗口(29)，其中该窗口具有底部和侧壁；
在窗口的底部和侧壁上制作导电势垒层(30)；
在窗口中制作包括钯-锡合金的催化层(31)，其覆盖导电势垒层；
用无电镀覆工艺在窗口的底部和侧壁上制作第一铜层(32)，其中第一铜层在已经制作催化层之后制作；
用电镀工艺在窗口的底部和侧壁上制作第二铜层(34)，其中第二铜层紧靠第一铜层，且第一铜层用作电镀工艺的引晶层；以及
对第二铜层和第一铜层进行抛光，以便在窗口中形成导电互连(39)。
5.一种半导体器件中的互连结构，其特征是：
半导体衬底(10)；
覆盖半导体衬底的介电层(28)；
穿透介电层的窗口(29)；
位于窗口中的导电势垒层(36)；
导电势垒层上和窗口中的钯-锡层；
位于窗口中且覆盖导电势垒层和钯-锡层的无电铜层(37)；以及
位于窗口中且覆盖无电铜层的电镀铜层(38)。
CN98126098A 1998-02-12 1998-12-28 半导体器件中的互连结构及其制作方法 Expired - Fee Related CN1124647C (zh)

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