TW395040B - Metallization process of integrating tungsten plug and copper interconnect - Google Patents

Abstract

The invention provides a metallization process of integrating tungsten plug and copper interconnect, which uses selective tungsten deposit to form the tungsten plug in the contact layer and form copper interconnect in application of the dual damascene structure. The process includes the steps of: (a) providing a semiconductor substrate covered with a dielectric layer; (b) forming the dual damascene structure including the interconnect trench and contact, which is exposed to the surface of the semiconductor substrate; (c) forming a tungsten plug in the contact using selective tungsten deposition method; (d) forming a barrier layer on the interconnect trench and the tungsten plug; and (e) forming a copper metal layer on the barrier layer, and filling up the interconnect trench.

Description

This is all about semiconductor process technology, and especially about the metallization process of double-copper metal interconnects. This process uses a layer of intermediate protection 1, ΐί (άυΜ damaSCene Structure), in the contact window copper and in the first metal (Metai υ is formed in layers, and integrated circuits are becoming more and more sophisticated and complicated. In order to be able to make enough metal interconnects on a limited surface, most of the three-dimensional architecture of multilayer interconnects is used to complete the connection of various components. In addition, a dielectric layer is used as a dielectric material for isolating each metal interconnection. In the process of the multiple interconnection conductor 2 'in addition to the production of the conductor pattern of each layer, it is necessary to use a contact curve or a via. ), As a channel between the contact area of the component and the wire, or the connection between the multilayer wires. In the traditional interconnecting process, ‘due to the structure of the contact window and the wiring pattern’, it requires separate deposition and definition pattern procedures, which makes the entire process steps extremely complicated. In order to overcome the above-mentioned difficulties, a double-layer embedded structure (dual damascene structure) is currently developed. A groove having a dielectric layer window and an interconnect pattern is first made on the dielectric layer of the substrate, and then a conductive layer is formed. Layer fills the interlayer window and interconnecting trenches, and simultaneously produces contact plugs and interconnecting structures, to achieve the effect of simplifying the process steps. 0 In recent years, in order to meet the development of shrinking component size and increase the speed of component operation 'Copper metal with low resistance constant and high electron migration resistance' has been gradually used as the material of metal interconnects, replacing the previous Ming metal process technology. Embedded interconnect technology with copper metal

CAProgram Files \ Patent \ 0503-3963-E.ptd Page 4 V. Description of the invention (2) Not only can reduce the size of the interconnect and reduce the RC time delay, but also solve the problem of difficult copper metal etching, so Has become the main development trend of multiple interconnects today. In today's semiconductor metallization process, although copper metal interconnects are the main development trend, the filling of the lower contact windows is generally still using tungsten plugs' to avoid damaging the underlying semiconductor components. Although tungsten has a high resistance, it is not suitable for metal wiring. However, because tungsten has a good resistance to electron migration under high current density, and it can form a good Omega contact with silicon ', plus the LP-CVD technology Success makes the crane plug very suitable for filling contact windows and vias. At present, the manufacture of tungsten plugs is mostly made by blanket CVD-W and then etched back. However, due to the application of blanket tungsten deposition below 0.25 / zm, there are inherent limitations. Therefore, below 0.25 / zm, 'selective tungsten deposition (Selective CVD-W) has begun to be used in the industry. In order to further understand the background of the present invention, the process of making plugs by selective tungsten deposition in the conventional art will be described with reference to FIG. 1 and the disadvantages thereof. FIG. 1 is a schematic cross-sectional view of forming a tungsten plug in a contact window using selective tungsten deposition. As shown in the figure, when the process needs to form tungsten plugs in contact windows of different depths, this method is used in the shallow The tungsten plug 20a formed by the contact window is prone to overflow, and the tungsten plug 20b formed in the deep contact window may be underfilled, which greatly limits the application range of the selective tungsten deposition technology. limit. In addition, after the tungsten plug is manufactured, the dielectric layer 18 and the tungsten plug 20a '2b are generally subjected to chemical mechanical polishing (CMP).

C: \ ProgramFiles \ Patent \ 0503-3963-E.ptd page 5 5. Description of the invention (3) Only after planarization can the first metal layer (metal n) be prepared, and CMP cleaning must be performed before (CMP ciean) This makes the whole system complicated and expensive. In view of this, the main purpose of the present invention is to provide a metallization system that integrates tungsten plugs and copper metal interconnects in order to solve the above. Tungsten is deposited to make tungsten plugs without having to worry about the problem of overfilling or insufficient filling of the plugs. Another object of the present invention is to provide a metallization process that integrates tungsten plugs and copper-gold interconnects. The manufacturing process of tungsten plugs and interconnects can be simplified, no CMP is required for planarization, and no additional CMP cleaning μ steps are required, which can reduce manufacturing costs. In order to achieve the above purpose, the method of the present invention firstly includes a dielectric layer A dual damascene structure is fabricated on the above, and then the tungsten plug is deposited and the first metal layer is manufactured together after iron. In the entire description of the present invention, the dual damascene structure refers to One Structure including "internal wiring trench" (metal trench) and "contact window" (contact window), and the contact window is located below the interconnection trench to expose the surface of the substrate Contact area or conductive layer. According to the method of the present invention, after a tungsten plug is first formed in a contact window in a double-layer embedded structure by a selective tungsten deposition method, no additional planarization step is required, and the method can be directly used in any manner. Metal interconnects are made in the interconnect trenches. For example, a barrier layer, a copper seed layer (as needed), a copper metal layer can be deposited in sequence in the interconnect trenches, and finally flattened with CMP To complete the production of copper metal interconnects. In detail, the method of the present invention includes the following steps: (a) Provide a ΓΓ ^ Μ C: \ ProgramFiles \ Patent \ 0503-3963-E_ptd page 6

V. Description of the invention (4) A semiconductor substrate with ϋ = Ι; 形成 forming a double-layer embedded structure including a touch window in the dielectric layer, exposing part of the semiconductor substrate ^ facet The tungsten deposition method forms a tungsten plug in the contact window, Cd) forms a barrier layer, covers the dielectric layer, the interconnect trench and the crane plug, and (e) forms a copper on the barrier layer. A metal layer and filling the interconnect trenches; and (f) removing the copper metal layer and the barrier layer on the dielectric layer to obtain a flat surface to complete the fabrication of the copper metal interconnects. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings FIG. 1 is A schematic cross-sectional view for explaining the conventional cross-sectional view of forming tungsten plugs in a contact window using selective tungsten deposition ^ 2A ~ 2D are a series of cross-sectional views for explaining the production of tungsten in a preferred embodiment of the present invention Process of plug and copper metal interconnection. DESCRIPTION OF SYMBOLS 10, 30 ~ substrate; 12, 32 ~ field oxide; 14, 34 ~ metal silicide; 16, 36 ~ conductive layer (polycrystalline silicon + metal silicide); 18, 38, 40 ~ dielectric Layer; 41a, 41b ~ double-layer in-entry structure; 20a, 20b, 42a, 42b ~ tungsten plug; 44 ~ barrier layer;

C: \ ProgramFiles \ Patent \ 0503-3963-E. Ptd page 7

4 6 ~ seed layer; 4 8-copper conductive layer. Example First, please refer to FIG. 2A, which shows the initial steps of the present invention. The system of the present invention is light. First, an α. Μ main uh must be provided as a + conductor substrate with a double-layer embedded structure. For the purpose of illustration, two layers of embedded structures 4la, 41b are shown in the figure. The contact window at 41a is a shallow contact window to expose the conductive layer 36 (such as polycrystalline silicon + metal silicide) on the field oxide 32; and the contact window at 41b is a deep contact window to expose the source electrode. The silicon substrate or metal silicide on the drain region 34 ^ 38 '40 is a dielectric layer ', and the material is, for example, an oxide layer such as (VTEOS, PE-TEOS, BP-TEOS, or other low dielectric) Coefficient (low k) of organic materials such as FLARE, PAE-2 or non-organic materials such as FSG, HSQ, etc. It should be noted that the element structure in the figure is for illustrative purposes only and is not intended to limit the invention, and Those skilled in the art can make this double-layer embedded structure in any way without departing from the spirit and scope of the present invention. Then, please refer to FIG. 2B to form a town in the contact window of the buried structure by selective ballast deposition. Plugs 42a and 42b. Generally, LP-CVD method is used for reacting gases such as WFe, S i Η *, Hz, etc. Tungsten sintering reduction reaction selectively deposits tungsten metal on the contact window. In addition, 'nf3' can be used for pre-treatment to remove the natural oxide layer under the contact window before deposition. The previous processing steps can improve the selective deposition. Success rate and reduce the contact resistance between tungsten and substrate. As shown in the figure, although the tungsten plug formed at this time still overflows the contact window (42a) or underfilled (42b), as long as the subsequent metal copper

C: \ ProgramFiles \ Patent \ 0503-3963-E.ptd page 8 V. Description of the invention (6) --- The deposition of the entire embedded structure can fill up the insufficient or overflowing part of the tungsten plug. Will not affect the process. Next, copper metal interconnects can be made in the interconnect trenches of the embedded structure in any conventional manner. Referring to FIG. 2B, a diffusion barrier layer 44 is formed along the outline of the embedded structure, and extends to cover the surface of the dielectric layer 44. The material can be a group (Ta) 'nitride group (TaN), nitrogen Chemical cranes (WN) 'or titanium nitride (TiN) commonly used in conventional processes. A seed layer 46 of copper metal is then formed along the surface of the barrier layer 44 by means of CVD or PVD to facilitate the subsequent metal copper plating process. 〇 According to a preferred embodiment of the present invention, the above-mentioned procedures for depositing the plugs, barrier layers, and copper seed layers can be sequentially performed in different chambers using a multi-chamber reaction chamber without breaking the vacuum. As a result, process reliability and productivity can be increased. On the other hand, in the conventional manufacturing process, since the steps of CMP planarization and CMP cleaning are still required in the middle, they cannot be sequentially completed in the multi-chamber reaction chamber. In comparison, the method of the present invention has simpler steps, lower cost, and higher reliability. Please refer to FIG. 2D. Then, a copper conductive layer 48 is deposited on the seed layer 46 by electroplating, and then the copper metal layer, the seed layer and the barrier layer on the dielectric layer 44 are deposited by chemical mechanical polishing. After removal to obtain a flat surface, the production of copper metal interconnects is completed. Although in this embodiment, the copper conductive layer 48 is formed by depositing a seed layer 44 in conjunction with a plating process, those skilled in the art can also use physical vapor deposition (PVD) without forming a seed layer. ) Or organometallic chemical vapor deposition (MO-CVD) directly deposited copper conductive layer.

C: \ Program Files \ Patent \ 0503_3963-E, ptd page 9

Claims (1)

6. The scope of the patent application (0 forming a barrier layer 'covering the dielectric layer, the interconnect trenches and the tungsten plug; and (e) forming a copper metal layer on the barrier layer, and Fill the inner confinement trench; and (0) remove the steel metal layer and the barrier layer on the dielectric layer to obtain a hutan surface. 6. The metallization process described in item 5 of the scope of patent application, A metal silicide is formed on the substrate exposed by the contact window. 7. The metal north process described in item 5 of the patent application scope, wherein the material of the barrier layer is selected from the group consisting of: nitride Titanium (TiN), group (Ta), nitride button (TaN), and tungsten oxide (WN). 8. The 4L metal dagger process as specified in item 5 of the patent application scope, wherein the copper metal layer is electroplated. Formed by physical vapor deposition or organic metal chemical vapor deposition (MO-CVD). 9. The metallization process described in item 5 of the scope of patent application, wherein step (f) is a chemical mechanical polishing method Remove the copper metal layer and the barrier layer on the dielectric layer. 10. A kind of integrated tungsten plug and copper metal interconnection The metallization process of the wire includes the following steps: (a) providing a semiconductor substrate covered with a dielectric layer; (b) forming a double-layer embedded structure including interconnect trenches and contact windows in the dielectric layer ' A part of the surface of the semiconductor substrate is exposed; Cc) a crane plug is formed in the contact window by a selective tungsten deposition method; (d) a barrier layer is formed covering the dielectric layer, the interconnect trenches and C: \ ProgramFiles \ Patent \ 0503-3963-E. Ptd page 12