413895 五'發明說明（1) 本發明是有關於金屬銅的半導體製程技術，且特別是 有關於一種提高銅製程穩定性（St ability)的方法。 近年來，為配合元件尺寸縮小化的發展以及提高元件 操作速度的需求，具有低電阻常數和高電子遷移阻抗的銅. 金屬’已逐漸被應用來作為金屬内連線的材質，取代以往 的鋁金屬製程技術。 金屬銅本身具有許多先天上的優勢，例如：（〗）低電 阻特性’其阻值為1. 7 // Ω - cm ’而鋁則為2 · 7 # Ω - cm ; (2) 良好的抗電子遷移性，比鋁高了四個數量級（〇rder); (3) 良好的抗應力導致的空洞形成性質（stress_induced void formation)等等。上述優點對於元件的特性有很大 的幫助，例如較快的速度：可降低Cr〇ss Talk ;以及具有 較小的RC時間常數。雖然銅的某些物理性質對於應用在元 件上具有很大的優勢，但是它在一些化學反應的特性上卻 阻礙了銅在元件上的應用，因為銅在低溫時便極易與許多 元素反應。另外，銅膜的容易受到腐蝕且極易氧化，、只要 在含氧的環境下，銅膜就會持續不斷的進行氧化作用，再 加上所形成的CuO或Ci^O是以不規則的方式成長，不僅會 形成在銅線的表面，也會出現在銅導線的内部，更嚴重曰影 響到内連線金屬的品質。 為了提高銅導線的Rc穩定性’目前在介層洞（via)的 階段（在阻障/黏著層尚未沈積之前）， 的電毁進行還原反應，以將銅導線中心用= 原成金屬銅，請參照式（1):413895 Five 'invention description (1) The present invention relates to the semiconductor process technology of metallic copper, and particularly relates to a method for improving the stability of copper process (St ability). In recent years, in order to meet the development of component size reduction and increase the speed of component operation, copper with low resistance constant and high electron migration resistance has been gradually used as the material of metal interconnects to replace the traditional aluminum Metal process technology. Copper metal itself has many inherent advantages, such as: (〗) Low resistance characteristics 'its resistance value is 1. 7 // Ω-cm' and aluminum is 2 · 7 # Ω-cm; (2) good resistance Electron mobility is four orders of magnitude higher than aluminum (〇rder); (3) Good stress-induced void formation and so on. The above advantages greatly help the characteristics of the component, such as faster speed: can reduce Cross Talk; and has a smaller RC time constant. Although some physical properties of copper have great advantages in the application to components, its characteristics of some chemical reactions have hindered the application of copper to components, because copper can easily react with many elements at low temperatures. In addition, the copper film is easily corroded and easily oxidized. As long as it is in an oxygen-containing environment, the copper film will continue to oxidize. In addition, the formed CuO or Ci ^ O is irregular. Growth will not only be formed on the surface of the copper wire, but also inside the copper wire, and it will seriously affect the quality of the interconnect metal. In order to improve the Rc stability of the copper wire, at the stage of the via (before the barrier / adhesive layer has not been deposited), the electrical destruction of the copper wire is reduced to reduce the copper wire center to the original copper. Please refer to formula (1):
413895 五、發明說明（2) H2 + CuO (〇r Cu2〇) ~>Cu + H20 式⑴ 然而’此方法僅限於"治療"的效果，即使當氧化銅經 過還原回到金屬銅後，仍難保它不會在後面製程中繼續受 到氧化〗因此’實有必要提供一個更可靠的方法以防止銅 導線受到進一步的氧化。 有鑑於此’本發明的主要目的就是為了解決上述問題 而提供一種提高銅製程穩定性的方法，該方法可提高銅導 線的抗氧化能力，以避免銅導線在介層洞階段遭到氧化。 為達上述目的’本發明提供一種提高銅製程穩定性的方 法’其特徵在於：利用選擇性化學氣相沈積法，在介層洞 所露出的銅導線上形成銅鍺合金（例如Cu3 G e )，以增加銅 導線的抗氧化能力、提高鋼製程的Rc穩定性。根據本發明 的方法’其主要步驟包括：（a)提供一半導體基底，該基 底上具有一介電層覆於一銅導電層上’且介電層形成有一 孔/同4出其下之銅導電層；（b)在銅導電層露出的表面上 形成一銅鍺合金；（C)形成一阻障層，覆於上述介電層、 孔洞、及銅鍺合金上；以及（d)於阻障層上形成—金屬層 並填滿上述孔洞。 在步驟（b)中，銅鍺合金可利用Ge}j4或。上為氣體源 的選擇性C V D法加以形成，請參照式（2 ):413895 V. Description of the invention (2) H2 + CuO (〇r Cu2〇) ~> Cu + H20 Formula ⑴ However, 'this method is limited to the effect of " treatment " even after the copper oxide is reduced back to metal copper It is still difficult to guarantee that it will not continue to be oxidized in subsequent processes. Therefore, it is necessary to provide a more reliable method to prevent further oxidation of the copper wire. In view of this, the main purpose of the present invention is to provide a method for improving the stability of the copper process in order to solve the above-mentioned problems. The method can improve the oxidation resistance of the copper conductors to prevent the copper conductors from being oxidized at the interlayer hole stage. In order to achieve the above object, the present invention provides a method for improving the stability of a copper process, which is characterized in that a copper-germanium alloy (such as Cu3Ge) is formed on a copper wire exposed by a via of a selective chemical vapor deposition method. In order to increase the oxidation resistance of copper wires and improve the Rc stability of the steel process. The method according to the present invention 'its main steps include: (a) providing a semiconductor substrate having a dielectric layer overlying a copper conductive layer' and the dielectric layer forming a hole / copper underneath A conductive layer; (b) forming a copper-germanium alloy on the exposed surface of the copper conductive layer; (C) forming a barrier layer covering the above-mentioned dielectric layer, holes, and copper-germanium alloy; and (d) resisting A metal layer is formed on the barrier layer and fills the holes. In step (b), the copper germanium alloy may use Ge} j4 or. It is formed by the selective C V D method for the gas source, please refer to the formula (2):
GeH4 + Cu-^CugGe + H2 式（2) 利用此法可使銅鍺合金僅形成在鋼金屬的表面，而不 會形成在介電層上。鋼鍺合金在空氣中可達到5〇〇。〇而保 持不被氧化’ *有相當好的抗氧化性質，而且它的電阻率GeH4 + Cu- ^ CugGe + H2 Formula (2) Using this method, the copper-germanium alloy can be formed only on the surface of the steel metal, but not on the dielectric layer. Steel germanium alloy can reach 500 in the air. 〇 ， While it is not oxidized ’* It has fairly good antioxidant properties, and its resistivity
C:\Prograra Files\Patent\0503-3966-E.ptd第 5 頁 413895 五、發明說明（3) 極低，例如C u3 G e的電阻率僅5 . 5 // Ω - c m，因此對於銅導 線的導電性影響不大。此外，在形成銅鍺合金之後，也可 按照習知方式，利用含有H2或1/He的電漿進行還原反應， 以進一步增加銅導線的可靠度。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明 第卜3圖為一系列剖面圖，用以說明本發明一較佳實 施例製作銅金屬内連線的流程。 符號說明 1 0〜銅導電層； 1 2刻終止層； 1 4〜介電層； 1 6〜銅鍺合金薄膜； 1 8〜擴散阻障層； 20〜導電層。 實施例 首先請參照第1圖，其顯示本發明之起始步驟。在銅 金屬層10以下的部分，可能包含數層金屬内連線與數個電 性上相互連接的半導體元件，如MOS電晶體、電阻、邏輯 元件等，為方面起見，圖中僅繪出銅導電層10以上的部 分，而銅導電層10以下的半導體基底與積體電路元件由於 非關本發明之重點，在此予以省略。C: \ Prograra Files \ Patent \ 0503-3966-E.ptd page 5 413895 V. Description of the invention (3) Very low, for example, the resistivity of C u3 G e is only 5. 5 // Ω-cm, so for copper The conductivity of the wire has little effect. In addition, after the copper-germanium alloy is formed, a reduction reaction can also be performed using a plasma containing H2 or 1 / He in a conventional manner to further increase the reliability of the copper wire. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings FIG. 3 A series of cross-sectional views are used to explain the process of making copper metal interconnects according to a preferred embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 0 ~ copper conductive layer; 12 etch stop layer; 14 ~ dielectric layer; 16 ~ copper germanium thin film; 18 ~ diffusive barrier layer; 20 ~ conductive layer. Examples First, please refer to FIG. 1, which shows the initial steps of the present invention. The part below the copper metal layer 10 may include several layers of metal interconnects and several electrically connected semiconductor elements, such as MOS transistors, resistors, logic elements, etc. For the sake of convenience, only the figures are drawn in the figure Portions above the copper conductive layer 10, and semiconductor substrates and integrated circuit elements below the copper conductive layer 10 are omitted because they are not the focus of the present invention.
C:\Program Fiies\Patent\0503-3966-E.ptd第 6 頁 413895 五'發明說明（4) 在銅導電層10之上依序形成有一蝕刻終止層12與〜介 電層14 ’ 一般而言，蝕刻終止層12的材質通常為氮化矽， 而介電層1 4例如是氧化矽、硼矽玻璃、硼磷矽玻璃、或是 其它低介電係數（low k)的有機材質如FLARE、PAE-2或非' 有機材質如FSG、HSQ等。上述的介電層經過微影與蝕刻程 序後形成有一介層洞15，露出底下的銅導電層1〇。經過光 阻去除的步驟後，此時在傳統製程上是以含有I或^/He的 電聚進行還原反應’以將銅導線1〇中的氧化銅還原成金屬 銅；但在本實施例中則是以選擇性口!）法，在銅導線露出 的表面上开> 成銅錄合金（Cu_Ge alloy)護層，以下將配合 第2圖作一詳細說明。 請參照第2圖’以選擇性的化學氣相沈積法在金屬銅 所露出的表面上形成一銅鍺合金薄膜16作為護層。該方法 是將上述銅導線暴露在含有GeH4 *Ge2H6的㈢^反應室中（壓 力約0.5〜ITorr)，以大於150X：的溫度（150〜450 °C)在銅金 屬的表面形成一鍺膜，使該鍺臈進一步與表面上的銅反應 成銅鍺合金，例如CuaGe。由於鍺膜的沈積是一種固態反 應（solid-state reaction)，對金屬銅具有相當的選擇 性’因此不會導致鍺膜沈積在介電層14上。如前文中所 述’銅鍺合金薄膜1 6具有極佳的抗氧化性，因此可防止底 下的銅導線受到氧化侵蝕，而且其電阻率很低，不會對銅 的導電性造成太大的影響。 接下來步驟’是依序沈積一阻障層與—導電層，以完 成導電插塞與金屬内連線的製作，但在沈積阻障層之前，C: \ Program Fiies \ Patent \ 0503-3966-E.ptd Page 6 413895 Five 'Description of the Invention (4) An etching stop layer 12 and a dielectric layer 14 are sequentially formed on the copper conductive layer 10' Generally and In other words, the material of the etch stop layer 12 is usually silicon nitride, and the dielectric layer 14 is, for example, silicon oxide, borosilicate glass, borophosphosilicate glass, or other low-k organic materials such as FLARE. , PAE-2 or non-'organic materials such as FSG, HSQ, etc. After the above-mentioned dielectric layer is subjected to a lithography and etching process, a dielectric hole 15 is formed to expose the copper conductive layer 10 underneath. After the photoresist removal step, at this time, in a conventional process, a reduction reaction is performed using an electropolymerization containing I or ^ / He to reduce copper oxide in the copper wire 10 to metallic copper; but in this embodiment The Cu-Ge alloy protective layer is formed on the exposed surface of the copper wire by the selective mouth!) Method, which will be described in detail with reference to Figure 2 below. Referring to FIG. 2 ', a copper-germanium alloy thin film 16 is formed on the exposed surface of metallic copper by a selective chemical vapor deposition method as a protective layer. In this method, the copper wire is exposed to a ㈢ ^ reaction chamber containing GeH4 * Ge2H6 (pressure is about 0.5 to ITorr), and a germanium film is formed on the surface of the copper metal at a temperature greater than 150X: (150 to 450 ° C). The germanium-rhenium is further reacted with copper on the surface to form a copper-germanium alloy, such as CuaGe. Since the deposition of the germanium film is a solid-state reaction, it has considerable selectivity to metallic copper 'and therefore does not cause the germanium film to be deposited on the dielectric layer 14. As mentioned above, the copper-germanium alloy film 16 has excellent oxidation resistance, so it can prevent the underlying copper wire from being oxidized and its electrical resistivity is very low, which will not affect the conductivity of copper much. . The next step ’is to sequentially deposit a barrier layer and a conductive layer to complete the fabrication of conductive plugs and metal interconnects, but before depositing the barrier layer,
413895 五 '發明說明（5) 可視需要而定’利用含有化或心/He的電漿進行還原反應， 以進一步提高銅導線的可靠度。請參照第3圖’在基底上 沿著介層洞的輪廓沈積一擴散阻障層1 8。此擴散阻障層可 以幫助後續金屬的附著並阻止其擴散，對銅而言，適當的 擴散阻障層材料包括：鈕（Ta)，氮化钽（TaN)，氮化鎢 (Wf〇 ’或是習知製程中常用的氮化鈦（TiN)等。之後，以 PVD、CVD、或電鍍的方式沈積一導電層（例如銅）2〇填滿 介層洞且延伸覆蓋在介電層上。 根據本發明之較佳實施例，上述沈積銅鍺合金、H2 /He電聚還原、以及沈積阻障層與導電層的程序可利用一 夕腔反應室（cluster chamber)在不同的腔中依序完成而 不破真空’藉此可提高製程的可靠度並提昇產能。而之後 的步驟’尚可包括以化學機械研磨法對金屬層2〇進行平坦 化、以及製作氮化矽護層等步驟，但由於這些製程非關本 發明之特徵’在此處不予贅述。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 ”413895 Five 'Explanation of the invention (5) as required' Reduction reaction using a plasma containing chemistry or heart / He is used to further improve the reliability of the copper wire. Referring to FIG. 3 ', a diffusion barrier layer 18 is deposited on the substrate along the contour of the via hole. This diffusion barrier layer can help the subsequent metal adhesion and prevent its diffusion. For copper, suitable materials for the diffusion barrier layer include: button (Ta), tantalum nitride (TaN), tungsten nitride (Wf〇 'or It is a titanium nitride (TiN) commonly used in the conventional manufacturing process. Then, a conductive layer (such as copper) is deposited by PVD, CVD, or electroplating to fill the interlayer hole and extend to cover the dielectric layer. According to a preferred embodiment of the present invention, the above-mentioned procedures for depositing copper-germanium alloy, H 2 / He electropolymerization reduction, and depositing a barrier layer and a conductive layer can be sequentially performed in different chambers using a cluster chamber. 'Complete without breaking the vacuum' can improve the reliability of the process and increase the production capacity. The subsequent steps' may also include steps such as planarizing the metal layer 20 by chemical mechanical polishing and forming a silicon nitride protective layer, but Because these processes are not related to the features of the present invention 'will not be repeated here. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art will not depart from the present invention. Spirit and scope , When it can make various modifications and variations of the present invention thus protect the scope of protection as defined by the appended depending on the scope of the patent, whichever. "