TW400391B - Method for avoiding the delamination of the dielectrics on the copper film - Google Patents

Abstract

This invention discloses a method for avoiding the delamination of the dielectrics on the copper film. Such method is to proceed reduction treatment on the copper film before the copper film deposited the dielectrics to improve the adhesion between the copper film and the subsequent dielectric material. The above-mentioned reduction procedure can be done by any of the following methods. (1) Put the wafer into the furnace or the rapid thermal annealing system and anneal the wafers at the environment containing N2/H2 gas. (2) Place the wafers into a plasma deposition chamber and proceed the reduction treatment in-situ using NH3 plasma before the dielectrics deposition.

Description

V. Description of the Invention (1) The present invention relates to semiconductor process technology, and in particular, to a method for preventing the dielectric layer from peeling from a copper film. In recent years, 'in order to meet the development of component size reduction and increase the operation speed of components' copper metal with low resistance constant and high electron migration resistance' has gradually been used as the material of metal interconnects, replacing the previous Ming metal Process technology. Copper metal itself has many inherent advantages, such as: (1) low resistance characteristics' its resistance value is I 7 " 〇_cm, and aluminum is 2. 7 " D cm; (2) good anti-electron Migration, four orders of magnitude higher than aluminum (〇rder); (3) good stress-induced void formation properties (stress_induced void fοrmation) and so on. The above advantages greatly help the characteristics of the component, such as faster speed; can reduce Cross Talk; and have a smaller RC time constant. Although the physical properties of copper have great advantages for its application to components ', its characteristics of some chemical reactions have hindered the application of copper to components' because copper can easily react with many elements at low temperatures. In addition, the copper film is easily corroded and easily oxidized, and can not form a self-protective oxide film like aluminum. Therefore, as long as the oxygen-containing environment, the copper film will continue to oxidize, and the Cu or (3) It will not only form on the surface of copper wires, but also on the inside of steel wires, which will seriously affect the quality of the interconnecting metal. At present, in the production of copper wires, a damascene process is mainly used to solve the problem of difficult etching of copper metal. The method is to first etch the grooves (or more) of the metal wires on a flat dielectric. Including the etched interlayer window) Page 4 V. Description of the invention (2), a comprehensive copper deposition is performed, and finally the excess metal is removed by chemical mechanical polishing to obtain a metal surface dispersed in the dielectric layer. As shown in FIG. 1, the flat-walled structure in FIG. 2 is an inner metal dielectric layer (IMD), and 12 is a copper metal layer. Next, referring to FIG. 2, after the copper wire is completed, the wire must be sealed with a cap layer 14 before vaporization, and then another dielectric layer 16 can be deposited for subsequent multiple layers. The wiring process' or deposition is used to protect the underlying components. However, copper wires are cleaned after grinding (p0st CMP clean), and during the period when the cover layer has not been deposited, they are susceptible to moisture oxidation and bubble-like defects on the surface (as shown in Figure 13). The adhesion of the deposited dielectric layer decreases, and a delamination phenomenon as shown in FIG. 17 occurs. The main purpose of the layer from the present invention is to provide a method for avoiding dielectric ionization to improve the reliability of the copper process. After grinding, the heading is $. The method of the present invention is to chemically mechanically apply the copper film to improve the adhesion between the dielectric material and the copper wire. The simplified substrate method includes the following main steps: -Semiconductor mechanical polishing: a copper metal layer; (b) chemical reduction of the above substrate; and m = c) a steel metal layer for the remaining copper metal surface treatment. () Depositing a dielectric layer on the above-mentioned two reduction methods ::::, the reduction treatment of the above step (c) can be carried out according to page 5. V. Description of the invention (3) ----- 1. The wafer is moved to a hot furnace tube or a rapid thermal tempering system, and thermal tempering is performed in a gas environment containing \ / 112; or 2. The wafer is placed in a plasma deposition chamber, and the dielectric layer has not been deposited yet. Previously, wafers were reduced in-situ with NH3 plasma. After the Yuancheng copper wire is produced, the wafer is generally transferred to a plasma chemical vapor deposition chamber, and Sil and NH3 are used as reaction gases to form a cap layer to seal the wire. Therefore, the above-mentioned second method 'is to move the wafer to the deposition chamber of the nitriding dream. Before the deposition, only the NHa gas is passed (the gas valve of Si & is kept closed), and the gas generated by the gas is used. The plasma film is subjected to reduction treatment to reduce the copper oxide on the copper film. After the treatment is completed, the Si valve is opened, and then the silicon nitride can be deposited. Because this method integrates the reduction process of the copper film into the silicon dioxide deposition process, it is very easy to perform in the process, and it will not affect the production capacity. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings FIG. 2 A series of cross-sectional views illustrating the conventional metallization process. Figures 3 to 5 are a series of scraped views for explaining the metallization process of the preferred embodiment of the present invention. Explanation of symbols 10, 20 ~ dielectric layer;

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12, 22 ~ copper wires; 13 ~ bubble-like defects; 14, 24 ~ capping layer; 16, 26 ~ inner metal dielectric layer or protective layer; 17 ~ dielectric layer peeling; 23 ~ thermal tempering; 25 ~ Plasma reduction treatment. Example First, please refer to FIG. 3, which shows the initial steps of this example. The part below the inner metal dielectric layer 20 may include several layers of metal interconnects I, and several electrically connected semiconductor elements, such as Mos transistors, resistors, logic elements, etc. In the figure, only the part with the inner metal dielectric layer of 20 or more is drawn, and the semiconductor substrate and bulk circuit elements with the inner metal dielectric layer of 20 or less are omitted because they are not the focus of the present invention. A copper wire 22 is provided in the inner metal dielectric layer, and the copper wire can be formed in the following manner: First, a pattern of interconnecting trenches (or including Defining the interstitial window). Next, a comprehensive copper deposition is performed on the dielectric layer by chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating. For example, an ionized metal plasma (IMP) can be used to deposit a seed layer, and then (the electroplating method is used to complete the deposition of the copper conductive layer. In addition, a diffusion resistance can be provided between the copper wire 22 and the dielectric layer 20 Barrier (not shown) to help metal copper adhere and prevent its diffusion; suitable diffusion barrier materials include buttons (Ta), tantalum nitride (TaN), tungsten nitride (WN) or titanium nitride (TiN )Wait.

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In the tempering system, thermal tempering is performed in a gas environment containing N / H2, and the tempering is completed. After the copper metal is deposited, mechanical polishing is performed to transfer the excess metal to the flat structure of the dielectric layer 20. Grinding step 'forms a large amount of fine powder on the wafer into a solid residue. Generally, spray cleaning or ultrasonic cleaning can be combined. Next, according to the present invention, a copper wire is subjected to a reduction treatment, and the icon number 23 represents a tempering process, and the dielectric layer 20 is used as the polishing end point. It can be obtained that after the copper wire 22 is embedded, the “cleaning at the end of a cleaning step is performed immediately”, otherwise the solution for condensing on the wafer surface is brushed on the wafer before preparation. The method 'is advanced before the sedimentary overlay is shown in Figure 4A or 4B. In the 4A system, the wafer is moved to a hot furnace tube or rapidly heated at about 200-400 ° C for 10-60 minutes, and the desired reduction effect can be achieved. Please refer to Figure 5 'the copper wire after the above treatment, because the Γ copper oxide on the surface has been reduced to metallic copper', the subsequent deposition of the cover layer 24 and the dielectric layer (or protective layer) 26 will have a better adhesion effect 'It can avoid peeling. Icon number 4B 25 represents a plasma reduction process. According to a preferred embodiment of the present invention, the wafer after grinding and cleaning is moved to a reaction chamber in which a coating layer is deposited, and the plasma is directly performed in-situ. Restore processing. Because the material of the cover layer 24 is usually silicon nitride, which is deposited using Si H4 and NH3 as the reaction gas, the method only needs to use a NH3 plasma to reduce the copper film before the deposition, and after the processing is completed, Then pass through Si H4 to deposit silicon nitride 'to form a good coating on the copper wire. It should be noted that although the reduction reaction is carried out with NH3 electric paddles as described above, those skilled in the art can also use other such as l / He 4H2 / N2 plasma to

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.yX a] L -jtr jLl Patent Application Scope I 1.-A method for preventing the dielectric layer on the copper film from peeling off, including the following steps (a) providing a semiconductor substrate with a copper metal layer (b) The above substrate is subjected to chemical mechanical polishing 'to remove part of the copper (c) Reduction treatment of the remaining copper metal surface (d) Depositing a dielectric layer on the above-mentioned reduction treatment 2. The method described in item 1 of the scope of patent application The step (c) further includes a cleaning step after grinding. 3. The method as described in item 1 of the scope of patent application, in which the heat is tempered in a gas environment containing A / H2. ; And a copper metal layer. Wherein step (b) and step (c) are r. The method described by nh3 in the deposition chamber of step (d) as described in item 1 of the scope of patent application, wherein step (c) is for the above copper. The metal is reduced. 5. If the scope of patent application No. 1 Yuyu is a gasification dream layer. The method reached by item, wherein the dielectric layer 6. If the scope of the patent application, item 5 further includes-an inner metal dielectric layer or a protective layer ~, the dielectric layer step: Λ a method to avoid the dielectric on the steel film A method for layer peeling includes the following steps (a): providing a dielectric layer covered with a dielectric layer, and a conductive layer, the dielectric layer passing through a copper metal layer in a slot; and on the dielectric layer Covering the groove (b) with the dielectric layer as the polishing end point, performing chemical processing on the substrate

Claims (1)

Sixth, the scope of patent application " ---- mechanical grinding 'to form a copper metal interconnect in the dielectric layer; (C) a cleaning process after grinding;', (d) placing the substrate ί ^ / Η2 for thermal tempering; (e) depositing a silicon nitride layer on the dielectric layer and the copper wire; and (f) depositing another dielectric layer on the silicon nitride On the floor. 8. The method according to item 7 of the scope of patent application, wherein in step (f), the dielectric layer is an inner metal dielectric layer or a protective layer. 9. A method for avoiding the peeling of a dielectric layer on a copper film, comprising the following steps: (a) providing a semiconductor substrate covered with a dielectric layer, the dielectric layer being defined and having an interconnecting trench after definition ' And the dielectric layer is overlaid with a copper metal layer filling the trench; (b) using the dielectric layer as a polishing end point, performing chemical mechanical polishing on the substrate to form a copper metal in the dielectric layer; Wiring; (c) performing a post-milling cleaning procedure; (d) placing the substrate in a deposition chamber where silicon nitride is intended to be deposited, and before the deposition has been performed, first reducing the above-mentioned copper wire with NH3 plasma (E) depositing a silicon nitride layer on the dielectric layer and the copper wire in the deposition chamber; and (0) depositing another dielectric layer on the silicon nitride layer. The method according to item 9, wherein in step (f) the dielectric layer is an inner metal dielectric layer or a protective layer. Page 11