CN114946018A - Selective tungsten deposition at low temperature - Google Patents

Selective tungsten deposition at low temperature Download PDF

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Publication number
CN114946018A
CN114946018A CN202180008110.0A CN202180008110A CN114946018A CN 114946018 A CN114946018 A CN 114946018A CN 202180008110 A CN202180008110 A CN 202180008110A CN 114946018 A CN114946018 A CN 114946018A
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tungsten
substrate
flow
equal
layer
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徐翼
呼宇飞
雷雨
大东和也
何达
岑嘉杰
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Applied Materials Inc
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Applied Materials Inc
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Priority claimed from US16/917,049 external-priority patent/US11404313B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14—Deposition of only one other metal element
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal

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Abstract

Embodiments of the present disclosure relate to methods of depositing tungsten. Some embodiments of the present disclosure provide methods for depositing tungsten performed at relatively low temperatures. Some embodiments of the present disclosure provide methods in which the ratio between the reactant gases is controlled. Some embodiments of the present disclosure provide for selective deposition of tungsten. Some embodiments of the present disclosure provide methods for depositing tungsten films having relatively low roughness, stress, and impurity levels at low temperatures.

Description

Selective tungsten deposition at low temperature
Technical Field
Embodiments of the present disclosure generally relate to improved methods of forming interconnects. Additional embodiments of the present disclosure relate to methods of forming tungsten at low temperatures.
Background
Reliably producing features below 100nm and smaller is one of the key technical challenges for next generation Very Large Scale Integration (VLSI) and ultra-large scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology advance, the shrinking dimensions of VLSI and ULSI technologies have placed additional demands on processing power. Reliable formation of gate structures on substrates is important to the success of VLSI and ULSI and to the continuing efforts to increase circuit density and quality of individual substrates and dies.
As the circuit density of next generation devices increases, the width of interconnects (such as vias, trenches, contacts, gate structures, and other features), and the width of the dielectric material therebetween, decreases to dimensions of 45nm and 32nm or less, while the thickness of the dielectric layer remains substantially constant, resulting in an increase in the aspect ratio of the features. To enable the fabrication of next generation devices and structures, three-dimensional (3D) stacking of semiconductor chips is often used to improve the performance of transistors. By arranging transistors in three dimensions rather than the conventional two dimensions, multiple transistors may be placed very close to each other in an Integrated Circuit (IC). The 3D stacking of semiconductor chips reduces wire length and keeps wire delay low. At the time of manufacture, 3D stacking of semiconductor chips, a stair-step configuration is often used to allow multiple interconnect structures to be placed thereon, thereby forming high-density vertical transistor devices.
Accordingly, there is a continuing need for improved methods for forming interconnects to reduce manufacturing costs, memory cell size, and power consumption of integrated circuits.
Tungsten films deposited by Chemical Vapor Deposition (CVD) are known to have relatively high stress value roughness. In addition, tungsten films deposited using tungsten hexafluoride are known to have relatively high levels of fluorine impurities. Relatively high levels of stress, roughness, and fluorine impurities often cause problems including, but not limited to, wafer bowing, structural deformation, voids and seams in the gap fill, and fluorine erosion damage at the interface.
Some methods that have been developed to overcome these problems rely on Atomic Layer Deposition (ALD). However, ALD processes are typically performed at relatively high temperatures (typically greater than or equal to 400 ℃).
Thus, there is a need for a method of depositing tungsten that provides low roughness, low stress, and low impurities that is also performed at lower temperatures.
Disclosure of Invention
One or more embodiments of the present disclosure relate to a method of depositing tungsten. The method includes exposing the substrate to a hydrogen gas stream and exposing the substrate to a tungsten precursor stream while exposing the substrate to the hydrogen gas stream to deposit a tungsten layer on the substrate. The substrate is maintained at a temperature of less than or equal to about 350 ℃.
Additional embodiments of the present disclosure relate to a method of depositing tungsten. The method includes exposing the substrate to a hydrogen gas stream and exposing the substrate to a tungsten precursor stream while exposing the substrate to the hydrogen gas stream. The ratio of the hydrogen flow to the tungsten precursor flow is greater than or equal to about 500: 1.
Additional embodiments of the present disclosure relate to a method of selectively depositing tungsten. The method includes exposing a substrate comprising a first material surface and a second material surface to a hydrogen gas stream and exposing the substrate to a tungsten precursor stream while exposing the substrate to the hydrogen gas stream to deposit a first thickness of tungsten on the first material surface and a second thickness of tungsten on the second material surface. A ratio of the first thickness to the second thickness is greater than or equal to about 200: 1.
Drawings
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
FIG. 1 illustrates a method of forming an interconnect in accordance with one or more embodiments;
fig. 2A-2G illustrate cross-sectional side views of an interconnect formed on a substrate at various stages of the method of fig. 1, in accordance with one or more embodiments;
fig. 3 illustrates a multi-chamber processing system on which the method of fig. 1 may be practiced in accordance with one or more embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Detailed Description
Before describing several exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.
As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which processes are functional. As will also be understood by those of skill in the art, reference to a substrate may also refer to only a portion of the substrate unless the context clearly indicates otherwise. Further, reference to deposition on a substrate may mean a bare substrate and a substrate having one or more films or features deposited or formed thereon.
As used herein, "substrate" refers to any substrate or surface of material formed on a substrate on which film processing is performed during the manufacturing process. For example, depending on the application, the surface of the substrate on which processing may be performed includes materials such as silicon, silicon oxide, strained silicon, Silicon On Insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to processing directly on the surface of the substrate itself, in the present disclosure, as disclosed in more detail below, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as the context indicates. Thus, for example, in the case where a film/layer or a portion of a film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.
Fig. 1 is a flow diagram illustrating one embodiment of a method 100 for forming an interconnect on a substrate. Fig. 2A-2G illustrate cross-sectional views of a substrate prior to the method 100 of fig. 1 and at different stages of the method 100 of fig. 1.
Fig. 2A shows a cross-sectional view of the interconnect 200 before the method 100 is started. In general, interconnect 200 includes a plurality of film layers that may be used to form an interconnect structure (such as a dual damascene structure). The film stack 201 is formed on a substrate 202. The stack 201 includes a dielectric layer 204. As shown in fig. 2A, a dielectric layer 204 is disposed on a substrate 202 and has a conductive layer 206 formed in the dielectric layer 204 and bounded by the dielectric layer 204. In one example, the dielectric layer 204 may be formed of one or more insulating materials, such as silicon oxide. In one example, conductive layer 206 may be formed from a conductive layer (such as copper).
At block 102, as shown in fig. 2B, a dielectric barrier layer 208 is deposited on the substrate 202. For example, as shown, a dielectric barrier layer 208 is deposited over both the dielectric layer 204 and the conductive layer 206. Thus, the dielectric barrier layer 208 may form a uniform uninterrupted layer over the dielectric layer 204 and the conductive layer 206. The dielectric barrier layer 208 may be formed of a low dielectric constant material. For example, the dielectric barrier layer 208 can be formed from a carbon-containing silicon layer (SiC), a nitrogen-doped carbon-containing silicon layer (SiCN), a silicon nitride layer, a metal nitride, or a metal oxide (e.g., AlN, AlO) x AlON), or the like.
At block 104, as shown in fig. 2C, a dielectric layer 210 is deposited on the substrate 202. For example, as shown, a dielectric layer 210 is deposited over the dielectric barrier layer 208. The dielectric layer 210 may be substantially similar to the dielectric layer 204. In one embodiment, the dielectric layer 210 may be formed of the same material as the dielectric layer 204. In another embodiment, the dielectric layer 210 may be formed of a different material than the dielectric layer 204 while maintaining the same low dielectric constant properties.
At block 106, as shown in fig. 2D, one or more vias 212 are formed in the interconnect 200 to expose the conductive layer 206. For example, a via 212 may be formed through both the dielectric layer 210 and the dielectric barrier layer 208 to expose the underlying conductive layer 206. Generally, the via 212 has a width W1. In some embodiments, the width of each via 212 is uniform over the entire length of the via 212. In other embodiments, the width of each via 212 may gradually change from the top of the via 212 to the bottom of the via 212.
At block 108, as shown in fig. 2E, one or more trenches 214 are formed in the interconnect 200. One or more trenches 214 may be formed in the dielectric layer 210. The trench 214 is configured to widen at least a portion of the via 212. In some embodiments, block 108 may be performed before block 106, i.e., trench 214 may be formed before via 212. In other embodiments (such as the described embodiment), the trench 214 is formed after the via 212 is formed.
In a conventional fabrication scheme, a "fill process" is performed to fill the via 212 and the trench 214 is filled with a metal material to form the interconnect 200. For example, a metal, such as copper, may be used to fill both the via 212 and the trench 214. It has been found that filling both vias 212 and trenches 214 with the same material results in high interconnect resistance, which can lead to RC delay and IR drop in the semiconductor chip.
The interconnect resistance on the chip affects the chip speed due to RC delay and power management through IR drop. As design rules continue to shrink, interconnect resistance reduction becomes an increasingly important priority. In particular, with short interconnect lines, smaller via sizes of less than 40nm, and multi-layer routing stacked with vias, the resistance of the vias (e.g., via 212) has a significant impact on the overall resistance, i.e., the resistance through the vias is higher compared to through-wiring. Thus, reducing via resistance has become increasingly important for achieving chip performance.
Conventional via formation results in high resistance due to the materials used in process integration. Following block 108, via filling is completed with a metal barrier, liner, and bulk fill material in a conventional manner. Metal barriers and liners are used for reliability and gap fill robustness. However, when deposited at the via bottom, the materials used for the barrier and liner layers can result in high via resistance due to their high resistivity. For example, a conventional dual damascene copper fill may consist of a TaN barrier layer deposited via a Physical Vapor Deposition (PVD) process, a Ta metallic liner layer deposited over the barrier layer (e.g., a PVD or Chemical Vapor Deposition (CVD) process), and a Cu seed/plating layer deposited over the metallic liner layer. Depending on the via size, the barrier and liner weights are greater than about 50% to 90% of the total via resistance. Thus, removing the metal barrier and liner layers may help reduce via resistance. At the same time, however, potential risks may occur due to the elimination of the barrier and liner layers. For example, interconnects will still need to meet reliability aspects, including avoiding dielectric breakdown and metal electromigration. Furthermore, proper metal fill process integration in dual damascene structures may be required to improve both via and line resistance.
Thus, the following discussion proposes a selective fill approach (e.g., a W fill approach), which addresses lower via resistance and meets both integration and reliability requirements. Interface processing (discussed below in connection with at least block 110) and fill processes (discussed below in connection with at least block 118) are developed to selectively grow a metallic material (e.g., W) from the via bottom without damaging the underlying metal layer (e.g., Cu, W, Co, and the like) and surrounding dielectrics (e.g., low-k dielectrics, oxides, and the like). Thus, the following discussion provides one or more techniques to reduce via resistance. The damascene fill will continue after the via fill, which helps to create an equivalent line resistance.
The improved method 100 includes the use of selective metal via filling to reduce resistance and meet reliability (interaction with sidewall dielectric 204 and exposed conductive layer 206) and line resistance requirements. At block 110, one or more pretreatment processes are performed on the interconnect 200 to prepare the interconnect 200 to receive selective metal via 212 fill. For example, block 110 may include sub-blocks 112-116.
At sub-block 112, interconnect 200 undergoes a first treatment process for the exposed portion of conductive layer 206 in via 212. For example, when the via 212 is deposited with a first metal, a first pretreatment process is used to prepare the exposed portion of the conductive layer 206 for bottom-up growth. A remote plasma cleaning process may be used to pre-treat the interconnect. The interconnect 200 may be transferred to a pre-processing chamber where the interconnect 200 undergoes a cleaning process. For example, the interconnect may be subjected to use of H at between about 250-350 deg.C 2 a/Ar mixture, a cleaning process at a temperature of about 1 to 10 Torr. In other embodiments, a slight bias energy may be applied to promote oxide separation without metal sputtering. For example, 0-200W of energy may be applied to the pre-processing chamber.
At sub-block 114, interconnect 200 undergoes a second pre-treatment process. The second treatment process is used to passivate the sidewalls 216 of the vias to minimize undesirable sidewall growth. As mentioned above, the dielectric layer 204 may be formed of a low dielectric constant material. Thus, the second pretreatment process helps to seal the surface pores of the dielectric layer 204 and protect the dielectric layer 204 from the soak precursor. In one embodiment, the second pretreatment process may be a hot precursor soak at high temperature (e.g., 200-. In some examples, precursors that may be used are Tetramethylsilane (TMS), Dimethylaminotrimethylsilane (DMATMS), and the like. In one embodiment, by subjecting interconnect 200 to a UV bake process, the second pre-treatment process in sub-block 114 may further include adding Ultraviolet (UV) energy to the precursor soak process.
In some implementations, block 110 may include sub-block 116. At block 116, the interconnect 200 undergoes an optional post-process cleaning. For example, an optional pre-treatment clean may be used in the case of oxidation or residue growth at the bottom of the via 212. Optional Pre-treatment cleaning uses a cleaning composition containing a peroxide (e.g., H) 2 O 2 ) To slightly remove residues, the chemistry has a basic pH tuning.
At block 118, as shown in fig. 2F, after the pretreatment process (block 110), metal 220 selectively fills vias 212. For example, material of metal 220 is deposited in via 212 up to point 222 where via 212 intersects trench 214. The metal 220 used may be any suitable metal material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), or the like. The primary requirement for metal 220 is that it be a different material than the subsequent metal deposited in trench 214. Selective deposition of metal 220 in the via helps reduce via resistance and meets reliability and line resistance requirements.
The metal 220 may be deposited using a Chemical Vapor Deposition (CVD) process. The CVD process may include H at high temperatures (e.g., 350- 2 And (4) pre-soaking. The CVD process may be performed at a temperature of about 200-500 deg.C using a low flow rate (e.g., 2-100sccm) metal-containing precursor (e.g., WF) 6 ) In a large amount of H 2 In the ambient environment. The combination of flow rate, pressure, and temperature helps to reduce the morphology of the metal 220 when deposited. Prior to depositing the material of metal 220, a conventional nucleation layer may be applied for initial 1-3nm nucleation. The total growth volume is controlled by process time, pressure, and precursor flow to uniformly fill the vias 212.
At block 120, as shown in fig. 2G, a second metal 224 is deposited in each trench 214. For example, a second metal 224 is deposited from point 222 to the top of trench 214. The second metal 224 used may be any suitable metallic material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), and the like. The primary requirement for the second metal 224 is that it be a different material than the material of the first metal 220 deposited in the via 212. The second metal 224 may be deposited using a CVD process. Dividing the conventional metal fill of a single metal material into a two-step process involves a first metal 220 deposited in via 212, and a second metal 224 deposited in trench 214 helps to reduce the resistance through via 212.
In some embodiments, a barrier seed layer (not shown) may be deposited over the first metal 220 prior to depositing the second metal 224. For example, if the second metal 224 is copper, the barrier seed layer may be a copper barrier seed layer.
In some embodiments, the method 100 may include an optional block 119 performed prior to depositing the second metal 224. At block 119, the interconnect 200 may undergo a pretreatment process prior to the second metal 224. A pretreatment process may be used to remove any oxide that may have formed on the top surface of the first metal 220. For example, interconnect 200 may undergo similar processes as sub-block 112.
Figure 3 illustrates a multi-chamber processing system 300. The processing system 300 may include load lock chambers 302, 304, a robot 306, a transfer chamber 308, process chambers 310, 312, 314, 316, 318, 328, and a controller 320. The load lock chambers 302, 304 allow substrates (not shown) to be transferred into and out of the processing system 300. The load lock chambers 302, 304 may evacuate substrates introduced into the processing system 300 to maintain a vacuum seal. The robot 306 may transfer substrates between the load lock chambers 302, 304 and the process chambers 310, 312, 314, 316, 318, and 328. The robot 306 may also transfer substrates between the load lock chambers 302, 304 and the transfer chamber 308.
Each of the processing chambers 310, 312, 314, 316, 318, and 328 may be equipped to perform a plurality of substrate operations, such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), PVD, etching, pre-cleaning, degas, heating, orientation, or other substrate processes. Further, each of the processing chambers 310, 312, 314, 316, 318, and 328 may be equipped to deposit a dielectric barrier layer, deposit a dielectric layer, form one or more vias and trenches in the stack, perform one or more preclean processes, deposit a first metallic material layer, and deposit a second metallic material layer.
The controller 320 may be configured to operate all aspects of the processing system 300, such as the method disclosed in fig. 1. For example, the controller 320 may be configured to control a method of forming an interconnect on a substrate. The controller 320 includes a programmable Central Processing Unit (CPU) 322 operable with memory 324 and mass storage devices, an input control unit, and a display unit (not shown) coupled to various components of the processing system to facilitate control of substrate processing, such as power supplies, clocks, cache, input/output (I/O) circuitry, and pads. The controller 320 also includes hardware for monitoring substrate processing via sensors in the processing system 300, including sensors that monitor precursor, process gas, and purge gas flows. Other sensors that measure system parameters, such as substrate temperature, chamber atmospheric pressure, and the like, may also provide information to the controller 320.
To facilitate control of the processing system 300 described above, the CPU 322 may be one of any form of general purpose computer processor that may be used in an industrial environment, such as a Programmable Logic Controller (PLC), to control various chambers and sub-processors. Memory 324 is coupled to CPU 322 and memory 324 is non-transitory and may be one or more of readily available memory, such as Random Access Memory (RAM), Read Only Memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. The support circuits 326 are coupled to the CPU 322 for supporting the processor in a conventional manner. The charged species generation, heating, and other processes are generally stored in the memory 324, typically as software routines. The software routines may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by CPU 322.
Memory 324 is in the form of a computer-readable storage medium containing instructions that, when executed by CPU 322, facilitate the operation of processing system 300. The instructions in memory 324 are in the form of a program product, such as a program, that implements the methods of the present disclosure. The program code can conform to any of a number of different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program of the program product defines functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks permanently storing information thereon that is readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory); and (ii) writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.
The methods discussed above may not rely solely on the processing system 300. For example, one or more blocks (such as block 120 or sub-block 114) may be performed in a process chamber external to the processing system 300.
One or more embodiments of the present disclosure relate to a low temperature method for depositing tungsten. Some embodiments of the present disclosure selectively deposit tungsten on a metal surface relative to a dielectric surface.
Some embodiments of the present disclosure advantageously provide methods of depositing tungsten that provide films with lower roughness, lower stress, and/or lower impurities. Some embodiments of the present disclosure provide methods of depositing tungsten that are performed at lower temperatures to facilitate applications requiring low thermal budgets.
Disclosed herein are methods for depositing tungsten. In some embodiments, the methods disclosed herein correspond to block 118 described above. In some embodiments, the tungsten deposited by the methods disclosed herein corresponds to the metal 220 described above.
An exemplary method includes exposing a substrate to hydrogen gas (H) 2 ) Flowing and exposing the substrate to a tungsten precursor flow while exposing the substrate to a hydrogen gas flow.
In some embodiments, the hydrogen stream and the tungsten precursor stream are both continuous. The continuous flow of both hydrogen and tungsten precursors should be understood by those skilled in the art to correspond to a Chemical Vapor Deposition (CVD) process. In some embodiments, the tungsten precursor flow is pulsed and the hydrogen flow is continuous. A pulsed flow of a tungsten precursor and a continuous flow of hydrogen gas should be understood by those skilled in the art as corresponding to a pulsed CVD process.
As described above, in some embodiments, the method may begin by heat soaking the substrate in hydrogen (H) gas 2 ) In the environment. In some embodiments, the heat soaking in a hydrogen ambient may be performed after the deposition of tungsten. In some embodiments, the method includes depositing a first amount of tungsten, performing a thermal soak, and depositing a second amount of tungsten. In some embodiments, the heat soaking is performed at a temperature in the range of about 250 ℃ to about 600 ℃, in the range of about 300 ℃ to about 500 ℃, in the range of about 300 ℃ to about 400 ℃, or in the range of about 400 ℃ to about 500 ℃.
In some embodiments, the methods disclosed herein are performed at relatively low temperatures. As described above, in some embodiments, the substrate is maintained at a temperature in the range of about 200 ℃ to about 500 ℃. In some embodiments, the substrate is maintained at a temperature in the range of about 200 ℃ to about 400 ℃, in the range of about 250 ℃ to about 375 ℃, in the range of about 300 ℃ to about 350 ℃, or in the range of about 250 ℃ to about 350 ℃. In some embodiments, the substrate is maintained at a temperature of less than or equal to about 400 ℃, less than or equal to about 375 ℃, less than or equal to about 350 ℃, less than or equal to about 325 ℃, or less than or equal to about 300 ℃.
In some embodiments, the flow rate of the hydrogen and/or tungsten precursor is controlled. In some embodiments, the flow rate of the hydrogen gas is in a range of about 2000sccm to about 20000sccm, in a range of about 2000sccm to about 18000sccm, in a range of about 5000sccm to about 20000sccm, or in a range of about 10000sccm to about 20000 sccm. In some embodiments, the flow rate of the tungsten precursor is less than or equal to about 500sccm, less than or equal to about 200sccm, less than or equal to about 100sccm, or less than or equal to about 50 sccm.
In some embodiments, the ratio between the flow rate of the hydrogen gas and the flow rate of the tungsten precursor is controlled. In some embodiments, the ratio of the flow rate of hydrogen gas to the flow rate of tungsten precursor is greater than or equal to about 100:1, greater than or equal to about 200:1, greater than or equal to about 500:1, or greater than or equal to about 1,000:1, greater than or equal to about 5,000:1, or greater than or equal to about 10,000: 1. Without being bound by theory, it is believed that the beneficial results (low roughness, low stress, etc.) in the tungsten film are due to the surplus of hydrogen gas present within the processing chamber.
In some embodiments, the pressure of the process chamber is controlled. In some embodiments, the pressure of the chamber is maintained in a range of about 5Torr to about 50Torr, in a range of about 10Torr to about 50Torr, in a range of about 20Torr to about 50Torr, in a range of about 5Torr to about 20Torr, or in a range of about 5Torr to about 10 Torr. In some embodiments, the pressure is maintained at less than or equal to about 50 Torr.
The tungsten precursor may be any suitable precursor for depositing a tungsten film. In some embodiments, the tungsten precursor comprises a reactive tungsten species and a carrier gas. In some embodiments, the tungsten precursor comprises a reactive tungsten complex and a carrier gas. In some embodimentsWherein the tungsten precursor comprises WF 6 、W x Cl 5x 、WCl 6 Or W (CO) 6 One or more of (a).
In some embodiments, the tungsten precursor comprises WF 6 Or substantially from WF 6 And (4) forming. As used in this aspect, the tungsten precursor consists essentially of WF when greater than or equal to about 95%, greater than or equal to about 98%, greater than or equal to about 99%, or greater than or equal to about 99.5% of the reactive tungsten species on a molar basis do not have any carrier gas 6 And (4) forming.
In some embodiments, tungsten deposited by the disclosed methods has relatively low levels of impurities. In the tungsten precursor containing WF 6 Of those embodiments in which the deposited tungsten has a thickness of less than or equal to about 10 20 Atom/cm 3 Less than or equal to about 5x10 19 Atom/cm 3 Less than or equal to about 10 19 Atom/cm 3 Less than or equal to about 5x10 18 Atom/cm 3 Or less than or equal to about 10 18 Atom/cm 3 The fluorine content of (a).
In some embodiments, the surface roughness of the deposited tungsten is relatively low. In some embodiments, the root mean square roughness of the deposited tungsten is less than or equal to about 2nm, less than or equal to about 1.5nm, less than or equal to about 1nm, or less than or equal to about 0.5 nm.
In some embodiments, the stress of the deposited tungsten is relatively low. In some embodiments, the deposited tungsten has a stress of less than or equal to about 2000MPa, less than or equal to about 1500MPa, less than or equal to about 1200MPa, less than or equal to about 1000MPa, less than or equal to about 800MPa, less than or equal to about 500MPa, or less than or equal to about 200 MPa.
In some embodiments, the substrate comprises a plurality of exposed materials. In some embodiments, the substrate comprises a first material surface and a second material surface. As identified above, the first material surface may comprise a metal or metal alloy. In some embodiments, the metal is selected from one or more of copper, tungsten, cobalt, or ruthenium. Additionally, the second material surface may comprise one or more of a low dielectric constant dielectric, an oxide, silicon nitride, silicon oxynitride, and the like.
In some embodiments, the methods described herein deposit tungsten selectively on a first material surface relative to a second material surface. In other words, in some embodiments, a first thickness of tungsten is deposited on the first material surface and a second thickness of tungsten is deposited on the second material surface. The first thickness is greater than the second thickness. In some embodiments, the ratio of the first thickness to the second thickness is greater than or equal to about 100:1, greater than or equal to about 200:1, greater than or equal to about 250:1, greater than or equal to about 500:1, greater than or equal to about 700:1, or greater than or equal to about 1,000: 1.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims (20)

1. A method of depositing tungsten, the method comprising:
exposing the substrate to a hydrogen gas stream; and
exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen gas to deposit a tungsten layer on the substrate,
wherein the substrate is maintained at a temperature of less than or equal to about 350 ℃.
2. The method of claim 1, wherein the flow of hydrogen and the flow of tungsten precursor are both continuous.
3. The method of claim 1, wherein the flow of the tungsten precursor is pulsed and the flow of hydrogen gas is continuous.
4. The method of claim 1, wherein a ratio of the flow of hydrogen gas to the flow of tungsten precursor is greater than or equal to about 500: 1.
5. The method of claim 1, wherein the tungsten layer has a root mean square roughness of less than or equal to about 1 nm.
6. The method of claim 1, wherein the tungsten layer has a stress of less than or equal to about 1000 MPa.
7. The method of claim 1, wherein the tungsten precursor comprises WF 6 。
8. The method of claim 6, wherein the tungsten layer has less than or equal to about 10 19 Atom/cm 3 The fluorine concentration of (a).
9. A method of depositing tungsten, the method comprising:
exposing the substrate to a hydrogen gas stream; and
exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen gas,
wherein a ratio of the flow of hydrogen gas to the flow of tungsten precursor is greater than or equal to about 500: 1.
10. The method of claim 9, wherein the flow of hydrogen and the flow of tungsten precursor are both continuous.
11. The method of claim 9, wherein the flow of the tungsten precursor is pulsed and the flow of hydrogen gas is continuous.
12. The method of claim 1, wherein the tungsten layer has a root mean square roughness of less than or equal to about 1 nm.
13. The method of claim 1, wherein the tungsten layer has a stress of less than or equal to about 1000 MPa.
14. The method of claim 1, wherein the tungsten precursor comprises WF 6 。
15. The method of claim 6, wherein the tungsten layer has less than or equal to about 10 19 Atom/cm 3 The fluorine concentration of (a).
16. A method of selectively depositing tungsten, the method comprising:
exposing a substrate comprising a first material surface and a second material surface to a hydrogen gas stream; and
exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen gas to deposit a first thickness of tungsten on the first material surface and a second thickness of tungsten on the second material surface, a ratio of the first thickness to the second thickness being greater than or equal to about 200: 1.
17. The method of claim 16, wherein the substrate is maintained at a temperature of less than or equal to about 350 ℃.
18. The method of claim 16, wherein a ratio of the flow of hydrogen gas to the flow of tungsten precursor is greater than or equal to about 500: 1.
19. The method of claim 16, wherein the flow of hydrogen and the flow of tungsten precursor are both continuous.
20. The method of claim 16, wherein the flow of the tungsten precursor is pulsed and the flow of hydrogen gas is continuous.
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US8900999B1 (en) * 2013-08-16 2014-12-02 Applied Materials, Inc. Low temperature high pressure high H2/WF6 ratio W process for 3D NAND application
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