TW202206634A - Selective tungsten deposition at low temperatures - Google Patents

Abstract

Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.

Description

Selective Tungsten Deposition at Low Temperatures

Embodiments of the present disclosure generally relate to improved methods of forming interconnects. Additional embodiments of the present disclosure relate to methods of forming tungsten at low temperatures.

Reliably generating features below 100 nm and smaller is one of the key technical challenges for next generation very large scale integration (VLSI) and ultra-large-scale integration (ULSI) of semiconductor devices . However, as circuit technology pushes the limits, the shrinking size of VLSI and ULSI technologies has placed additional demands on processing power. Reliable formation of gate structures on substrates is important to the success of VLSI and ULSI and to continued efforts to increase circuit density and the quality of individual substrates and dies.

As the circuit density of next-generation components increases, the width of interconnects such as vias, trenches, contacts, gate structures, and other features, and the width of the dielectric material in between, has decreased to 45 nm and 32 nm. size or less, while the thickness of the dielectric layer remains substantially constant, resulting in an increase in the aspect ratio of the feature. To enable the fabrication of next-generation devices and structures, three-dimensional (3D) stacking of semiconductor wafers is often used to improve the performance of transistors. By arranging transistors in three dimensions instead of the conventional two dimensions, multiple transistors can be placed very close to each other in an integrated circuit (IC). 3D stacking of semiconductor wafers reduces wire lengths and keeps wire delays low. In manufacturing, 3D stacking of semiconductor wafers, a stepped structure is often used to allow multiple interconnect structures to be placed thereon, thereby forming a high density of vertical transistor elements.

Accordingly, there is a continuing need for improved methods for forming interconnects to reduce manufacturing cost, memory cell size, and power consumption of integrated circuits.

Tungsten films deposited by chemical vapor deposition (CVD) are known to have relatively high stress value roughness. Additionally, tungsten films deposited using tungsten hexafluoride are known to have relatively high levels of fluorine impurities. Relatively high levels of stress, roughness, and fluorine impurities often cause problems including, but not limited to, wafer bowing, structural deformation, voids and crevices in gap fill, and fluorine attack damage at interfaces.

Some methods that have been developed to overcome these problems rely on atomic layer deposition (ALD). However, ALD methods are typically performed at relatively high temperatures (generally greater than or equal to 400°C).

Thus, there is a need for a method of depositing tungsten that provides low roughness, low stress, and low impurities that also performs at lower temperatures.

One or more embodiments of the present disclosure relate to a method of depositing tungsten. The method includes exposing a substrate to a flow of hydrogen gas and exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen gas to deposit a tungsten layer on the substrate. The substrate is maintained at a temperature of less than or equal to about 350°C.

Additional embodiments of the present disclosure relate to a method of depositing tungsten. The method includes exposing the substrate to a flow of hydrogen gas and exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen gas. The ratio of hydrogen stream to tungsten precursor stream is greater than or equal to about 500:1.

Additional embodiments of the present disclosure relate to a method of selectively depositing tungsten. The method includes exposing a substrate comprising a first material surface and a second material surface to a flow of hydrogen gas and exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen to deposit a first thickness of tungsten on the first material surface and A second thickness of tungsten is deposited on the surface of the second material. The ratio of the first thickness to the second thickness is greater than or equal to about 200:1.

Before describing several exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

As used in this specification and the scope of the accompanying patent application, the term "substrate" refers to the surface, or a portion of a surface, on which a process operates. As will also be understood by those skilled in the art, unless the context clearly dictates otherwise, reference to a substrate may also refer to only a portion of the substrate. Furthermore, reference to depositing on a substrate may mean a bare substrate and a substrate on which one or more films or features are deposited or formed.

"Substrate" as used herein refers to any substrate or surface of material formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, the substrate surface on which processing may be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon Silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and/or bake the substrate surface. In addition to processing directly on the surface of the substrate itself, in this disclosure, as disclosed in more detail below, any of the disclosed film processing steps may also be performed on underlying layers formed on the substrate, and the term "substrate surface" is intended to include such as The context indicates such a lower layer. Thus, for example, where a film/layer or part of a film/layer has already been deposited on the substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

FIG. 1 is a flowchart illustrating one embodiment of a method 100 for forming interconnects on a substrate. FIGS. 2A-2G show cross-sectional views of the substrate prior to the method 100 of FIG. 1 and at various stages of the method 100 of FIG. 1 .

FIG. 2A shows a cross-sectional view of interconnect 200 prior to starting method 100 . In general, interconnect 200 includes multiple layers that can be used to form interconnect structures, such as dual damascene structures. Film stack 201 is formed on substrate 202 . Stack 201 includes dielectric layer 204 . As shown in FIG. 2A , a dielectric layer 204 is disposed on the substrate 202 and has a conductive layer 206 formed in and defined by the dielectric layer 204 . In one example, the dielectric layer 204 may be formed of one or more insulating materials, such as silicon oxide. In one example, conductive layer 206 may be formed of a conductive layer such as copper.

At block 102 , as shown in FIG. 2B , a dielectric barrier layer 208 is deposited on the substrate 202 . For example, as shown, a dielectric barrier layer 208 is deposited over both the dielectric layer 204 and the conductive layer 206 . Thus, the dielectric barrier layer 208 may form a uniform, uninterrupted layer over the dielectric layer 204 and the conductive layer 206 . The dielectric barrier layer 208 may be formed of a low dielectric constant material. For example, the dielectric barrier layer 208 may be a silicon carbon-containing layer (SiC), a nitrogen-doped silicon-containing carbon layer (SiCN), a silicon nitride layer, a metal nitride, or a metal oxide (eg, AlN, _AlOx , AlON) , or the like.

At block 104 , as shown in FIG. 2C , a dielectric layer 210 is deposited on the substrate 202 . For example, as shown, dielectric layer 210 is deposited over dielectric barrier layer 208 . Dielectric layer 210 may be substantially similar to dielectric layer 204 . In one embodiment, dielectric layer 210 may be formed of the same material as dielectric layer 204 . In another embodiment, the dielectric layer 210 may be formed of a different material than the dielectric layer 204 while maintaining the same low dielectric constant properties.

At block 106 , as shown in FIG. 2D , one or more vias 212 are formed in interconnect 200 to expose conductive layer 206 . For example, vias 212 may be formed through both dielectric layer 210 and dielectric barrier layer 208 to expose underlying conductive layer 206 . Generally, the through hole 212 has a width W1. In some embodiments, the width of each through hole 212 is uniform over the entire length of the through hole 212 . In other embodiments, the width of each through hole 212 may gradually change from the top of the through hole 212 to the bottom of the through hole 212 .

At block 108 , one or more trenches 214 are formed in interconnect 200 as shown in FIG. 2E . One or more trenches 214 may be formed in the dielectric layer 210 . The trenches 214 are configured to widen at least a portion of the vias 212 . In some embodiments, block 108 may be performed before block 106 , ie, trenches 214 may be formed before vias 212 . In other embodiments, such as the described embodiments, trenches 214 are formed after vias 212 are formed.

In a conventional fabrication scheme, a "fill process" is performed to fill the vias 212 and the trenches 214 are filled with a metal material to form the interconnect 200 . For example, a metal such as copper may be used to fill both vias 212 and trenches 214 . Filling both vias 212 and trenches 214 with the same material has been found to result in high interconnect resistance, which can lead to RC delays and IR drops in semiconductor wafers.

Interconnect resistance on the die affects die speed due to RC delay and power management by IR drop. As design rules continue to shrink, interconnect resistance reduction is an increasingly important priority. In particular, with short interconnect lines, smaller via sizes less than 40 nm, and multilayer wiring stacked with vias, the resistance of vias (eg, via 212 ) has a significant effect on the overall resistance, That is, the resistance through the via is higher than through the wire. Thus, reducing via resistance has become increasingly important for achieving wafer performance.

Conventional via formation results in high resistance due to the materials used in process integration. Following block 108, via filling is completed with metal barriers, liners, and bulk fill material in conventional methods. Metal barriers and liners are used for reliability and gap fill robustness. However, when deposited at the bottom of the via, the materials used for the barrier and liner layers can result in high via resistance due to their high resistivity. For example, conventional dual damascene copper fills can be formed from a TaN barrier layer (deposited via a physical vapor deposition (PVD) process), a Ta metal liner layer deposited on the barrier layer (eg, PVD or chemical vapor deposition (CVD) process), and Cu seed/electroplating layer deposited on the metal liner layer. Depending on the via size, the barrier and pad weights are approximately 50% to 90% greater than the total via resistance. Therefore, removing the metal barrier and liner layers can help reduce via resistance. At the same time, however, potential risks may occur due to the elimination of barrier and liner layers. For example, interconnects will still need to meet reliability aspects, including avoiding dielectric breakdown and metal electromigration. Furthermore, suitable metal fill process integration in dual damascene structures may be required to improve both via resistance and line resistance.

Accordingly, the discussion below proposes a selective fill approach (eg, a W fill approach), which illustrates lower via resistance while meeting integration and reliability requirements. An interface treatment (discussed below in conjunction with at least block 110 ) and a fill process (discussed below in conjunction with at least block 118 ) are developed to selectively grow metal material (eg, W) from the bottom of the via without damaging underlying metal layers (eg, Cu, W, Co, and the like) and surrounding dielectrics (eg, low-k dielectrics, oxides, and the like). Accordingly, the following discussion provides one or more techniques for reducing via resistance. After the via fill, the damascene fill will continue, which contributes to the equivalent line resistance.

The improved method 100 includes using selective metal via fill to reduce resistance and meet reliability (interaction with sidewall dielectric 204 and exposed conductive layer 206 ) and line resistance requirements. At block 110 , one or more preprocessing processes are performed on interconnect 200 to prepare interconnect 200 to receive selective metal via 212 fill. For example, block 110 may include sub-blocks 112-116.

At sub-block 112 , interconnect 200 undergoes a first processing process for exposed portions of conductive layer 206 in via 212 . For example, when vias 212 are deposited with a first metal, a first pretreatment process is used to prepare exposed portions of conductive layer 206 for bottom-up growth. A remote plasma cleaning process can be used to pretreat interconnects. Interconnect 200 may be moved to a preprocessing chamber where interconnect 200 undergoes a cleaning process. For example, the interconnect may undergo a cleaning process between about 250-350°C, using a _H2 /Ar mixture, at a temperature of about 1-10 Torr. In other embodiments, a slight bias energy may be applied to facilitate oxide separation without metal sputtering. For example, 0-200 W of energy can be applied to the pretreatment chamber.

At sub-block 114, interconnect 200 undergoes a second preprocessing process. The second process is used to passivate the sidewalls 216 of the via to minimize undesired sidewall growth. As mentioned above, the dielectric layer 204 may be formed of a low dielectric constant material. Therefore, the second pretreatment process helps to seal the surface pores of the dielectric layer 204 and protect the dielectric layer 204 from the immersion precursors. In one embodiment, the second pretreatment process may be a thermal precursor soak at high temperature (eg, 200-400°C). In some examples, precursors that can be used are tetramethylsilane (TMS), dimethylaminotrimethylsilane (DMATMS), and the like. In one embodiment, the second pretreatment process in sub-block 114 may further include adding ultraviolet (UV) energy to the precursor soak process by subjecting the interconnect 200 to a UV bake process.

In some embodiments, block 110 may include sub-block 116 . At block 116, interconnect 200 undergoes optional post-processing cleaning. For example, an optional pre-cleaning can be used in the case of oxidation or residue growth at the bottom of the via 212 . An optional _pretreatment wash uses a peroxide (eg, H2O2 ₎ containing chemistry with an alkaline pH tuning to slightly remove residue.

At block 118, metal 220 selectively fills vias 212 after the pretreatment process (block 110) as shown in FIG. 2F. For example, the material of metal 220 is deposited in via 212 up to point 222 where via 212 intersects trench 214 . The metal 220 used may be any suitable metal material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), or the like. The main requirement for metal 220 is that it be a different material than the subsequent metal deposited in trench 214 . Selective deposition of metal 220 in the via helps to reduce via resistance and meet reliability and line resistance requirements.

Metal 220 may be deposited using a chemical vapor deposition (CVD) process. The CVD process may include H ₂ pre-soak at high temperature (eg, 350-500°C). The CVD process can be performed at a temperature of about 200-500°C using a low flow rate (eg, 2-100 seem) metal-containing precursor (eg, WF ₆ ) in a high volume H ₂ ambient. The combination of flow rate, pressure, and temperature helps reduce the morphology of the metal 220 when deposited. Prior to depositing the material for metal 220, conventional nucleation layers can be applied for initial 1-3 nm nucleation. The total growth is controlled by process time, pressure, and precursor flow to fill the vias 212 uniformly.

At block 120 , as shown in FIG. 2G , a second metal 224 is deposited in each trench 214 . For example, a second metal 224 is deposited from point 222 to the top of trench 214 . The second metal 224 used may be any suitable metal material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), and the like. The main requirement for the second metal 224 is that it be a different material than that of the first metal 220 deposited in the vias 212 . The second metal 224 may be deposited using a CVD process. Separating conventional metal filling of a single metal material into a two-step process involving a first metal 220 deposited in the via 212 and a second metal 224 deposited in the trench 214 helps to reduce the penetration of the through via 212 resistance.

In some embodiments, a barrier seed layer (not shown) may be deposited over the first metal 220 prior to depositing the second metal 224 . For example, if the second metal 224 is copper, the barrier seed layer may be a copper barrier seed layer.

In some embodiments, method 100 may include optional block 119 performed prior to depositing second metal 224 . At block 119 , the interconnect 200 may undergo a pretreatment process prior to the second metal 224 . A pretreatment process can be used to remove any oxides that may have formed on the top surface of the first metal 220 . For example, interconnect 200 may undergo a similar process as subblock 112 .

FIG. 3 shows a multi-chamber processing system 300 . Processing system 300 may include load lock chambers 302 , 304 , robot 306 , transfer chamber 308 , processing chambers 310 , 312 , 314 , 316 , 318 , 328 , and controller 320 . The load lock chambers 302 , 304 allow substrates (not shown) to be transferred into and out of the processing system 300 . The load lock chambers 302, 304 may evacuate substrates introduced into the processing system 300 to maintain a vacuum seal. Robot 306 may transfer substrates between load lock chambers 302 , 304 and processing chambers 310 , 312 , 314 , 316 , 318 , and 328 . Robot 306 may also transfer substrates between load lock chambers 302 , 304 and transfer chamber 308 .

Each processing chamber 310, 312, 314, 316, 318, and 328 may be equipped to perform multiple substrate operations, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), PVD, etching, pre-cleaning, removal gas, heating, orientation, or other substrate processes. Additionally, each processing chamber 310, 312, 314, 316, 318, and 328 may be equipped to deposit a dielectric barrier layer, deposit a dielectric layer, form one or more vias and trenches in the stack, perform an or A plurality of pre-cleaning processes, depositing a first metal material layer, and depositing a second metal material layer.

Controller 320 may be configured to operate all aspects of processing system 300, such as the method disclosed in FIG. For example, the controller 320 may be configured to control the method of forming the interconnects on the substrate. Controller 320 includes a programmable central processing unit (CPU) 322 operable with memory 324 and mass storage elements, an input control unit, and various components coupled to the processing system to facilitate processing of substrates. Controlled display units (not shown), such as power supplies, clocks, cache memory, input/output (I/O) circuits, and pads. Controller 320 also includes hardware for monitoring substrate processing via sensors in processing system 300, including sensors that monitor precursor, process gas, and purge gas flow. Other sensors that measure system parameters such as substrate temperature, chamber atmospheric pressure, and the like may also provide information to controller 320 .

To facilitate control of the processing system 300 described above, the CPU 322 may be one of any form of general-purpose computer processor that can be used in an industrial environment such as a programmable logic controller ; PLC)) is used to control each chamber and sub-processor. Memory 324 is coupled to CPU 322 and is one or more of non-transitory and readily available memories, such as random access memory (RAM), read-only memory ( read only memory; ROM), floppy disk drive, hard disk, or any other form of digital storage (local or remote). Support circuitry 326 is coupled to CPU 322 for supporting the processor in a conventional manner. Charged species generation, heating, and other processes are generally stored in memory 324, typically in software routines. The software routines may also be stored and/or executed by a second CPU (not shown) located remotely from the hardware controlled by CPU 322 .

Memory 324 is in the form of a computer-readable storage medium containing instructions that, when executed by CPU 322 , facilitate the operation of processing system 300 . The instructions in memory 324 are in the form of a program product, such as a program that implements the methods of the present disclosure. The code can conform to any of several different programming languages. In one example, the present disclosure can be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The programs of the program product define the functionality of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (eg, a read-only memory device within a computer, such as a CD-ROM readable by a CD-ROM drive on which information is permanently stored disks, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory); and (ii) a writable storage medium on which variable information is stored (for example, in a magnetic disk drive or hard disk drive) floppy disk or any type of solid-state random access semiconductor memory). Such computer-readable storage media are embodiments of the present disclosure when carrying computer-readable instructions that direct the functions of the methods described herein.

The methods discussed above may not only rely on processing system 300 . For example, one or more blocks, such as block 120 or sub-block 114 , may be performed in a processing chamber external to processing system 300 .

One or more embodiments of the present disclosure relate to low temperature methods for depositing tungsten. Some embodiments of the present disclosure selectively deposit tungsten on metal surfaces relative to dielectric surfaces.

Some embodiments of the present disclosure advantageously provide methods of depositing tungsten that provide films with lower roughness, lower stress, and/or lower impurities. Some embodiments of the present disclosure provide methods of depositing tungsten that are performed at lower temperatures to facilitate applications requiring low thermal budgets.

This article discloses a method for depositing tungsten. In some embodiments, the methods disclosed herein correspond to block 118 described above. In some embodiments, the tungsten deposited by the methods disclosed herein corresponds to the metal 220 described above.

Exemplary methods include exposing the substrate to a flow of hydrogen (H ₂ ) and exposing the substrate to a flow of a tungsten precursor while exposing the substrate to the flow of hydrogen.

In some embodiments, both the hydrogen flow and the tungsten precursor flow are continuous. The continuous flow of both hydrogen and tungsten precursors should be understood by those skilled in the art to correspond to a chemical vapor deposition (CVD) process. In some embodiments, the tungsten precursor flow is pulsed and the hydrogen flow is continuous. The pulsed flow of the tungsten precursor and the continuous flow of hydrogen should be understood by those skilled in the art to correspond to a pulsed CVD process.

As described above, in some embodiments, the method may begin by thermally immersing the substrate in a hydrogen ( _H2 ) environment. In some embodiments, thermal soaking in a hydrogen atmosphere may be performed after depositing tungsten. In some embodiments, the method includes depositing a first amount of tungsten, performing a thermal soak, and depositing a second amount of tungsten. In some embodiments, the heat soak is in the range of about 250°C to about 600°C, in the range of about 300°C to about 500°C, in the range of about 300°C to about 400°C, or in the range of about 400°C to about 400°C Performed at temperatures in the range of about 500°C.

In some embodiments, the methods disclosed herein are performed at relatively low temperatures. As described above, in some embodiments, the substrate is maintained at a temperature in the range of about 200°C to about 500°C. In some embodiments, in some embodiments, the substrate is maintained in a range from about 200°C to about 400°C, in a range from about 250°C to about 375°C, in a range from about 300°C to about 350°C, or at a temperature in the range of about 250°C to about 350°C. In some embodiments, the substrate is maintained at a temperature of less than or equal to about 400°C, less than or equal to about 375°C, less than or equal to about 350°C, less than or equal to about 325°C, or less than or equal to about 300°C.

In some embodiments, the flow rate of the hydrogen and/or tungsten precursor is controlled. In some embodiments, the flow rate of hydrogen gas is in the range of about 2000 sccm to about 20000 sccm, in the range of about 2000 sccm to about 18000 sccm, in the range of about 5000 sccm to about 20000 sccm, or in the range of about 10000 sccm sccm to about 20,000 sccm. In some embodiments, the flow rate of the tungsten precursor is less than or equal to about 500 seem, less than or equal to about 200 seem, less than or equal to about 100 seem, or less than or equal to about 50 seem.

In some embodiments, the ratio is controlled between the flow rate of the hydrogen gas and the flow rate of the tungsten precursor. In some embodiments, the ratio of the flow rate of hydrogen gas to the flow rate of the tungsten precursor is greater than or equal to about 100:1, greater than or equal to about 200:1, greater than or equal to about 500:1, or greater than or equal to about 1,000: 1. Greater than or equal to about 5,000:1, or greater than or equal to about 10,000:1. Without being bound by theory, it is believed that the beneficial results (low roughness, low stress, etc.) in the tungsten film are due to the surplus of hydrogen gas present within the processing chamber.

In some embodiments, the pressure of the processing chamber is controlled. In some embodiments, the pressure of the chamber is maintained in the range of about 5 Torr to about 50 Torr, in the range of about 10 Torr to about 50 Torr, in the range of about 20 Torr to about 50 Torr, in the range of about In the range of 5 Torr to about 20 Torr, or in the range of about 5 Torr to about 10 Torr. In some embodiments, the pressure is maintained at less than or equal to about 50 Torr.

The tungsten precursor can be any suitable precursor for depositing tungsten films. In some embodiments, the tungsten precursor includes a reactive tungsten species and a carrier gas. In some embodiments, the tungsten precursor includes a reactive tungsten complex and a carrier gas. _In some embodiments, the tungsten precursor includes one or more of _WF6 , _WxCl5x , _WCl6 , or W(CO) ₆ .

_{In some embodiments, the tungsten precursor comprises or consists essentially of WF 6 .} As used in this aspect, when the reactive tungsten species is greater than or equal to about 95%, greater than or equal to about 98%, greater than or equal to about 99%, or greater than or equal to about 99.5% on a molar basis without any carrier gas , the tungsten precursor consists essentially of WF ₆ .

In some embodiments, tungsten deposited by the disclosed methods has relatively low levels of impurities. In those embodiments wherein the tungsten precursor comprises WF ₆ , the deposited tungsten has less than or equal to about 10 ²⁰ atoms/cm ³ , less than or equal to about 5× ^{10 19} atoms/cm ³ , less than or equal to about 10 ¹⁹ atoms/cm 3 cm ³ , less than or equal to about 5× ^{10 18} atoms/cm ³ , or less than or equal to about 10 ¹⁸ atoms/cm ³ of fluorine content.

In some embodiments, the surface roughness of the deposited tungsten is relatively low. In some embodiments, the rms roughness of the deposited tungsten is less than or equal to about 2 nm, less than or equal to about 1.5 nm, less than or equal to about 1 nm, or less than or equal to about 0.5 nm.

In some embodiments, the stress of the deposited tungsten is relatively low. In some embodiments, the deposited tungsten has a stress of less than or equal to about 2000 MPa, less than or equal to about 1500 MPa, less than or equal to about 1200 MPa, less than or equal to about 1000 MPa, less than or equal to about 800 MPa, less than or equal to about 800 MPa About 500 MPa, or less than or equal to about 200 MPa.

In some embodiments, the substrate includes multiple exposed materials. In some embodiments, the substrate includes a first material surface and a second material surface. As identified above, the first material surface may comprise a metal or metal alloy. In some embodiments, the metal is selected from one or more of copper, tungsten, cobalt, or ruthenium. Additionally, the second material surface may include one or more of low-k dielectrics, oxides, silicon nitrides, silicon oxynitrides, and the like.

In some embodiments, the methods described herein selectively deposit tungsten on the surface of the first material relative to the surface of the second material. In other words, in some embodiments, a first thickness of tungsten is deposited on the surface of the first material and a second thickness of tungsten is deposited on the surface of the second material. The first thickness is greater than the second thickness. In some embodiments, the ratio of the first thickness to the second thickness is greater than or equal to about 100:1, greater than or equal to about 200:1, greater than or equal to about 250:1, greater than or equal to about 500:1, greater than or equal to About 700:1, or greater than or equal to about 1,000:1.

Although the foregoing relates to embodiments of the present invention, other and further embodiments of the present invention may be devised without departing from its essential scope, which is determined by the following claims.

Reference throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means a particular feature, structure, material, or characteristic described in connection with the embodiments Included in at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one or more embodiments", "in some embodiments", "in one embodiment" or "in an embodiment" in various places throughout this specification do not Must refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

100: Method 102: Blocks 104: Blocks 106: Blocks 108: Blocks 110: Blocks 112: Square 114: Square 116: Blocks 118: Square 119: Blocks 120: Square 200: Interconnect 202: Substrate 204: Dielectric Layer 206: Conductive layer 208: Dielectric barrier layer 210: Dielectric Layer 212: Through hole 214: Groove 216: Sidewall 220: Metal 224: Second Metal 300: Multi-chamber processing system 302: Load lock chamber 304: Load lock chamber 306: Robot 308: Transfer Chamber 310: Processing Chamber 312: Processing Chamber 314: Processing Chamber 316: Processing Chamber 318: Processing Chamber 320: Controller 322: Programmable Central Processing Unit (CPU) 324: memory 326: Support circuit 328: Processing Chamber

In order to enable a detailed understanding of the manner in which the above-described features of the present disclosure are used, a more detailed description of the present disclosure, briefly summarized above, can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the appended drawings illustrate only common embodiments of the disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

FIG. 1 illustrates a method of forming an interconnect in accordance with one or more embodiments;

FIGS. 2A-2G illustrate cross-sectional side views of interconnects formed on a substrate at various stages of the method of FIG. 1 in accordance with one or more embodiments;

Figure 3 illustrates a multi-chamber processing system on which the method of Figure 1 may be practiced, in accordance with one or more embodiments.

To facilitate understanding, the same reference numerals have been used, where possible, to identify the same elements that are common to the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated in other embodiments without further recitation.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

Domestic storage information (please note in the order of storage institution, date and number) without Foreign deposit information (please note in the order of deposit country, institution, date and number) without

200: Interconnect

202: Substrate

204: Dielectric Layer

206: Conductive layer

208: Dielectric barrier layer

210: Dielectric Layer

220: Metal

224: Second Metal

Claims (20)

A method of depositing tungsten, the method comprising the steps of: exposing a substrate to a stream of hydrogen; and exposing the substrate to a stream of a tungsten precursor while exposing the substrate to the hydrogen stream to deposit a tungsten layer on the substrate, wherein the substrate is maintained at a temperature of less than or equal to about 350°C. The method of claim 1, wherein the flow of the hydrogen gas and the flow of the tungsten precursor are both continuous. The method of claim 1, wherein the flow of the tungsten precursor is pulsed and the hydrogen flow is continuous. The method of claim 1, wherein a ratio of the flow of the hydrogen gas to the flow of the tungsten precursor is greater than or equal to about 500:1. The method of claim 1, wherein the tungsten layer has a root mean square roughness of less than or equal to about 1 nm. The method of claim 1, wherein the stress of the tungsten layer is less than or equal to about 1000 MPa. The method of claim 1, wherein the tungsten precursor comprises _WF6 . The method of claim 6, wherein the tungsten layer has a fluorine concentration of less than or equal to about 10 ¹⁹ atoms/cm ³ . A method of depositing tungsten, the method comprising the steps of: exposing a substrate to a stream of hydrogen; and exposing the substrate to a stream of a tungsten precursor while exposing the substrate to the hydrogen stream, wherein a ratio of the flow of hydrogen gas to the flow of the tungsten precursor is greater than or equal to about 500:1. The method of claim 9, wherein the flow of the hydrogen gas and the flow of the tungsten precursor are both continuous. The method of claim 9, wherein the flow of the tungsten precursor is pulsed and the hydrogen flow is continuous. The method of claim 1, wherein the tungsten layer has a root mean square roughness of less than or equal to about 1 nm. The method of claim 1, wherein the stress of the tungsten layer is less than or equal to about 1000 MPa. The method of claim 1, wherein the tungsten precursor comprises _WF6 . The method of claim 6, wherein the tungsten layer has a fluorine concentration of less than or equal to about 10 ¹⁹ atoms/cm ³ . A method of selectively depositing tungsten, the method comprising the steps of: exposing a substrate including a first material surface and a second material surface to a flow of hydrogen; and Expose the substrate to a stream of a tungsten precursor while exposing the substrate to the hydrogen stream to deposit a first thickness of tungsten on the first material surface and a second thickness on the second material surface of tungsten, a ratio of the first thickness to the second thickness is greater than or equal to about 200:1. The method of claim 16, wherein the substrate is maintained at a temperature of less than or equal to about 350°C. The method of claim 16, wherein a ratio of the flow of hydrogen gas to the flow of the tungsten precursor is greater than or equal to about 500:1. The method of claim 16, wherein the flow of the hydrogen gas and the flow of the tungsten precursor are both continuous. The method of claim 16, wherein the flow of the tungsten precursor is pulsed and the hydrogen flow is continuous.

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