CN105493188A - 用于使用感测电路执行比较运算的设备与方法 - Google Patents

用于使用感测电路执行比较运算的设备与方法 Download PDF

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CN105493188A
CN105493188A CN201480044584.0A CN201480044584A CN105493188A CN 105493188 A CN105493188 A CN 105493188A CN 201480044584 A CN201480044584 A CN 201480044584A CN 105493188 A CN105493188 A CN 105493188A
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特洛伊·A·曼宁
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Micron Technology Inc
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    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
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    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
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    • G11C15/043—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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Abstract

本发明包含与使用感测电路执行比较及/或报告运算有关的设备及方法。一种实例方法可包含将存储器阵列的输入/输出IO线充电到一电压。所述方法可包含确定存储于所述存储器阵列中的数据是否匹配比较值。所存储的数据是否匹配比较值的所述确定可包含激活所述存储器阵列的若干存取线。所述确定可包含感测耦合到所述若干存取线的若干存储器单元。所述确定可包含感测所述IO线的所述电压是否响应于对应于所述若干存储器单元的选定解码线的激活而改变。

Description

用于使用感测电路执行比较运算的设备与方法
技术领域
本发明大体上涉及半导体存储器及方法，且更特定来说，涉及与使用感测电路执行比较运算有关的设备及方法。
背景技术
存储器装置通常被提供为计算机或其它电子系统中的内部半导体集成电路。存在许多不同类型的存储器，包含易失性存储器及非易失性存储器。易失性存储器可需要电源以维持其数据(举例来说，主机数据、错误数据等等)且包含随机存取存储器(RAM)、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、同步动态随机存取存储器(SDRAM)及晶闸管随机存取存储器(TRAM)以及其它。非易失性存储器可在未供电时通过保持所存储的数据而提供永久性数据，且可包含NAND快闪存储器、NOR快闪存储器及电阻可变存储器(例如相变随机存取存储器(PCRAM))、电阻式随机存取存储器(RRAM)及磁阻式随机存取存储器(MRAM)(例如自旋力矩转移随机存取存储器(STTRAM))以及其它。
电子系统通常包含若干处理资源(举例来说，一或多个处理器)，其可检索及执行指令且将所执行指令的结果存储到适合位置。处理器可包括若干功能单元(例如算术逻辑单元(ALU)电路、浮点单元(FPU)电路及/或组合逻辑块)，举例来说，所述功能单元可用以通过对数据(举例来说，一或多个操作数)执行逻辑运算(例如AND、OR、NOT、NAND、NOR及XOR逻辑运算)而执行指令。举例来说，功能单元电路(FUC)可用以对操作数执行算术运算，例如加法、减法、乘法及/或除法。
在将指令提供到FUC以供执行的过程中可涉及电子系统中的若干组件。指令可由(例如)处理资源(例如控制器及/或主机处理器)产生。数据(举例来说，将对其执行指令的操作数)可存储于可由FUC存取的存储器阵列中。可从所述存储器阵列检索指令及/或数据且可在FUC开始对所述数据执行指令之前序列化及/或缓冲指令及/或数据。此外，因为可通过FUC以一或多个时钟循环执行不同类型的运算，所以也可序列化及/或缓冲指令及/或数据的中间结果。
执行指令(举例来说，作为程序执行的部分)可涉及执行运算(例如比较运算)，且可将结果提供(举例来说，报告)到处理资源作为(举例来说)算法的执行流程的部分。此类比较及报告功能性可启用(例如)“如果-则-否则”程序化流程，此通常是程序执行的部分。
附图说明
图1是根据本发明的若干实施例的呈包含存储器装置的计算系统的形式的设备的框图。
图2说明根据本发明的若干实施例的耦合到感测电路的存储器阵列的一部分的示意图。
图3说明根据本发明的若干实施例的耦合到感测电路的存储器阵列的一部分的示意图。
图4说明根据本发明的若干实施例的用于执行比较运算的方法的实例。
具体实施方式
本发明包含与使用感测电路执行比较运算有关的设备及方法。一种实例方法包括将存储器阵列的输入/输出(IO)线(举例来说，本地IO线(LIO线))充电(举例来说，预充电)到一电压(举例来说，一预充电电压)。所述方法可包含通过激活所述存储器阵列的若干存取线及感测耦合到所述若干存取线的若干存储器单元来确定存储于所述存储器阵列中的数据是否匹配比较值。所述方法可包含感测所述LIO线的所述电压(举例来说，预充电电压)是否响应于对应于所述若干存储器单元的选定解码线(举例来说，列解码线)的激活而改变。在本发明中，“线”意味着至少两个节点之间的可操作耦合。
本发明的若干实施例可提供益处，例如与确定比较值(举例来说，特定数据值及/或数据值集合)与存储于存储器阵列中的数据值之间是否存在匹配相关联的经改进比较及报告功能性。例如，若干实施例可实现识别特定数据是否存储于若干存储器单元中而(例如)不经由总线(举例来说，数据总线、地址总线、控制总线)将数据传送出存储器阵列及感测电路。可将存储于阵列中的数据是否匹配比较值的确定报告到(例如)控制电路(举例来说，到裸片上控制器及/或到外部主机)。可将存储于阵列中的数据是否匹配比较值的确定报告到存储器阵列中。此类比较及报告功能性可与执行若干逻辑运算(举例来说，AND、NOT、NOR、NAND、XOR等等)相关联。然而，实施例不受限制于这些实例。
而且，与各种处理资源相关联的电路(例如FUC)可能不符合与存储器阵列相关联的间距规则。举例来说，存储器阵列的单元可具有4F2或6F2单元大小，其中“F”是对应于单元的特征大小。与先前系统的FUC相关联的装置(举例来说，逻辑门)可能无法形成于与存储器单元的间距上，此可影响(举例来说)芯片大小及/或存储器密度。
在本发明的以下详细描述中，参考形成本发明的一部分的附图，且在附图中以说明的方式展示可如何实践本发明的一或多个实施例。足够详细地描述这些实施例以使所属领域的一般技术人员能够实践本发明的实施例，且应理解，在不脱离本发明的范围的情况下，可利用其它实施例且可进行过程、电气及/或结构改变。如本文中所使用，标示符“N”、“P”、“R”等等(尤其关于图式中的元件符号)可指示：可包含如此指定的若干特定特征。如本文中所使用，“若干”特定事物可指代此类事物中的一或多者(举例来说，若干存储器阵列可指代一或多个存储器阵列)。
本文中的图遵循编号规定，其中首位数字或前几位数字对应于图式图号且剩余数字识别图式中的元件或组件。可通过使用类似数字识别不同图之间的类似元件或组件。举例来说，130可参考图1中的元件“30”，且类似元件在图2中可被称为230。如将了解，可添加、交换及/或消除在本文中的各种实施例中所展示的元件以便提供本发明的若干额外实施例。另外，如将了解，图中所提供的元件的比例及相对尺寸希望说明本发明的某些实施例，且不应在限制性意义上理解。
图1是根据本发明的若干实施例的呈包含存储器装置120的计算系统100的形式的设备的框图。如本文中所使用，存储器装置120、存储器阵列130及/或感测电路150也可被单独视为“设备”。
系统100包含主机110，主机110耦合到包含存储器阵列130的存储器装置120。主机110可为主机系统，例如个人膝上型计算机、桌上型计算机、数码相机、移动电话或存储卡读卡器，以及各种其它类型的主机。主机110可包含系统主机板及/或背板且可包含若干处理资源(举例来说，一或多个处理器、微处理器或一些其它类型的控制电路)。系统100可包含单独的集成电路或主机110及存储器装置120两者可都在相同的集成电路上。系统100可为(例如)服务器系统及/或高性能计算(HPC)系统及/或高性能计算(HPC)系统的部分。尽管图1中展示的实例说明具有范纽曼(VonNeumann)架构的系统，但本发明的实施例可以非范纽曼架构(举例来说，图灵机(Turingmachine))实施，所述非范纽曼架构可能不包含通常与范纽曼架构相关联的一或多个组件(举例来说，CPU、ALU等等)。
为明确起见，系统100已经简化以集中在与本发明特定相关的特征上。存储器阵列130可为(例如)DRAM阵列、SRAM阵列、STTRAM阵列、PCRAM阵列、TRAM阵列、RRAM阵列、NAND快闪阵列及/或NOR快闪阵列。阵列130可包括布置成通过存取线(本文中可称为行线、字线或选择线)耦合的行及通过感测线(本文中可称为数字线或数据线)耦合的列的存储器单元。尽管图1中展示单一阵列130，但实施例并不如此受限制。例如，存储器装置120可包含若干阵列130(举例来说，若干DRAM单元库)。结合图2及3描述实例DRAM阵列。
存储器装置120包含用以锁存越过I/O总线156(举例来说，数据总线)经由I/O电路144提供的地址信号的地址电路142。由行解码器146及列解码器152接收及解码地址信号以存取存储器阵列130。可通过使用感测电路150感测感测线上的电压及/或电流改变来从存储器阵列130读取数据。感测电路150可从存储器阵列130读取及锁存数据页(举例来说，行)。I/O电路144可用于越过I/O总线156与主机110进行双向数据通信。写入电路148用以将数据写入到存储器阵列130。
控制电路140解码由控制总线154从主机110提供的信号。这些信号可包含用以控制对存储器阵列130执行的控制操作(包含数据读取、数据写入及数据擦除操作)的芯片启用信号、写入启用信号及地址锁存信号。在各种实施例中，控制电路140负责执行来自主机110的指令。控制电路140可为状态机、定序器或某一其它类型的控制器(举例来说，裸片上控制器)。
下文结合图2及3进一步描述感测电路150的实例。例如，在若干实施例中，感测电路150可包括若干感测放大器(举例来说，图2中展示的感测放大器206-1……206-P或图3中展示的感测放大器306)及若干计算组件(举例来说，图3中展示的计算组件331)，所述计算组件可包括累加器且可用以(举例来说，对与互补感测线相关联的数据)执行比较及报告运算。在若干实施例中，感测电路(举例来说，150)可用以使用存储于阵列130中的数据作为输入来执行比较及报告运算，且将逻辑运算的结果存储回到阵列130而未经由感测线地址存取传送(举例来说，未激发列解码信号)。因而，各种计算功能可在阵列130内使用感测电路150执行而非由感测电路外部的处理资源(举例来说，由与主机110相关联的处理器及/或位于装置120上(举例来说，在控制电路140上或别处)的其它处理电路，例如ALU电路)执行。在各种先前方法中，(例如)与操作数相关联的数据将经由感测电路从存储器读取且经由本地I/O线被提供到外部ALU电路。外部ALU电路将使用操作数执行计算函数且结果将经由本地I/O线传送回到阵列。相比之下，在本发明的若干实施例中，感测电路(举例来说，150)可经配置以对存储于存储器(举例来说，阵列130)中的数据执行逻辑运算且将结果存储到存储器而不启用耦合到感测电路的本地I/O线。
图2说明根据本发明的若干实施例的耦合到感测电路的存储器阵列的部分的示意图。在此实例中，存储器阵列为存储器单元(MC)260-1……260-N的DRAM阵列。在若干实施例中，存储器单元为破坏性读取存储器单元(举例来说，读取存储于单元中的数据破坏所述数据使得最初存储于所述单元中的数据在被读取之后刷新)。图2中的阵列的存储器单元260-1……260-N可布置成通过字线204耦合的若干行及通过感测线(举例来说，数字线)205-1……205-M耦合的若干列。为方便参考，感测线205-1……205-M表示互补感测线的相应对(举例来说，图3中的305-1及305-2)。尽管图2中仅说明一行及两列存储器单元，但实施例并不如此受限制。例如，特定阵列可具有若干列的存储器单元及/或感测线(举例来说，4,096个、8,192个、16,384个等等)。作为实例，特定存储器单元晶体管(举例来说，图3中的302)的栅极可耦合到其对应字线(204)，源极/漏极区域可耦合到其对应感测线(举例来说，205-1)，且特定存储器单元晶体管的第二源极/漏极区域可耦合到其对应电容器(举例来说，图3中的303)。
根据本发明的若干实施例，图2中的阵列可耦合到感测电路。在此实例中，感测电路包括感测放大器206-1……206-P及次级感测放大器(SSA)268。感测电路可为图1中展示的感测电路150。感测放大器206-1到206-P耦合到相应感测线205-1到205-M。感测放大器206-1到206-P可为感测放大器(例如下文结合图3描述的感测放大器306)。感测放大器206-1到206-P分别经由晶体管218-1及218-2耦合到输入/输出线266-1(IO)及266-2(IO_)。列解码线264-1(CD-1)到264-R(CD-R)耦合到晶体管218-1及218-2的栅极且可选择性地经激活以经由IO线266-1及266-2将由相应感测放大器206-1到206-P感测的数据传送到SSA268。
在操作中，感测放大器(举例来说，206-1到206-P)可通过响应于选定行线(举例来说，204)的激活而放大互补感测线(举例来说，205-1到205-M)上的差分信号(举例来说，电压或电流)来感测存储于存储器单元(举例来说，260-1到260-N)中的数据值(举例来说，逻辑“1”或“0”)。作为实例，感测放大器206-1到206-P可将互补感测线对205-1的感测线中的一者(举例来说，D)驱动到第一值(举例来说，到供应电压(例如Vcc))，且可将互补感测线对205-1的另一感测线(D_)驱动到第二值(举例来说，到参考电压(例如接地电压))。以此方式，可基于(例如)将互补感测线对的哪一感测线驱动到Vcc来确定由存储器单元(举例来说，260-1)存储的数据值。接着，互补感测线对205-1到205-M的电压可经由列解码线264-1到264-R的激活而被选择性地传送到IO线266-1及266-2。以此方式，由感测放大器206-1到206-P感测的数据可经由IO线266-1及266-2传送到SSA268。通常，SSA268在特定时间可仅能够存储来自单一单元(举例来说，单元260-1到260-N中的一者)的数据值。因而，如果期望将存储于单元260-1中的数据传送到SSA268，就将激活列解码线264-1，且如果期望将存储于单元206-N中的数据传送到SSA268，就将激活列解码264-R。如果激活两条线264-1及264-R，SSA268就可能无法确定存储于单元中的任一者中的实际所存储数据值。
然而，在各种实例中，选择性地激活列解码线(举例来说，264-1到264-R)中的一者以上可为有用的。举例来说，根据本发明的若干实施例，可结合执行比较运算来完成选择性地激活若干列解码线。例如，在本发明的若干实施例中，可操作图2中展示的数据路径部分以确定存储于存储器阵列(举例来说，阵列130)中的数据是否匹配比较值，此可由裸片上控制电路(举例来说，控制电路140)及/或由外部控制电路(举例来说，主机110)提供作为(举例来说)“如果-则-否则”程序化流程的部分。
在若干实施例中，控制电路(举例来说，图1中的140)可经配置以将IO线(举例来说，266-1)充电(举例来说，预充电)到一电压(举例来说，预充电电压)。举例来说，可将IO线266-1预充电到对应于逻辑“1”的电压(举例来说，供应电压(例如Vcc))。控制电路可经配置以选择性地激活行线(举例来说，包含存储器单元260-1……260-N的行线)及列解码线(举例来说，CD-1……CD-R)。感测电路(举例来说，图1中的150)可经配置以感测耦合到经激活行线的若干选定存储器单元(举例来说，260-1……260-N)。感测电路可经配置以确定IO线266-1的预充电电压是否响应于列解码线CD-1到CD-R的选择性激活而改变。
在若干实施例中，控制电路(举例来说，图1中的140)可结合感测电路一起用以执行比较功能(举例来说，确定存储于存储器阵列中的数据是否匹配比较值)。作为实例，可将IO线266-1预充电到特定电压。所述特定电压可为对应于数据值的电压。例如，预充电电压可为可对应于逻辑“1”的供应电压(例如Vcc)或可对应于逻辑“0”的接地电压。
列解码线CD-1的激活开启晶体管218-1及218-2，此将对应于存储于感测放大器206-1中的数据的电压提供到IO线266-1及266-2。因而，IO线266-1的预充电电压可基于存储于感测放大器206-1中的特定数据值(其表示存储于特定存储器单元(例如单元260-1)中的数据)而改变。举例来说，如果感测放大器206-1感测存储于单元260-1中的逻辑0(举例来说，接地电压)，则当CD-1激活时IO线266-1上的预充电电压(举例来说，Vcc)将被下拉(举例来说，降低)，且可由SSA268检测预充电电压中的改变。因而，所检测的预充电电压中的改变指示所感测的存储器单元(举例来说，260-1)存储与对应于所述预充电电压的数据值(举例来说，1)不同的数据值(举例来说，0)。类似地，如果感测放大器206-1感测存储于单元260-1中的逻辑1(举例来说，Vcc)，则当CD-1激活时IO线266-1上的预充电电压(举例来说，Vcc)将不被下拉，且由SSA268将不会检测预充电电压中的改变。因而，未检测到预充电电压的改变指示所感测的存储器单元(举例来说，260-1)存储与对应于所述预充电电压的数据值(举例来说，1)相同的数据值(举例来说，1)。
SSA268确定预充电电压是否改变的上文所描述的能力可用以执行比较函数以确定特定比较值是否匹配(例如)存储于存储器阵列中的数据。作为实例，如果运算需要已知耦合到特定行线的若干单元是否存储特定比较值(举例来说，0)，则所述特定行线可连同对应于所述若干存储器单元的感测线一起激活。如果单元中的任一者存储0，则IO线(举例来说，本地IO线)的预充电电压将改变(举例来说，下拉)。可将运算的结果报告到(例如)请求控制电路(举例来说，裸片上控制器、主机等等)。可将运算的结果报告到存储器阵列中以用于进一步计算。所确定的结果可用作继续执行特定算法的部分。例如，执行可不仅包含确定所述行的存储器单元中的任一者是否存储数据值(举例来说，0)，而且包含确定哪一(些)单元存储所述数据值。因而，可选择性地激活列解码线的子集以比较由其对应单元存储的数据值与比较值，所述比较值可结合(例如)二分搜索一起使用。
可由耦合到感测电路的控制电路(举例来说，裸片上控制器)及/或由(举例来说)若干其它源(例如外部主机)请求结合比较运算所使用的比较值。类似地，比较运算的结果可被报告到各种控制电路及/或在被报告到控制电路之前用以执行作为如果-则-否则程序化流程的部分的进一步运算(举例来说，逻辑运算)。
图3说明根据本发明的若干实施例的耦合到感测电路的存储器阵列330的一部分的示意图。在此实例中，存储器阵列330是各自由存取装置302(举例来说，晶体管)及存储元件303(举例来说，电容器)组成的1T1C(一个晶体管一个电容器)存储器单元的DRAM阵列。在若干实施例中，存储器单元是破坏性读取存储器单元(举例来说，读取存储于单元中的数据破坏所述数据使得最初存储于单元中的数据在被读取之后刷新)。阵列330的单元布置成通过字线304-0(行0)、304-1(行1)、304-2(行2)、304-3(行3)……304-N(行N)耦合的行及通过感测线(举例来说，数字线)305-1(D)及305-2(D_)耦合的列。在此实例中，每一列的单元与一对互补感测线305-1(D)及305-2(D_)相关联。尽管图3中仅说明单一列的存储器单元，但实施例并不如此受限制。例如，特定阵列可具有若干列的存储器单元及/或感测线(举例来说，4,096个、8,192个、16,384个等等)。特定存储器单元晶体管302的栅极耦合到其对应字线304-0、304-1、304-2、304-3……304-N，第一源极/漏极区域耦合到其对应感测线305-1，且特定存储器单元晶体管的第二源极/漏极区域耦合到其对应晶体管303。尽管图3中未说明，但感测线305-2也可耦合到存储器单元的列。
根据本发明的若干实施例，阵列330耦合到感测电路。在此实例中，感测电路包括感测放大器306及计算组件331。感测电路可为图1中展示的感测电路150。感测放大器306耦合到对应于存储器单元的特定列的互补感测线D、D_。感测放大器306可经操作以确定存储于选定单元中的状态(举例来说，逻辑数据值)。实施例不受限于实例感测放大器306。例如，根据本文中描述的若干实施例的感测电路可包含电流模式感测放大器及/或单端型感测放大器(举例来说，耦合到一条感测线的感测放大器)。
在若干实施例中，计算组件(举例来说，331)可包含形成于与感测放大器(举例来说，306)的晶体管及/或阵列(举例来说，330)的存储器单元的间距上的若干晶体管，所述间距可符合特定特征大小(举例来说，4F2、6F2等等)。如下文进一步描述，计算组件331可结合感测放大器306一起操作以使用来自阵列330的数据作为输入来执行各种比较及报告运算，且将结果存储回到阵列330而未经由感测线地址存取传送数据(举例来说，未激发列解码信号)使得数据经由本地I/O线(举例来说，图2中的266-1)传送到阵列外部的电路及感测电路。
在图3中所说明的实例中，对应于计算组件331的电路包括耦合到感测线D及D_中的每一者的五个晶体管；然而，实施例不限于此实例。晶体管307-1及307-2具有分别耦合到感测线D及D_的第一源极/漏极区域及耦合到交叉耦合锁存器(举例来说，耦合到一对交叉耦合晶体管(例如交叉耦合NMOS晶体管308-1及308-2及交叉耦合PMOS晶体管309-1及309-2)的栅极)的第二源极/漏极区域。如本文中进一步描述，包括晶体管308-1、308-2、309-1及309-2的交叉耦合锁存器可称为次级锁存器(对应于感测放大器306的交叉耦合锁存器在本文中可称为初级锁存器)。
晶体管307-1及307-2可称为传递晶体管，其可经由相应信号311-1(Passd)及311-2(Passdb)启用以便将相应感测线D及D_上的电压或电流传递到包括晶体管308-1、308-2、309-1及309-2的交叉耦合锁存器的输入(举例来说，次级锁存器的输入)。在此实例中，晶体管307-1的第二源极/漏极区域耦合到晶体管308-1及309-1的第一源极/漏极区域以及晶体管308-2及309-2的栅极。类似地，晶体管307-2的第二源极/漏极区域耦合到晶体管308-2及309-2的第一源极/漏极区域以及晶体管308-1及309-1的栅极。
晶体管308-1及308-2的第二源极/漏极区域共同耦合到负控制信号312-1(Accumb)。晶体管309-1及309-2的第二源极/漏极区域共同耦合到正控制信号312-2(Accum)。Accum信号312-2可为供应电压(举例来说，Vcc)且Accumb信号可为参考电压(举例来说，接地)。启用信号312-1及312-2激活对应于次级锁存器的包括晶体管308-1、308-2、309-1及309-2的交叉耦合锁存器。经激活感测放大器对操作以放大共同节点317-1与共同节点317-2之间的差分电压，使得节点317-1被驱动到Accum信号电压及Accumb信号电压中的一者(举例来说，到Vcc及接地中的一者)，且节点317-2被驱动到Accum信号电压及Accumb信号电压中的另一者。如下文进一步描述，信号312-1及312-2被标记为“Accum”及“Accumb”，此是因为次级锁存器在用以执行逻辑运算时可充当累加器。在若干实施例中，累加器包括形成次级锁存器的交叉耦合晶体管308-1、308-2、309-1及309-2以及传递晶体管307-1及308-2。如本文中进一步描述，在若干实施例中，包括耦合到感测放大器的累加器的计算组件可将配置以执行逻辑运算，所述逻辑运算包括对由一对互补感测线中的至少一者上的信号(举例来说，电压或电流)表示的数据值执行累加运算。
计算组件331也包含反相晶体管314-1及314-2，其具有耦合到相应数字线D及D_的第一源极/漏极区域。晶体管314-1及314-2的第二源极/漏极区域分别耦合到晶体管316-1及316-2的第一源极/漏极区域。晶体管314-1及314-2的栅极耦合到信号313(InvD)。晶体管316-1的栅极耦合到共同节点317-1，晶体管308-2的栅极、晶体管309-2的栅极及晶体管308-1的第一源极/漏极区域也耦合到共同节点317-1。以互补方式，晶体管316-2的栅极耦合到共同节点317-2，晶体管308-1的栅极、晶体管309-1的栅极及晶体管308-2的第一源极/漏极区域也耦合到共同节点317-2。因而，启用信号InvD用以使存储于次级锁存器中的数据值反相且将所述反相值驱动到感测线305-1及305-2上。
在本发明的若干实施例中，比较运算可包含激活存储器单元的行(举例来说，行线204)以确定在所述行线中是否存在匹配(举例来说，至少一个存储器单元存储比较值)。比较运算可经扩展以包含比较32位比较值与存储于阵列中的数据。举例来说，可将若干存储器单元的比较值聚合于累加器中(如上文描述)以确定是否存在匹配32位比较值的比较值的集合。
本发明的实施例不受限于图2及3中所说明的特定感测电路配置。例如，根据本文中描述的若干实施例，不同的计算组件电路可用以执行逻辑运算。
图4说明根据本发明的若干实施例的用于执行比较运算的方法的实例。在框470处，所述方法包含将存储器阵列(举例来说，图3中的330)的输入/输出(IO)线(举例来说，图2中的266-1)预充电到预充电电压。(例如)可将IO线(举例来说，本地IO线)预充电到对应于特定数据值的电压，例如供应电压(举例来说，对应于逻辑1的Vcc)或参考电压(举例来说，对应于逻辑0的接地电压)。若干实施例可包含将存储器阵列的LIO线(举例来说，图2中的266-2)预充电到预充电电压。LIO线所预充电到的电压可为LIO线所预充电到的电压的反相。
在框472处，所述方法包含确定存储于存储器阵列中的数据是否匹配比较值。所述比较值可为由外部主机(举例来说，外部处理器)及/或裸片上控制器提供的值。所述比较值可包含控制电路尝试确定是否存储于存储器阵列中的至少一个存储器单元中的若干不同数据值。所述比较值可存储于若干存储器单元中。举例来说，数据可存储于一个、两个、三个等等存储器单元中。匹配可指代由控制电路提供的比较值存储于阵列中的至少一个存储器单元中的确定。比较值未存储于至少一个存储器单元中的确定可指示不存在匹配。
在框474处，可通过激活存储器阵列的若干行线来确定存储于存储器阵列中的数据是否匹配比较值的确定。所述若干行线可基于所述行线的特性而选择性地激活。所述若干行线可包含由控制器(举例来说，外部主机、裸片上控制器)预先确定的特定行线。
在框476处，可通过感测耦合到所述若干行线的若干存储器单元来确定存储于存储器阵列中的数据是否匹配比较值的确定。可由感测放大器感测存储器阵列的行线的存储器单元的电压，且可激活列解码线以将所述感测放大器(及对应存储器单元)的电压提供到LIO线。
在框478处，可通过感测LIO线的预充电电压是否响应于对应于若干存储器单元的选定列解码线的激活而改变来确定存储于存储器阵列中的数据是否匹配比较值的确定。举例来说，可将LIO线预充电到对应于逻辑1的供应电压(举例来说，Vcc)。存储器阵列中的存储器单元可存储对应于控制器设法定位(举例来说，匹配)的比较值的数据值(举例来说，逻辑0)。当存储器单元被激活且所述单元的电压(举例来说，经由对应感测放大器)被提供到LIO线时，如果由所述单元存储的数据值匹配比较值(举例来说，如果由所述单元存储的数据值为逻辑0)，则所述LIO线上的电压(举例来说，预充电电压)将下降。次级感测放大器可检测电压的下降且确定已发生匹配。可将匹配的确定报告到提供比较值的电路(举例来说，裸片上控制器、外部主机等等)及/或报告到一些其它控制电路以供进一步使用。如果确定匹配，则可执行进一步操作以确定阵列内发生所述匹配的特定位置(举例来说，单元)。外围控制逻辑可读取数据路径以确定存储器阵列的比较状态。定位匹配可包含搜索方法(举例来说，二分搜索)以确定匹配存储器阵列中的哪一存储器单元。匹配可发生在若干存储器单元(举例来说，零个存储器单元、一个存储器单元或多个存储器单元)处。
尽管本文中已说明并描述特定实施例，但所属领域的一般技术人员将了解，经计算以实现相同结果的布置可替代所展示的特定实施例。本发明希望涵盖本发明的一或多个实施例的调适或变动。应理解，已以说明方式而非限制方式进行上文描述。所属领域的技术人员在审阅上文描述之后将明白上文实施例与本文中未特定描述的其它实施例的组合。本发明的一或多个实施例的范围包含其中使用上文结构及方法的其它应用。因此，应参考附随权利要求书及此类权利要求所授权的等效物的全部范围来确定本发明的一或多个实施例的范围。
在前述具体实施方式中，出于简化本发明的目的，将一些特征集合于单一实施例中。本发明的此方法不应被解释为反映本发明的所揭示实施例必须使用比明确陈述于每一权利要求中更多的特征的意图。事实上，如所附权利要求书反映，本发明标的物在于少于单一所揭示实施例的全部特征。因此，特此将所附权利要求书并入到具体实施方式中，其中每一权利要求独立地作为单独实施例。

Claims (31)

1.一种执行比较功能的方法，其包括：
将存储器阵列的输入/输出IO线充电到一电压；
通过以下步骤确定存储于所述存储器阵列中的数据是否匹配比较值：
激活所述存储器阵列的若干存取线；
感测耦合到所述若干存取线的若干存储器单元；及
感测所述IO线的所述电压是否响应于对应于所述若干存储器单元的选定解码线的激活而改变。
2.根据权利要求1所述的方法，其中对IO线充电包含将所述存储器阵列的IO线预充电到预充电电压。
3.根据权利要求1所述的方法，其中将所述IO线充电到所述电压包含将所述IO线充电到供应电压。
4.根据权利要求3所述的方法，其中所述供应电压对应于数据值1。
5.根据权利要求1所述的方法，其中将所述IO线充电到一电压包含将所述IO线充电到接地电压。
6.根据权利要求5所述的方法，其中所述接地电压对应于数据值0。
7.根据权利要求1到6中任一权利要求所述的方法，其中激活选定解码线包括激活所述阵列的所述解码线的子集。
8.根据权利要求7所述的方法，其包含基于所述解码线子集的一组准则确定所述子集。
9.一种设备，其包括：
存储器单元阵列；
控制电路，其耦合到所述阵列且经配置以致使：
将所述阵列的本地输入/输出LIO线预充电到预充电电压；及
选择性地激活所述阵列的存取线及解码线；及
感测电路，其耦合到所述阵列且经配置以：
感测耦合到经激活存取线的若干选定存储器单元；及
确定所述LIO线的所述预充电电压是否响应于对应于所述若干选定存储器单元的解码线的激活而改变。
10.根据权利要求9所述的设备，其中所述控制电路包括裸片上控制器。
11.根据权利要求9所述的设备，其中所述控制电路包括外部主机。
12.根据权利要求9所述的设备，其中所述预充电电压对应于特定数据值，且所述LIO线的所述预充电电压中的经确定改变指示对应于经激活解码线的选定存储器单元存储除所述特定数据值外的数据值。
13.根据权利要求9所述的设备，其中所述感测电路包括经配置以检测所述LIO线的所述预充电电压是否改变的次级感测放大器。
14.根据权利要求9所述的设备，其中所述LIO线的所述预充电电压中的经确定改变指示存储器单元中的数据匹配比较值。
15.根据权利要求9所述的设备，其中所述控制电路经配置以将所述LIO线的所述预充电电压中的经确定改变报告到主机。
16.根据权利要求9到15中任一权利要求所述的设备，其中所述感测电路经配置以提供所述LIO线的所述预充电电压中的经确定改变被检测的指示。
17.一种设备，其包括：
存储器单元阵列；
控制电路，其耦合到所述存储器阵列且经配置以致使所述存储器阵列的输入/输出IO线充电到一电压；及
感测电路，其耦合到所述存储器阵列且包括：
若干初级感测放大器，其耦合到互补感测线的相应对；
若干累加器，其耦合到所述若干初级感测放大器；
次级感测放大器，其耦合到所述IO线且经配置以感测所述IO线的所述电压是否响应于所述阵列的选定解码线的激活而改变以确定存储于所述阵列中的数据是否匹配比较值。
18.根据权利要求17所述的设备，其中所述累加器中的每一者包括：
第一传递晶体管，其具有耦合到一对互补感测线的第一感测线的第一源极/漏极区域；
第二传递晶体管，其具有耦合到所述对互补感测线的第二感测线的第一源极/漏极区域；及
第一对交叉耦合晶体管及第二对交叉耦合晶体管。
19.根据权利要求18所述的设备，其中所述设备经配置以执行逻辑运算，所述逻辑运算包括对由所述对互补感测线中的至少一者上的信号表示的数据值执行累加运算。
20.根据权利要求19所述的设备，其中所述信号经由所述若干初级感测放大器中的至少一者被提供到所述IO线。
21.根据权利要求20所述的设备，其中将IO线充电到一电压包含将所述存储器阵列的IO线预充电到预充电电压。
22.根据权利要求21所述的设备，其中所述信号被提供到所述次级感测放大器，且其中所述次级感测放大器检测在所述信号对应于不同于所述预充电电压的电压时所述预充电电压的改变。
23.根据权利要求19所述的设备，其中所述累加器经配置以接收反相信号，其中激活所述反相信号使存储于所述累加器中的数据值反相且将对应于所述反相数据值的信号驱动到所述对互补感测线中的一者上。
24.根据权利要求23所述的设备，其中所述对互补感测线经配置以将对应于所述反相数据值的所述信号提供到所述若干初级感测放大器中的至少一者。
25.根据权利要求24所述的设备，其中所述若干初级感测放大器中的所述至少一者经配置以将所述反相数据值提供到IO线，其中所述IO线经配置以将所述反相数据值提供到所述次级感测放大器。
26.根据权利要求25所述的设备，其中所述IO线被充电到接地电压，且其中所述次级感测放大器检测在对应于所述反相数据值的所述信号为大于接地电压的电压时所述电压的改变。
27.一种设备，其包括：
存储器单元阵列；
控制电路，其耦合到所述阵列且经配置以进行以下动作作为比较运算的一部分：
致使将所述阵列的本地输入/输出LIO线预充电到预充电电压；
致使选择性地激活所述阵列的存取线；及
致使选择性地激活所述阵列的解码线；及
感测电路，其耦合到所述阵列且经配置以：
感测耦合到多个经选择性激活的存取线的存储器单元；及
感测所述LIO线的所述预充电电压是否响应于对应于所述存储器单元的多个所述解码线的选择性激活而改变；
其中所述预充电电压响应于所述多列解码线的所述选择性激活而改变的确定指示耦合到所述多个经选择性激活的存取线的所述存储器单元中的至少一者存储匹配比较值的数据值。
28.根据权利要求27所述的设备，其包括控制电路，所述控制电路经配置以致使所述存储器单元中的所述至少一者存储匹配所述比较值的数据值的所述确定被报告回到所述阵列中。
29.根据权利要求27到28中任一权利要求所述的设备，其包括控制电路，所述控制电路经配置以致使搜索以识别所述存储器单元中的所述至少一者的哪一存储器单元匹配所述比较值。
30.根据权利要求29所述的设备，其包括控制电路，所述控制电路经配置以致使所述存储器单元的所述识别被报告到主机。
31.根据权利要求29所述的设备，其包括控制电路，所述控制电路经配置以致使所述存储器单元的所述识别被报告回到所述阵列中。
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