TW201517047A - 用於使用感測電路執行比較運算之裝置與方法 - Google Patents

用於使用感測電路執行比較運算之裝置與方法 Download PDF

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TW201517047A
TW201517047A TW103125169A TW103125169A TW201517047A TW 201517047 A TW201517047 A TW 201517047A TW 103125169 A TW103125169 A TW 103125169A TW 103125169 A TW103125169 A TW 103125169A TW 201517047 A TW201517047 A TW 201517047A
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Troy A Manning
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Micron Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/043—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

本發明包含關於使用感測電路執行比較及/或報告運算之裝置及方法。一種例示性方法可包含將一記憶體陣列之一輸入/輸出(IO)線充電至一電壓。該方法可包含判定儲存於該記憶體陣列中之資料是否匹配一比較值。所儲存之資料是否匹配一比較值之該判定可包含啟動該記憶體陣列之若干存取線。該判定可包含感測耦合至該若干存取線之若干記憶體胞。該判定可包含感測該IO線之該電壓是否回應於對應於該若干記憶體胞之選定解碼線之啟動而改變。

Description

用於使用感測電路執行比較運算之裝置與方法
本發明大體上係關於半導體記憶體及方法，且更特定言之係關於使用感測電路執行比較運算之裝置及方法。
記憶體器件通常提供為電腦或其他電子系統中之內部半導體積體電路。存在諸多不同類型之記憶體，包含揮發性記憶體及非揮發性記憶體。揮發性記憶體可需要電力以維持其資料(例如，主機資料、錯誤資料等)且包含隨機存取記憶體(RAM)、動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、同步動態隨機存取記憶體(SDRAM)及閘流體隨機存取記憶體(TRAM)等。非揮發性記憶體可在未供電時藉由保持儲存資料而提供永久性資料，且可包含NAND快閃記憶體、NOR快閃記憶體及電阻可變記憶體(諸如相變隨機存取記憶體(PCRAM)、電阻性隨機存取記憶體(RRAM)及磁阻性隨機存取記憶體(MRAM)，諸如自旋力矩轉移隨機存取記憶體(STT RAM))等。
電子系統通常包含若干處理資源(例如，一或多個處理器)，其等可擷取及執行指令且將所執行指令之結果儲存至一適合位置。一處理器可包括若干功能單元，諸如算術邏輯單元(ALU)電路、浮點單元(FPU)電路及/或一組合邏輯區塊，例如，該等功能單元可用以藉由對資料(例如，一或多個運算元)執行諸如AND、OR、NOT、NAND、 NOR及XOR邏輯運算而執行指令。例如，功能單元電路(FUC)可用以對運算元執行諸如加法、減法、乘法及/或除法之算術運算。
在將指令提供至FUC以供執行中可涉及一電子系統中之若干組件。指令可由(例如)諸如一控制器及/或主機處理器之一處理資源產生。資料(例如，將對其執行指令之運算元)可儲存於可藉由FUC存取之一記憶體陣列中。可自該憶體陣列擷取指令及/或資料且可在FUC開始對資料執行指令之前序列化及/或緩衝指令及/或資料。此外，因為可透過FUC以一或多個時脈循環執行不同類型之運算，所以亦可序列化及/或緩衝指令及/或資料之中間結果。
執行指令(例如，作為程式執行之部分)可涉及執行諸如比較運算之運算，且可將結果提供(例如，報告)至處理資源作為(例如)一演算法之執行流程之部分。此比較及報告功能性可啟用(例如)「若-則-否則」程式化流程，此通常係程式執行之部分。
100‧‧‧計算系統
110‧‧‧主機
120‧‧‧記憶體器件
130‧‧‧記憶體陣列
140‧‧‧控制電路
142‧‧‧位址電路
144‧‧‧I/O電路
146‧‧‧列解碼器
148‧‧‧寫入電路
150‧‧‧感測電路
152‧‧‧行解碼器
154‧‧‧控制匯流排
156‧‧‧I/O匯流排
204‧‧‧字線/列線
205-1至205-M‧‧‧感測線
206-1至206-P‧‧‧感測放大器
218-1‧‧‧電晶體
218-2‧‧‧電晶體
260-1至260-N‧‧‧記憶體胞(MC)
264-1至264-R‧‧‧行解碼線(CD-1)至(CD-R)
266-1‧‧‧輸入/輸出線(IO)
266-2‧‧‧輸入/輸出線(IO_)
268‧‧‧次要感測放大器(SSA)
302‧‧‧電晶體/存取器件
303‧‧‧電容器/儲存元件
304-0至304-N‧‧‧字線
305-1‧‧‧感測線(D)
305-2‧‧‧感測線(D_)
306‧‧‧感測放大器
307-1‧‧‧傳遞電晶體
307-2‧‧‧傳遞電晶體
308-1‧‧‧交叉耦合NMOS電晶體
308-2‧‧‧交叉耦合NMOS電晶體
309-1‧‧‧交叉耦合PMOS電晶體
309-2‧‧‧交叉耦合PMOS電晶體
311-1‧‧‧信號(Passd)
311-2‧‧‧信號(Passdb)
312-1‧‧‧負控制信號(Accumb)
312-2‧‧‧正控制信號(Accum)
313‧‧‧信號(InvD)
314-1‧‧‧反相電晶體
314-2‧‧‧反相電晶體
316-1‧‧‧電晶體
316-2‧‧‧電晶體
317-1‧‧‧共同節點
317-2‧‧‧共同節點
330‧‧‧記憶體陣列
331‧‧‧計算組件
470‧‧‧方塊
472‧‧‧方塊
474‧‧‧方塊
476‧‧‧方塊
478‧‧‧方塊
圖1係根據本發明之若干實施例之呈包含一記憶體器件之一計算系統之形式之一裝置之一方塊圖。
圖2繪示根據本發明之若干實施例之耦合至感測電路之一記憶體陣列之一部分之一示意圖。
圖3繪示根據本發明之若干實施例之耦合至感測電路之一記憶體陣列之一部分之一示意圖。
圖4繪示根據本發明之若干實施例之用於執行一比較運算之一方法之一實例。
本發明包含關於使用感測電路執行比較運算之裝置及方法。一例示性方法包括將一記憶體陣列之一輸入/輸出(IO)線(例如，一本地IO線(LIO線))充電(例如，預充電)至一電壓(例如，一預充電電壓)。 該方法可包含藉由啟動該記憶體陣列之若干存取線及感測耦合至該若干存取線之若干記憶體胞而判定儲存於該記憶體陣列中之資料是否匹配一比較值。該方法可包含感測該LIO線之該電壓(例如，預充電電壓)是否回應於對應於該若干記憶體胞之選定解碼線(例如，行解碼線)之啟動而改變。在本發明中，一「線」意指至少兩個節點之間之一可操作耦合。
本發明之若干實施例可提供諸如與判定一比較值(例如，一特定資料值及/或資料值集合)與儲存於一記憶體陣列中之一資料值之間是否存在一匹配相關聯之經改良比較及報告功能性之益處。例如，若干實施例可提供識別特定資料是否儲存於若干記憶體胞中而(例如)不經由一匯流排(例如，資料匯流排、位址匯流排、控制匯流排)將資料傳送出記憶體陣列及感測電路。可將儲存於陣列中之資料是否匹配比較值之判定報告至(例如)控制電路(例如，至一晶粒上控制器及/或至一外部主機)。可將儲存於陣列中之資料是否匹配比較值之判定報告至記憶體陣列中。此比較及報告功能性可與執行若干邏輯運算(例如，AND、NOT、NOR、NAND、XOR等)相關聯。然而，實施例不受限於此等實例。
再者，與(若干)各種處理資源相關聯之電路(諸如FUC)可不符合與一記憶體陣列相關聯之間距規則(pitch rule)。例如，一記憶體陣列之胞可具有一4F2或6F2胞大小，其中「F」係對應於胞之一特徵大小。與先前系統之FUC相關聯之器件(例如，邏輯閘)可能無法形成於與記憶體胞之間距上，此可影響(例如)晶片大小及/或記憶體密度。
在本發明之以下詳細描述中，參考形成本發明之一部分之附圖，且在附圖中以圖解方式展示可如何實踐本發明之一或多項實施例。足夠詳細地描述此等實施例以使一般技術者能夠實踐本發明之該等實施例，且應瞭解，在不脫離本發明之範疇之情況下，可利用其他 實施例且可進行程序、電氣及/或結構改變。如本文中所使用，標示符「N」、「P」、「R」等(尤其關於圖式中之參考數字)可指示：可包含如此指定之若干特定特徵。如本文中所使用，「若干」特定事物可係指此等事物之一或多者(例如，若干記憶體陣列可係指一或多個記憶體陣列)。
本文中之圖遵循一編號慣例，其中首位或前幾位數字對應於圖式圖號且剩餘數字識別圖式中之一元件或組件。可藉由使用類似數字識別不同圖之間之類似元件或組件。例如，130可參考圖1中之元件「30」，且一類似元件在圖2中可稱為230。應瞭解，可添加、交換及/或消除在本文中之各種實施例中所展示之元件以便提供本發明之若干額外實施例。此外，如應瞭解，圖中所提供的元件之比例及相對尺度意欲繪示本發明之某些實施例，且不應被視為限制意義。
圖1係根據本發明之若干實施例之呈包含一記憶體器件120之一計算系統100之形式之一裝置之一方塊圖。如本文中所使用，一記憶體器件120、一記憶體陣列130及/或一感測電路150亦可被單獨視為一「裝置」。
系統100包含一主機110，該主機110耦合至包含一記憶體陣列130之記憶體器件120。主機110可係一主機系統，諸如一個人膝上型電腦、一桌上型電腦、一數位相機、一行動電話或一記憶體卡讀取器，以及各種其他類型之主機。主機110可包含一系統主機板及/或背板且可包含若干處理資源(例如，一或多個處理器、微處理器或某一其他類型之控制電路)。系統100可包含單獨積體電路，或主機110及記憶體器件120兩者可在相同積體電路上。系統100可係(例如)一伺服器系統及/或一高效能計算(HPC)系統及/或該高效能計算(HPC)系統之一部分。儘管圖1中展示之實例繪示具有一范紐曼(Von Neumann)架構之一系統，然本發明之實施例可以非范紐曼架構(例如，一杜林機(Turing machine)，其可不包含通常與一范紐曼架構相關聯之一或多個組件(例如，CPU、ALU等))實施。
為明確起見，系統100已經簡化以集中在與本發明特定相關之特徵。記憶體陣列130可係(例如)DRAM陣列、SRAM陣列、STT RAM陣列、PCRAM陣列、TRAM陣列、RRAM陣列、NAND快閃陣列及/或NOR快閃陣列。陣列130可包括配置成藉由存取線(本文中可稱為列線、字線或選擇線)耦合之列及藉由感測線(本文中可稱為數位線或資料線)耦合之行之記憶體胞。儘管圖1中展示一單一陣列130，然實施例並不如此受限制。例如，記憶體器件120可包含若干陣列130(例如，若干DRAM胞庫)。結合圖2及圖3描述一例示性DRAM陣列。
記憶體器件120包含用以鎖存經由一I/O匯流排156(例如，一資料匯流排)透過I/O電路144提供之位址信號之位址電路142。藉由一列解碼器146及一行解碼器152接收及解碼位址信號以存取記憶體陣列130。可藉由使用感測電路150感測感測線上之電壓及/或電流改變而自記憶體陣列130讀取資料。感測電路150可自記憶體陣列130讀取及鎖存一資料頁(例如，列)。I/O電路144可用於經由I/O匯流排156與主機110之雙向資料通信。寫入電路148用以將資料寫入至記憶體陣列130。
控制電路140解碼由控制匯流排154自主機110提供之信號。此等信號可包含用以控制對記憶體陣列130執行之控制操作(包含資料讀取、資料寫入及資料抹除操作)之晶片啟用信號、寫入啟用信號及位址鎖存信號。在各種實施例中，控制電路140負責執行來自主機110之指令。控制電路140可係一狀態機、一定序器或某一其他類型之控制器(例如，一晶粒上控制器)。
下文結合圖2及圖3進一步描述感測電路150之一實例。例如，在若干實施例中，感測電路150可包括若干感測放大器(例如，圖2中展 示之感測放大器206-1、...、206-P或圖3中展示之感測放大器306)及若干計算組件(例如，圖3中展示之計算組件331)，該等計算組件可包括一累加器且可用以(例如，對與互補感測線相關聯之資料)執行比較及報告運算。在若干實施例中，感測電路(例如，150)可用以使用儲存於陣列130中之資料作為輸入來執行比較及報告運算，且將邏輯運算之結果儲存回至陣列130而未經由一感測線位址存取傳送(例如，未觸發(firing)一行解碼信號)。因而，各種計算功能可在陣列130內使用感測電路150執行而非藉由感測電路外部之處理資源(例如，藉由與主機110相關聯之一處理器及/或定位於器件120上(例如，在控制電路140上或別處)之其他處理電路，諸如ALU電路)執行。在各種先前方法中，(例如)與一運算元相關聯之資料將經由感測電路自記憶體讀取且經由本地I/O線提供至外部ALU電路。外部ALU電路將使用運算元執行計算功能且結果將經由本地I/O線傳送回至陣列。相比之下，在本發明之若干實施例中，感測電路(例如，150)可經組態以對儲存於記憶體(例如，陣列130)中之資料執行邏輯運算且將結果儲存至記憶體而不啟用耦合至感測電路之一本地I/O線。
圖2繪示根據本發明之若干實施例之耦合至感測電路之一記憶體陣列之一部分之一示意圖。在此實例中，記憶體陣列係記憶體胞(MC)260-1、...、260-N之一DRAM陣列。在若干實施例中，記憶體胞係破壞性讀取記憶體胞(例如，讀取儲存於胞中之資料破壞該資料使得最初儲存於胞中之資料在讀取之後經再新)。圖2中之陣列之記憶體胞260-1、...、260-N可配置成藉由字線204耦合之若干列及藉由感測線(例如，數位線)205-1、...、205-M耦合之若干行。為方便參考，感測線205-1、...、205-M表示互補感測線之各自對(例如，圖3中之305-1及305-2)。儘管圖2中繪示記憶體胞之一個列及兩個行，然實施例並不如此受限制。例如，一特定陣列可具有若干行之記憶體胞及/ 或感測線(例如，4,096個、8,192個、16,384個等)。作為一實例，一特定記憶體胞電晶體(例如，圖3中之302)之一閘極可耦合至其對應字線(204)，一源極/汲極區域可耦合至其對應感測線(例如，205-1)，且一特定記憶體胞電晶體之一第二源極/汲極區域可耦合至其對應電容器(例如，圖3中之303)。
根據本發明之若干實施例，圖2中之陣列可耦合至感測電路。在此實例中，感測電路包括感測放大器206-1、...、206-P及次要感測放大器(SSA)268。感測電路可係圖1中展示之感測電路150。感測放大器206-1至206-P耦合至各自感測線205-1至205-M。感測放大器206-1至206-P可係諸如下文結合圖3描述之感測放大器306之感測放大器。感測放大器206-1至206-P分別經由電晶體218-1及218-2耦合至輸入/輸出線266-1(IO)及266-2(IO_)。行解碼線264-1(CD-1)至264-R(CD-R)耦合至電晶體218-1及218-2之閘極且可選擇性地經啟動以經由IO線266-1及266-2將藉由各自感測放大器206-1至206-P感測之資料傳送至SSA 268。
在操作中，感測放大器(例如，206-1至206-P)可藉由回應於一選定列線(例如，204)之啟動而放大互補感測線(例如，205-1至205-M)上之一差動信號(例如，電壓或電流)來感測儲存於一記憶體胞(例如，260-1至260-N)中之一資料值(例如，一邏輯「1」或「0」)。作為一實例，感測放大器206-1至206-P可將該對互補感測線205-1之感測線之一者(例如，D)驅動至一第一值(例如，至諸如Vcc之一供應電壓)，且可將該對互補感測線205-1之另一感測線(D_)驅動至一第二值(例如，至諸如一接地電壓之一參考值)。以此方式，可基於(例如)將互補感測線對之哪一感測線驅動至Vcc而判定藉由記憶體胞(例如，260-1)儲存之資料值。接著，互補感測線對205-1至205-M之電壓可經由行解碼線264-1至264-R之啟動而選擇性地傳送至IO線266-1及266-2。以此方 式，藉由感測放大器206-1至206-P感測之資料可經由IO線266-1及266-2傳送至SSA 268。通常，SSA 268在一特定時間可僅能夠儲存來自一單一胞(例如，胞260-1至260-N之一者)之一資料值。因而，若期望將儲存於胞260-1中之資料傳送至SSA 268，則將啟動行解碼線264-1，且若期望將儲存於胞206-N中之資料傳送至SSA 268，則將啟動行解碼線264-R。若啟動兩個線264-1及264-R，則SSA 268可能無法判定儲存於胞之任一者中之實際儲存資料值。
然而，在各種例項中，選擇性地啟動一個以上行解碼線(例如，264-1至264-R)可係有用的。例如，根據本發明之若干實施例，可結合執行一比較運算來完成選擇性地啟動若干行解碼線。例如，在本發明之若干實施例中，可操作圖2中展示之資料路徑部分以判定儲存於一記憶體陣列(例如，陣列130)中之資料是否匹配一比較值，此可藉由一晶粒上控制電路(例如，控制電路140)及/或藉由外部控制電路(例如，主機110)提供作為(例如)一「若-則-否則」程式化流程之部分。
在若干實施例中，控制電路(例如，圖1中之140)可經組態以將一IO線(例如，266-1)充電(例如，預充電)至一電壓(例如，一預充電電壓)。例如，可將IO線266-1預充電至對應於一邏輯「1」之一電壓(舉例而言，諸如Vcc之一供應電壓)。控制電路可經組態以選擇性地啟動列線(例如，包含記憶體胞260-1、...、260-N之一列線)及行解碼線(例如，CD-1、...、CD-R)。感測電路(例如，圖1中之150)可經組態以感測耦合至一經啟動列線之若干選定記憶體胞(例如，260-1、...、260-N)。感測電路可經組態以判定IO線266-1之預充電電壓是否回應於行解碼線CD-1至CD-R之選擇性啟動而改變。
在若干實施例中，控制電路(例如，圖1中之140)可結合感測電路一起用以執行一比較功能(例如，判定儲存於記憶體陣列中之資料是否匹配一比較值)。作為一實例，可將IO線266-1預充電至一特定電 壓。該特定電壓可係對應於一資料值之一電壓。例如，該預充電電壓可係諸如Vcc之一供應電壓(其可對應於一邏輯「1」)或一接地電壓(其可對應於一邏輯「0」)。
行解碼線CD-1之啟動開啟電晶體218-1及218-2，此將對應於儲存於感測放大器206-1中之資料之電壓提供至IO線266-1及266-2。因而，IO線266-1之預充電電壓可基於儲存於感測放大器206-1中之特定資料值(其表示儲存於諸如胞260-1之一特定記憶體胞中之資料)而改變。例如，若感測放大器206-1感測儲存於胞260-1中之一邏輯0(例如，一接地電壓)，則當CD-1啟動時IO線266-1上之預充電電壓(例如，Vcc)將被下拉(例如，降低)，且可藉由SSA 268偵測到預充電電壓之改變。 因而，所偵測之預充電電壓之改變指示所感測之記憶體胞(例如，260-1)儲存不同於對應於該預充電電壓之資料值(例如，1)之一資料值(例如，0)。類似地，若感測放大器206-1感測儲存於胞260-1中之一邏輯1(例如，Vcc)，則當CD-1啟動時IO線266-1上之預充電電壓(例如，Vcc)將不被下拉，且SSA 268將不會偵測到預充電電壓之改變。因而，未偵測到預充電電壓之改變指示所感測之記憶體胞(例如，260-1)儲存與對應於該預充電電壓之資料值(例如，1)相同之一資料值(例如，1)。
SSA 268判定預充電電壓是否改變之上述能力可用以執行比較功能以判定一特定比較值是否匹配(例如)儲存於一記憶體陣列中之資料。作為一實例，若一運算需要已知耦合至一特定列線之若干胞是否儲存一特定比較值(例如，0)，則該特定列線可連同對應於該若干記憶體胞之感測線一起啟動。若胞之任一者儲存一O，則IO線(例如，本地IO線)之預充電電壓將改變(例如，下拉)。可將運算之結果報告至(例如)請求控制電路(例如，晶粒上控制器、主機等)。可將運算之結果報告至記憶體陣列中以進行進一步計算。所判定之結果可用作繼續 執行一特定演算法之部分。例如，執行可不僅包含判定該列之記憶體胞之任一者是否儲存一資料值(例如，0)，而且包含判定哪一(些)胞儲存該資料值。因而，可選擇性地啟動行解碼線之子集以比較藉由其等對應胞儲存之資料值與比較值，該比較值可結合(例如)二元搜尋法一起使用。
可藉由耦合至感測電路之控制電路(例如，晶粒上控制器)及/或藉由(例如)諸如一外部主機之若干其他源而請求結合比較運算使用之比較值。類似地，比較運算之結果可報告至各種控制電路及/或在報告至控制電路之前用以執行作為若-則-否則程式化流程之部分之進一步運算(例如，邏輯運算)。
圖3繪示根據本發明之若干實施例之耦合至感測電路之一記憶體陣列330之一部分之一示意圖。在此實例中，記憶體陣列330係1T1C(一電晶體一電容器)記憶體胞之一DRAM陣列，各1T1C記憶體胞由一存取器件302(例如，電晶體)及一儲存元件303(例如，一電容器)組成。在若干實施例中，記憶體胞係破壞性讀取記憶體胞(例如，讀取儲存於胞中之資料破壞該資料使得最初儲存於胞中之資料在讀取之後經再新)。陣列330之胞配置成藉由字線304-0(列0)、304-1(列1)、304-2(列2)、304-3(列3)、...、304-N(列N)耦合之列及藉由感測線(例如，數位線)305-1(D)及305-2(D_)耦合之行。在此實例中，各行之胞與一對互補感測線305-1(D)及305-2(D_)相關聯。儘管圖3中僅繪示一單一行之記憶體胞，然實施例並不如此受限制。例如，一特定陣列可具有若干行之記憶體胞及/或感測線(例如，4,096個、8,192個、16,384個等)。一特定記憶體胞電晶體302之一閘極耦合至其對應字線304-0、304-1、304-2、304-3、...、304-N，一第一源極/汲極區域耦合至其對應感測線305-1，且一特定記憶體胞電晶體之一第二源極/汲極區域耦合至其對應電容器303。儘管圖3中未繪示，然感測線305-2 亦可耦合至一行記憶體胞。
根據本發明之若干實施例，陣列330係耦合至感測電路。在此實例中，感測電路包括一感測放大器306及一計算組件331。感測電路可係圖1中展示之感測電路150。感測放大器306耦合至對應於一特定行之記憶體胞之互補感測線D及D_並耦合至一輸入/輸出線366(IO/IO_)。感測放大器306可經操作以判定儲存於一選定胞中之一狀態(例如，邏輯資料值)。實施例不受限於例示性感測放大器306。例如，根據本文中描述之若干實施例之感測電路可包含電流模式感測放大器及/或單端感測放大器(例如，耦合至一感測線之感測放大器)。
在若干實施例中，一計算組件(例如，331)可包括形成於與感測放大器(例如，306)之電晶體及/或陣列之記憶體胞之間距上之若干電晶體，該間距可符合一特定特徵大小(例如，4F2、6F2等)。如下文進一步描述，計算組件331可結合感測放大器306一起操作以使用來自陣列330之資料作為輸入來執行各種比較及報告運算，且將結果儲存回至陣列330而未經由一感測線位址存取傳送資料(例如，未觸發一行解碼信號)，使得資料經由本地I/O線(例如，圖2中之266-1)傳送至陣列外部之電路及感測電路。
在圖3中所繪示之實例中，對應於計算組件331之電路包括耦合至感測線D及D_之各者之五個電晶體；然而，實施例不限於此實例。電晶體307-1及307-2具有分別耦合至感測線D及D_之一第一源極/汲極區域，及耦合至一交叉耦合鎖存器(例如，耦合至一對交叉耦合電晶體(諸如交叉耦合NMOS電晶體308-1及308-2及交叉耦合PMOS電晶體309-1及309-2之閘極)之一第二源極/汲極區域。如本文中進一步描述，包括電晶體308-1、308-2、309-1及309-2之交叉耦合鎖存器可稱為一次要鎖存器(對應於感測放大器306之交叉耦合鎖存器在本文中可稱作一主要鎖存器)。
電晶體307-1及307-2可稱為傳遞電晶體，其等可經由各自信號311-1(Passd)及311-2(Passdb)啟用以便將各自感測線D及D_上之電壓或電流傳遞至包括電晶體308-1、308-2、309-1及309-2之交叉耦合鎖存器之輸入端(例如，次要鎖存器之輸入端)。在此實例中，電晶體307-1之第二源極/汲極區域耦合至電晶體308-1及309-1之一第一源極/汲極區域以及電晶體308-2及309-2之閘極。類似地，電晶體307-2之第二源極/汲極區域耦合至電晶體308-2及309-2之一第一源極/汲極區域以及電晶體308-1及309-1之閘極。
電晶體308-1及308-2之一第二源極/汲極區域共同耦合至一負控制信號312-1(Accumb)。電晶體309-1及309-2之一第二源極/汲極區域共同耦合至一正控制信號312-2(Accum)。Accum信號312-2可係一供應電壓(例如，Vcc)且Accumb信號可係一參考電壓(例如，接地)。啟用信號312-1及312-2啟動對應於次要鎖存器之包括電晶體308-1、308-2、309-1及309-2之交叉耦合鎖存器。經啟動感測放大器對操作以放大共同節點317-1與共同節點317-2之間之一差動電壓，使得將節點317-1驅動至Accum信號電壓及Accumb信號電壓之一者(例如，至Vcc及接地之一者)，且將節點317-2驅動至Accum信號電壓及Accumb信號電壓之另一者。如下文進一步描述，信號312-1及312-2標記為「Accum」及「Accumb」，此係因為次要鎖存器在用以執行一邏輯運算時可充當一累加器。在若干實施例中，一累加器包括形成次要鎖存器之交叉耦合電晶體308-1、308-2、309-1及309-2以及傳遞電晶體307-1及307-2。如本文中進一步描述，在若干實施例中，包括耦合至一感測放大器之一累加器之一計算組件可經組態以執行一邏輯運算，該邏輯運算包括對藉由一對互補感測線之至少一者上之一信號(例如，電壓或電流)表示之一資料值執行一累加運算。
計算組件331亦包含反相電晶體314-1及314-2，其等具有耦合至 各自數位線D及D_之一第一源極/汲極區域。電晶體314-1及314-2之一第二源極/汲極區域分別耦合至電晶體316-1及316-2之一第一源極/汲極區域。電晶體314-1及314-2之閘極耦合至一信號313(InvD)。電晶體316-1之閘極耦合至共同節點317-1，電晶體308-2之閘極、電晶體309-2之閘極及電晶體308-1之第一源極/汲極區域亦耦合至該共同節點317-1。以一互補方式，電晶體316-2之閘極耦合至共同節點317-2，電晶體308-1之閘極、電晶體309-1之閘極及電晶體308-2之第一源極/汲極區域亦耦合至該共同節點317-2。因而，啟用信號InvD用以使儲存於次要鎖存器中之資料值反相且將該反相值驅動至感測線305-1及305-2上。
在本發明之若干實施例中，一比較運算可包含啟動一列之記憶體胞(例如，列線204)以判定該列線中是否存在一匹配(例如，至少一記憶體胞儲存一比較值)。一比較運算可經擴展以包含比較一32位元比較值與儲存於陣列中之資料。例如，可將若干記憶體胞之比較值彙總於一累加器中(如上文描述)以判定是否存在匹配一32位元比較值之一比較值集合。
本發明之實施例不限於圖2及圖3中所繪示之特定感測電路組態。例如，根據本發明之若干實施例，不同計算組件電路可用以執行邏輯運算。
圖4繪示根據本發明之若干實施例之用於執行一比較運算之一方法之一實例。在方塊470，該方法包含將一記憶體陣列(例如，圖3中之330)之一輸入/輸出(IO)線(例如，圖2中之266-1)預充電至一預充電電壓。(例如)可將IO線(例如，一本地IO線)預充電至對應於一特定資料值之一電壓，諸如一供應電壓(例如，對應於邏輯1之Vcc)或一參考電壓(例如，對應於邏輯0之一接地電壓)。若干實施例可包含將一記憶體陣列之一LIO_線(例如，圖2中之266-2)預充電至一預充電電壓。 LIO_線所預充電至之電壓可係LIO線所預充電至之一電壓之一反相。
在方塊472，該方法包含判定儲存於記憶體陣列中之資料是否匹配一比較值。該比較值可係由一外部主機(例如，一外部處理器)及/或一晶粒上控制器提供之一值。該比較值可包含控制電路嘗試判定是否儲存於一記憶體陣列中之至少一記憶體胞中之若干不同資料值。該比較值可儲存於若干記憶體胞中。例如，資料可儲存於一個、兩個、三個等記憶體胞中。一匹配可係指由控制電路提供之一比較值儲存於陣列之至少一記憶體胞中之一判定。比較值未儲存於至少一記憶體胞中之一判定可指示不存在一匹配。
在方塊474，可藉由啟動記憶體陣列之若干列線而判定儲存於記憶體陣列中之資料是否匹配一比較值之判定。該若干列線可基於該等列線之一特性而選擇性地啟動。該若干列線可包含由一控制器(例如，一外部主機、一晶粒上控制器)預先判定之特定列線。
在方塊476，可藉由感測耦合至該若干列線之若干記憶體胞而判定儲存於記憶體陣列中之資料是否匹配一比較值之判定。可藉由感測放大器感測記憶體陣列之列線之記憶體胞之電壓，且可啟動行解碼線以將該等感測放大器(及對應記憶體胞)之電壓提供至LIO線。
在方塊478，可藉由感測LIO線之預充電電壓是否回應於對應於若干記憶體胞之選定行解碼線之啟動而改變來判定儲存於記憶體陣列中之資料是否匹配一比較值之判定。例如，可將LIO線預充電至對應於一邏輯1之一供應電壓(例如，Vcc)。記憶體陣列中之一記憶體胞可儲存對應於一控制器設法定位(例如，匹配)之一比較值之一資料值(例如，邏輯0)。當記憶體胞經啟動且該胞之電壓(例如，經由對應感測放大器)提供至LIO線時，若藉由該胞儲存之資料值匹配比較值(例如，若藉由該胞儲存之資料值係一邏輯0)，則該LIO線上之電壓(例如，預充電電壓)將下降。次要感測放大器可偵測到電壓之下降且判 定已發生一匹配。可將匹配之判定報告至提供比較值之電路(例如，一晶粒上控制器、一外部主機等)及/或提供至某一其他控制電路以供進一步使用。若判定一匹配，則可執行進一步操作以判定陣列內發生該匹配之一特定位置(例如，胞或若干胞)。周邊控制邏輯可讀取一資料路徑以判定記憶體陣列之比較狀態。定位匹配可包含一搜尋方法(例如，二元搜尋)以判定匹配記憶體陣列中之哪一記憶體胞。匹配可發生在若干記憶體胞(例如，零個記憶體胞、一個記憶體胞或複數個記憶體胞)處。
儘管本文中已繪示並描述特定實施例，然一般技術者將明白，經計算以達成相同結果之一配置可替代所展示之特定實施例。本發明意欲涵蓋本發明之一或多項實施例之調適或變動。應瞭解，已以一闡釋性方式而非一限制方式進行上文描述。熟習此項技術者在檢閱上文描述之後將明白上文實施例與本文中未具體描述之其他實施例之組合。本發明之一或多項實施例之範疇包含其中使用上文結構及方法之其他應用。因此，應參考隨附申請專利範圍及此等申請專利範圍所授權之等效物之全部範圍而判定本發明之一或多項實施例之範疇。
在前述實施方式中，為簡化本發明之目的，將一些特徵集合於一單一實施例中。本發明之此方法不應被解釋為反映本發明之所揭示實施例必須使用比明確陳述於各技術方案中更多之特徵之一意圖。實情係，如以下申請專利範圍反映，本發明標的在於少於一單一所揭示實施例之全部特徵。因此，特此將以下申請專利範圍併入實施方式中，其中各技術方案獨立地作為一單獨實施例。
204‧‧‧字線/列線
205-1至205-M‧‧‧感測線
206-1至206-P‧‧‧感測放大器
218-1‧‧‧電晶體
218-2‧‧‧電晶體
260-1至260-N‧‧‧記憶體胞(MC)
264-1至264-R‧‧‧行解碼線(CD-1)至(CD-R)
266-1‧‧‧輸入/輸出線(IO)
266-2‧‧‧輸入/輸出線(IO_)
268‧‧‧次要感測放大器(SSA)

Claims (25)

  1. 一種執行一比較功能之方法，其包括：將一記憶體陣列之一輸入/輸出(IO)線充電至一電壓；藉由以下步驟判定儲存於該記憶體陣列中之資料是否匹配一比較值：啟動該記憶體陣列之若干存取線；感測耦合至該若干存取線之若干記憶體胞；及感測該IO線之該電壓是否回應於對應於該若干記憶體胞之選定解碼線之啟動而改變。
  2. 如請求項1之方法，其中對一IO線充電包含將該記憶體陣列之一IO線預充電至一預充電電壓。
  3. 如請求項1之方法，其中將該IO線充電至該電壓包含將該IO線充電至一供應電壓。
  4. 如請求項3之方法，其中該供應電壓對應於1之一資料值。
  5. 如請求項1之方法，其中將該IO線充電至一電壓包含將該IO線充電至一接地電壓。
  6. 如請求項5之方法，其中該接地電壓對應於0之一資料值。
  7. 如請求項1至6中任一項之方法，其中啟動選定解碼線包括啟動該陣列之該等解碼線之一子集。
  8. 如請求項7之方法，其包含基於該子集之一準則集合而判定解碼線之該子集。
  9. 一種裝置，其包括：一記憶體胞陣列；控制電路，其耦合至該陣列且經組態以引起：將該陣列之一本地輸入/輸出(LIO)線預充電至一預充電電 壓；及選擇性地啟動該陣列之存取線及解碼線；及感測電路，其耦合至該陣列且經組態以：感測耦合至一經啟動存取線之若干選定記憶體胞；及判定該LIO線之該預充電電壓是否回應於對應於該若干選定記憶體胞之解碼線之啟動而改變。
  10. 如請求項9之裝置，其中該控制電路包括一晶粒上控制器。
  11. 如請求項9之裝置，其中該控制電路包括一外部主機。
  12. 如請求項9之裝置，其中該預充電電壓對應於一特定資料值，且該LIO線之該預充電電壓之一經判定改變指示對應於一經啟動解碼線之一選定記憶體胞儲存除該特定資料值外之一資料值。
  13. 如請求項9之裝置，其中該感測電路包括經組態以偵測該LIO線之該預充電電壓是否改變之一次要感測放大器。
  14. 如請求項9至13中任一項之裝置，其中該LIO線之該預充電電壓之一經判定改變指示一記憶體胞中之資料匹配一比較值。
  15. 一種裝置，其包括：一記憶體胞陣列；控制電路，其耦合至該記憶體陣列且經組態以引起將該記憶體陣列之一輸入/輸出(IO)線充電至一電壓；及感測電路，其耦合至該記憶體陣列且包括：若干主要感測放大器，其等耦合至互補感測線之各自對；若干累加器，其等耦合至該若干主要感測放大器；一次要感測放大器，其耦合至該IO線且經組態以感測該IO線之該電壓是否回應於該陣列之選定解碼線之啟動而改變以判定儲存於該陣列中之資料是否匹配一比較值。
  16. 如請求項15之裝置，其中該等累加器之各者包括： 一第一傳遞電晶體，其具有耦合至一對互補感測線之一第一感測線之一第一源極/汲極區域；一第二傳遞電晶體，其具有耦合至該對互補感測線之一第二感測線之一第一源極/汲極區域；及一第一對交叉耦合電晶體及一第二對交叉耦合電晶體。
  17. 如請求項16之裝置，其中該裝置經組態以執行一邏輯運算，該邏輯運算包括對由該對互補感測線之至少一者上之一信號表示之一資料值執行一累加運算。
  18. 如請求項17之裝置，其中該信號係透過該若干主要感測放大器之至少一者提供至該IO線。
  19. 如請求項18之裝置，其中將一IO線充電至一電壓包含將該記憶體陣列之一IO線預充電至一預充電電壓。
  20. 如請求項19之裝置，其中該信號係提供至該次要感測放大器，且其中該次要感測放大器在該信號對應於不同於該預充電電壓之一電壓時偵測該預充電電壓之一改變。
  21. 如請求項17之裝置，其中該累加器經組態以接收一反相信號，其中啟動該反相信號使儲存於該累加器中之一資料值反相且將對應於該反相資料值之一信號驅動至該對互補感測線之一者上。
  22. 如請求項21之裝置，其中該對互補感測線經組態以將對應於該反相資料值之該信號提供至該若干主要感測放大器之至少一者。
  23. 如請求項22之裝置，其中該若干主要感測放大器之該至少一者經組態以將該反相資料值提供至IO_線，其中該IO_線經組態以將該反相資料值提供至該次要感測放大器。
  24. 如請求項23之裝置，其中該IO_線係充電至一接地電壓，且其中 該次要感測放大器在對應於該反相資料值之該信號係大於一接地電壓之一電壓時偵測該電壓之一改變。
  25. 一種裝置，其包括：一記憶體胞陣列；控制電路，其耦合至該陣列且經組態以進行下列動作作為一比較運算之部分：引起將該陣列之一本地輸入/輸出(LIO)線預充電至一預充電電壓；引起選擇性地啟動該陣列之存取線；及引起選擇性地啟動該陣列之解碼線；及感測電路，其耦合至該陣列且經組態以：感測耦合至複數個經選擇性啟動之存取線之記憶體胞；及感測該LIO線之該預充電電壓是否回應於對應於該等記憶體胞之複數個該等解碼線之選擇性啟動而改變；其中該預充電電壓回應於該複數個行解碼線之該選擇性啟動而改變之一判定指示耦合至該複數個經選擇性啟動之存取線之該等記憶體胞之至少一者儲存匹配一比較值之一資料值。
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