CN104981899A - 具有石墨烯屏蔽体的三维(3d)集成电路(3dic)以及相关的制造方法 - Google Patents
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Abstract
公开了一种具有石墨烯屏蔽体的三维(3-D)集成电路(3DIC)。在某些实施例中，在3DIC的两个相邻层级(34，52)之间设置至少一层石墨烯层(38)。石墨烯层是由纯碳制成的、具有原子以规则六边形图案排列的至少一个原子厚度的片状层。石墨烯层可以被设置在3DIC中任意层数的相邻层级之间。在示例性实施例中，石墨烯层提供了3DIC中相邻层级或相邻层之间的电磁干扰屏蔽体，以便减少层级之间的串扰。在其它示例性实施例中，石墨烯层可以被设置在3DIC中，以便提供引导热量朝向3DIC的周边区域并向3DIC的周边区域散发热量的散热器。在一些实施例中，石墨烯层被配置为提供EMI屏蔽体和热屏蔽体两者。
Description
优先申请
本申请要求2013年2月12日提交的，名称为“THREE-DIMENSIONAL(3-D)INTEGRATED CIRCUITS(3DICS)WITHGRAPHENE SHIELD,AND RELATED COMPONENTS AND METHODS”，序列号为13/765,061的美国专利申请的优先权，其通过全文引用的方式并入本文中。
相关申请
本申请与2013年2月12日提交的，名称为“ION REDUCED,IONCUT-FORMED THREE DIMENSIONAL,INTEGRATED CIRCUITS(3DICS),AND RELATED METHODS AND SYSTEMS”，序列号为13/765,080的美国专利申请相关。
背景技术
I.本公开内容的领域
本公开内容的技术涉及三维集成电路(3DIC)。
II.背景
移动通信设备已经在当前社会中变得常见。这些移动设备的流行部分地由现在在这样的设备上实现的许多功能所驱使。对这样的功能的需求增加了处理能力要求，并产生了对更强大的电池的需要。在移动通信设备壳体的有限空间内，电池与处理电路进行竞争。这些因素和其它因素有助于电路内的部件和功耗的持续小型化。
部件的小型化影响处理电路的所有方面，包括在处理电路中的晶体管和其它无功元件。一种小型化技术涉及不仅在x-y坐标系中，还在z-坐标系中布置集成电路。也就是说，当前的小型化技术使用三维(3D)集成电路(IC)(3DIC)来实现较高的器件封装密度、较低的互连延迟和较低的成本。当前，存在几种技术来制造或形成3DIC。
用于形成3DIC的第一种技术是选择性外延层生长。选择性外延层生长可以产生可接受的像样品质的IC，但是由于与工艺相关联的严格要求，这种技术是昂贵的。用于形成3DIC的第二种技术是晶圆上晶圆制造技术，据此，将电子部件分别构建在两个或更多个半导体晶圆上。将该两个或更多个半导体晶圆堆叠、对准、接合和划片成3DIC。需要并提供硅通孔(TSV)以实现在堆叠的晶圆之间的电连接。由于IC在各个层上的互相依赖，在堆叠的晶圆中的任何一个晶圆的未对准或TSV缺陷会导致整个缺陷的集成电路。用于形成3DIC的第三种技术是晶圆上管芯技术，据此将电子部件构建在两个半导体晶圆上。在这种技术中，一个晶圆被切片，并且将切割的管芯对准并接合到第二晶圆的管芯座上。这种晶圆上管芯技术还会经受对准的问题。用于形成3DIC的第四种技术是管芯上管芯技术，据此将电子部件构建在多个管芯上，并且随后将其堆叠、对准和接合。这种方法经受相同的未对准的问题，这个问题可能致使最后的3DIC不可用。
用于形成3DIC的第五种技术是单片技术，由此将电子部件和它们的连接件构建在单个半导体晶圆上的层中。通过离子切割工艺来将这些层进行组装。以这种方式使用这些层消除了对精确对准和TSV的需求。在单片方法中，准备了在其上具有集成部件的受主晶圆。在受主晶圆的顶面上形成氧化层。通过使施主晶圆经受离子(通常是氢)注入工艺来准备施主晶圆。随后将具有离子注入的施主晶圆的表面堆叠到受主晶圆的氧化层上。受主晶圆的氧化层通过退火工艺与施主晶圆的表面接合。施主晶圆随后被移除，将硅层转移到受主晶圆。在转移的硅层上方循序地制造另外的电子部件和互连件。相比于外延生长，单片技术不是那么昂贵，并且消除了未对准的风险，得到了比依赖于晶圆与晶圆对准、晶圆与管芯对准或者管芯与管芯对准的技术更多的功能器件。
单片方法使得集成电路具有较小覆盖区，但是，三维集成电路中的有源部件的密度产生了比简单的二维集成电路相对高的热量。高的温度会负面影响电路中有源部件的性能。此外，通过将电路布置在三维中而不只是在二维中还产生了电路之间针对电磁干扰(EMI)或者串扰的新机会。EMI还负面影响电路中有源部件的性能。
发明内容
在详细描述中所公开的实施例包括具有石墨烯屏蔽体的三维(3-D)集成电路(3DIC)。还公开了相关的部件和方法。在本文中所公开的某些实施例中，在3DIC的相邻两个层级之间设置至少一层石墨烯层。石墨烯层是由纯碳制成的、具有原子以规则六边形图案排列的至少一个原子厚度的片状层。石墨烯层可以被设置在3DIC中任意层数的相邻层级之间。在示例性实施例中，石墨烯层提供了在3DIC中的相邻层级或者相邻层之间的电磁干扰(EMI)屏蔽体，以便减少在层级之间的串扰。在3DIC中相邻层级中的部件之间的干扰会负面影响3DIC的性能。在其它示例性实施例中，石墨烯层可以被设置在3DIC中，以便提供引导热量朝向周边区域或3DIC的散热器，并向周边区域或3DIC的散热器散热的散热器。在一些实施例中，石墨烯层被配置为提供EMI屏蔽体和热屏蔽体两者。
就这点而言，在一个实施例中，公开了一种单片3DIC，所述3DIC包括第一半导体集成电路层级，所述第一半导体集成电路层级包括第一部件。所述3DIC还包括第二半导体集成电路层级，所述第二半导体集成电路层级包括第二部件，所述第二部件相对于所述第一半导体集成电路层级垂直设置。3DIC还包括至少一层石墨烯层，所述至少一层石墨烯层被设置在所述第一半导体集成电路层级与所述第二半导体集成电路层级之间，以使得所述至少一层石墨烯层既不是所述第一部件的部分也不是所述第二部件的部分。
在另一个实施例中，公开了一种单片三维集成电路。所述3DIC包括第一单元，所述第一单元用于提供包括第一部件的半导体层级。所述3DIC还包括第二单元，所述第二单元用于提供包括第二部件的半导体层级，所述第二部件相对于用于提供所述半导体层级的所述第一单元垂直设置。所述3DIC还包括至少一层石墨烯层，所述至少一层石墨烯层被设置在用于提供所述半导体层级的所述第一单元和所述第二单元之间，以使得所述至少一层石墨烯层既不是所述第一部件的部分也不是所述第二部件的部分。
在另一个实施例中，公开了一种形成单片三维集成电路的方法。所述方法包括提供包括第一部件的第一半导体层级。所述方法还包括在所述第一半导体层级的表面上方设置至少一层石墨烯。所述方法还包括将所述第一部件与所述至少一层石墨烯电隔离。所述方法还包括在所述至少一层石墨烯上方提供包括第二部件的第二半导体层级，使得所述至少一层石墨烯位于所述第一半导体层级与第二半导体层级之间，并且，将所述第二部件与所述至少一层石墨烯电隔离。
附图说明
图1A-图1D示出了在用于组装三维(3-D)集成电路(IC)(3DIC)的离子切割工艺中的示例性传统步骤；
图2示出了阐述用于离子切割的示例性传统工艺的流程图；
图3示出了在3DIC的构造中的示例性石墨烯转移；
图4示出了在3DIC的构造中的示例性蚀刻步骤；
图5示出了在3DIC的构造中的示例性硅转移步骤；
图6示出了在3DIC的构造中的示例性第二层级的创建步骤；
图7示出了包括石墨烯屏蔽体的示例性完成的3DIC；
图8示出了图7的3DIC沿着线8-8的示例性横截面视图；
图9是示出了用于如图3-图8中示出的3DIC的构造的示例性工艺的流程图；以及
图10是示例性的基于处理器的系统的框图，该基于处理器的系统可以包括图8的屏蔽的3DIC。
具体实施方式
现在参照附图，描述了本公开内容的几个示例性实施例。本文使用词语“示例性”以表示“充当示例、实例或者说明”。本文所描述的作为“示例性”的任何实施例并不必被解释为比其它实施例优选或有利。
在详细描述中所公开的实施例包括具有石墨烯屏蔽体的三维(3-D)集成电路(3DIC)。还公开了相关部件和方法。在本文所公开的某些实施例中，在3DIC的两个相邻层级之间设置至少一层石墨烯层。石墨烯层是由纯炭制成的，具有原子以规则六边形图案排列的至少一个原子厚度的片状层。石墨烯层可以被设置在3DIC中任意数量的相邻层级之间。在示例性实施例中，石墨烯层提供了在3DIC中的相邻层级或者层之间的电磁干扰(EMI)屏蔽，以便减少在层级之间的串扰。在3DIC中相邻层级中的部件之间的串扰会负面影响3DIC的性能。在其它示例性实施例中，石墨烯层可以被设置在3DIC中，以便提供指导热量朝向3DIC的周边区域，并向3DIC的周边区域散热的散热器。在一些实施例中，石墨烯层被配置为提供EMI屏蔽和热屏蔽两者。
在对包括热屏蔽体和EMI屏蔽体的经屏蔽的3DIC的实施例进行讨论之前，参照图1A-图1D和图2提供了在三维集成电路的组装中所使用的传统工艺的简要回顾。下面参照图3开始对具有热屏蔽体和EMI屏蔽体的三维集成电路的示例性实施例的讨论。
就这点而言，图1A示出了用于创建三维集成电路(3DIC)的传统工艺的第一步骤。具体地，提供了具有诸如硅(Si)衬底之类的衬底12的受主晶圆10。衬底12可以被称为衬底单元。如所公知的，在衬底12上生长第一层级电子部件(一般标识为14)。在电子部件14上生长氧化层16。同时准备施主晶圆18。施主晶圆18可以被称为施主单元。施主晶圆18还可以是硅材料。施主晶圆18使用离子进行注入，以形成离子化区域22，其有效地将处理部分20与施主部分24分隔开。传统的注入工艺允许创建局部化的高浓度区域(有时称为Delta注入区)。在示例性工艺中，离子是氢离子。在施主部分24上生长氧化层26。
参照图1B，将施主晶圆18堆叠在受主晶圆10的顶部，以使得氧化层16与氧化层26接触。氧化层16、26可以称为用于接合的单元。氧化层16、26进行接合，并且通过相对低温度的工艺(例如，在大约250℃与350℃之间)进行退火。如在图1C中所示出的，在退火之后，将施主晶圆18从受主晶圆10解理。如公知的，氧化层26、施主部分24和离子化区域22的解理部分22A保持附接于受主晶圆10，并且，离子化区域22的剩余部分22B保持在施主晶圆18的处理部分20上。
在解理之后，参照图1D，在施主部分24上生长另外的电子部件28(例如晶体管)，以便形成第二层级电子部件30。可以通过重复该工艺来创建除了第二层级电子部件30以外的附加层级电子部件(未示出)，以创建多级3DIC或多层级3DIC。
采用图1A-图1D提供了对示例性传统离子切割工艺50的视觉描绘，该传统离子切割工艺50进一步在图2中以流程图形式呈现。传统离子切割工艺50从准备受主晶圆10(框52)开始。准备受主晶圆10涉及准备衬底12，并且可以涉及掺杂、固化、切割或者如公知的其它技术。一旦准备好，在受主晶圆10上生长第一层级电子部件14(框54)。一旦生长了电子部件14，在受主晶圆10上生长氧化层16(框56，也参见图1A)。
继续参照图2，同时地或相继地将离子注入施主晶圆18中，以形成离子化区域22(框58，也参见图1A)。如上面所指出的，在示例性实施例中，离子是氢离子。同样在施主晶圆18上生长氧化层26。将施主晶圆18设置在受主晶圆10上(框60，也参见图1B)。对施主晶圆18进行退火(通常在大约250到350℃的温度范围)(框62)，融合氧化层16、26。退火发生直至发生离子化区域22的裂开为止，这使得施主部分24和解理部分22A能够从施主晶圆18转移到受主晶圆10。这种转移被称为对施主晶圆18进行解理(框64，也参见图1C)。在示例性方法中，施主部分24大约是1.3μm厚。在转移之后，可以在施主部分24上生长第二层级电子部件30(框66，也见图1D)。
在诸如图2中示出的、产生3DIC 26的传统工艺中，随着在电子部件层级14、24内的电子部件消耗功率，热量可以在3DIC内积累。同样地，在第一层级电子部件14内的电子部件可以与第二层级电子部件24内的电子部件具有串扰，并且反之亦然。随着电子部件层级数量的增加，加剧了热量和串扰问题。散热失败通过改变3DIC中材料的传导性来负面影响3DIC，并且如果热量太大，则材料可能以毁坏3DIC的这种方式融化并回流。同样地，虽然串扰不可能破坏器件，但其使得旨在用于操作第一器件的信号出现在第二器件中，使得第二器件以不期望的方式工作。替代地，这种串扰可能超越相关法律和规定(例如，联邦通信委员会(FCC)对设备可以发射的EMI辐射量施加限制)。不能遵守这样的法律和规定可能意味着设备不能在某些管辖范围或市场中销售(例如，不能遵守FCC规定意味着设备可能不能在美国工作)。本公开内容通过提供在电子部件层级之间的EMI屏蔽体来解决这些问题。在示例性实施例中，EMI屏蔽体是石墨烯层。如上面所提到的，石墨烯层是由纯碳制成的、具有原子以规则六边形图案排列的至少一个原子厚度的片状层。石墨烯的导热性是铜的十倍，并且电子迁移率是硅的一百倍，由此作为热屏蔽体和减少串扰的EMI屏蔽体两者。
就这点而言，图3示出了具有衬底32的构造中的3DIC 30。在示例性实施例中，衬底32可以是硅。已经使用传统工艺在衬底32上创建了第一层级电子部件34。氧化层36可以包封第一层级电子部件34或者位于第一层级电子部件34的顶部。使用聚甲基丙烯酸甲酯(PMMA)保持衬底40来将石墨烯层38应用到氧化层36。使用这样的PMMA保持衬底40来转移石墨烯在本领域中是公知的。在示例性实施例中，石墨烯层38由单个原子厚度的石墨烯层形成。在另一个示例性实施例中，石墨烯层由大于一个原子厚度的石墨烯层(即，双层)形成。应当指出，为了使石墨烯层38成为有效的EMI屏蔽体，石墨烯层38不与第一层级电子部件34内的任何部件电连接。也就是说，将石墨烯层38与第一层级电子部件34内的部件电隔离。
如在图4中所示出的，PMMA保持衬底40被移除，并且石墨烯层38被蚀刻成包括一个或多个孔隙42的图案。在示例性实施例中，孔隙42邻近构造中的3DIC 30的边缘44。在另一个示例性实施例中，孔隙42与构造中的3DIC 30的边缘44是内部有间隔的。在示例性实施例中，如所期望的，蚀刻可以通过任何传统技术来执行。在另一个示例性实施例中，孔隙42通过除了蚀刻以外的某些工艺来制作。
参照图5，在石墨烯层38上方生长氧化层46，并且氧化层46用于通过离子切割工艺接合到另一硅层48。如在2013年2月12日提交的、名称为“ION REDUCED,ION CUT-FORMED THREE-DIMENSIONAL(3D)INTEGRATED CIRCUITS(IC)(3DICS),AND RELATED METHODS ANDSYSTEMS”，序列号为13/765,080的美国专利申请中所描述的，硅层48的顶部50可以经受化学机械抛光和氧化工艺以移除过量的离子。如所期望的，可以对新的硅层48进行掺杂(例如，p-掺杂，n-掺杂)。其它公知的准备步骤仍然可以包括在离子切割工艺中。
参照图6，在构造中的3DIC 30上，并且尤其是在硅层48上生长第二层级电子部件52。可以相对于孔隙42来设置个体部件53以实现过孔(如下面将参照图7和图8进行解释的)。应当指出，为了使石墨烯层38成为有效的EMI屏蔽体，石墨烯层38不与第二层级电子部件52内的任何部件53电连接。也就是说，将石墨烯层38与第二层级电子部件52内的部件53电隔离。
参照图7，示出了完成的3DIC 54。完成的3DIC 54包括位于边缘44邻近处的热过孔56。石墨烯层38是极好的热导体，并且连同热过孔56，热量可以从3DIC 54的中心传递到边缘44并散发。在示例性实施例中，热过孔直接连接到石墨烯层38，使得热量可以从石墨烯层38传递到热过孔56。邻近边缘44布置热过孔56允许热量从完成的3DIC 54的边缘散发。这种散热有效地将热量从完成的3DIC 54的中心部分移除，并且保护完成的3DIC 54免于过热。另外，层级间连接过孔58可以被设置为相对于边缘44内部有间隔的，以便连接第一层级电子部件34中的个体部件和第二电子部件层级52中的个体部件。层级间连接过孔58延伸通过孔隙42。在示例性实施例中，石墨烯层38连接到地(未示出)。通过将石墨烯层38接地，创建了有效的EM屏蔽体。
在图8中示出了完整的3DIC 54的横截面视图。如所示出的，完整的3DIC 54可以包括内部的热过孔56(示出了一个)以及内部设置的层级间连接过孔58。如在图7和图8两者中所示出的，将层级间连接过孔58与孔隙42的边缘隔开，以便在石墨烯层38和层级间连接过孔58之间不存在电连接。在层级间连接过孔58与石墨烯层38之间保持电气隔离有助于保持石墨烯层38的EM屏蔽功能。
虽然没有示出，但应当意识到，可以在第二电子部件层级52的顶部上生长另外的层级。这些另外的层级还可以具有如本文所讨论的设置在它们之间的屏蔽体。作为进一步的备注，虽然在本文的示例性实施例中描述了石墨烯，但是其它物质也可以用作屏蔽体。然而，由于石墨烯组合了导热性和电子迁移率，因此，它很好地适合于本文所概述的目的。相应地，其它适当的材料可以包括具有大于铜至少五倍的导热性以及大于硅至少五十倍的电子迁移率的那些材料。
参照图9对形成完整的3DIC 54的工艺70进行了总结。工艺70从准备衬底32(框72)开始。如公知的，这种准备可以包括掺杂、创建隔离槽等等。工艺70以生长第一层级电子部件34(框74)而继续进行。如公知的，这种生长可以通过外延生长、气相淀积、蚀刻，诸如此类来完成。
继续参照图9，工艺70通过在第一层级电子部件34上设置石墨烯层38(框76)而继续进行。如之前所描述的，石墨烯层38可以通过使用PMMA保持衬底40进行转移。工艺70以通过预定义的图案在石墨烯层38中创建孔隙42(框78)来继续。如所期望的，孔隙42可以通过蚀刻等工艺来创建。
继续参照图9，工艺通过将第二硅层48转移到石墨烯层38上方(框80)而继续进行。如所公知的，第二硅层48可以通过离子切割工艺来进行转移。可以对第二硅层48进行处理(框82)以移除离子、平整表面，并且针对第二电子部件层级52另外准备第二硅层48。也就是说，在对第二硅层48进行处理之后，定义了第二电子部件层级52(框84)。如已充分理解的，可以通过外延生长、气相淀积、蚀刻，诸如此类来定义第二电子部件层级52。随后形成过孔56和过孔58(框86)，并且完成了图7的完成的3DIC 54。如果期望的话，可以提供具有另外的屏蔽层的另外的电子部件层级。
可以在任何基于处理器的设备中提供根据本文所公开的实施例的具有石墨烯屏蔽体的3DIC，或者将它集成到任何基于处理器的设备中。例如，并非限制，包括机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、计算机、便携式计算机、台式计算机、个人数字助理(PDA)、监控器、计算机监控器、电视机、调谐器、收音机、卫星收音机、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器以及便携式数字视频播放器。
就这点而言，图10示出了可以采用3DIC的基于处理器的系统110的示例。在该示例中，基于处理器的系统110包括一个或多个中央处理单元(CPU)112，每个CPU包括一个或多个处理器114。CPU 112可以具有高速缓冲存储器116，该高速缓冲存储器116耦合到处理器114用于对暂时存储的数据进行快速存取。CPU 112耦合到系统总线118，并且可以交互耦合在基于处理器的系统110中所包括的主设备和从设备。如所公知的，CPU112通过在系统总线118上交换地址、控制和数据信息来与这些其它设备进行通信。例如，CPU 112可以向存储控制器120传输总线事务请求。尽管没有在图10中示出，但是可以提供多系统总线118，其中每条系统总线118构成不同的结构。
其它设备可以连接到系统总线118。如在图10中所示出的，作为示例，这些设备可以包括存储系统122、一个或多个输入设备124、一个或多个输出设备126、一个或多个网络接口设备128以及一个或多个显示控制器130。输入设备124可以包括任何类型的输入设备，包括但不限于输入键盘、开关、声音处理器等等。输出设备126可以包括任何类型的输出设备，包括但不限于音频、视频、其它可视指示器等等。网络接口设备128可以是被配置为允许数据到/从网络132进行交换的任何设备。网络132可以是任何类型的网络，包括但不限于有线或无线网络、专用或公用网络、局域网(LAN)、广域局域网(WLAN)和互联网。网络接口设备128可以被配置为支持所期望的任何类型的通信协议。存储系统122可以包括一个或多个存储单元124(0-N)。
CPU 112还可以被配置为通过系统总线118访问显示控制器130，以便控制发送到一个或多个显示器136的信息。显示控制器130经由一个或多个视频处理器138向显示器136发送信息以进行显示，视频处理器138将要显示的信息处理成适合于显示器136的格式。显示器136可以包括任何类型的显示器，包括但不限于阴极射线管(CRT)、液晶显示器(LCD)、等离子体显示器等等。
本领域技术人员还将意识到，结合本文所公开的实施例所描述的各种示例性逻辑框、模块、电路以及算法可以被实现为电子硬件、存储在存储器或在另一种计算机可读介质中，并且由处理器或其它处理设备执行的指令，或者两者的组合。作为示例，本文所描述的仲裁器、主设备和从设备可以在任何电路、硬件部件、集成电路(IC)或IC芯片中采用。本文所公开的存储器可以是任何类型和大小的存储器，并且可以被配置为存储所期望的任何类型的信息。为了清楚地示出这种可互换性，各个示例性的部件、框、模块、电路和步骤已经从其功能性的角度作出以上普遍性描述。如何实现这种功能性取决于具体应用、设计选择和/或施加在整体系统上的设计约束。技术人员可以针对各种特定应用以不同方式来实现所描述的功能性，但是这样的实现决策不应当被解释为引起脱离本公开内容的范围。
结合本文所公开的实施例所描述的各示例性逻辑框、模块和电路可以使用处理器、DSP、专用集成电路(ASIC)、FPGA或其它可编程逻辑器件、分立的门或晶体管逻辑、分立的硬件部件、或被设计为执行本文中描述的功能的它们的任意组合来实现或执行。处理器可以是微处理器，但是在替代方案中，处理器可以是任何常规的处理器、控制器、微控制器、或状态机。处理器还可以被实现为例如DSP与微处理器的组合的计算设备的组合、多个微处理器、与DSP核心协作的一个或多个微处理器、或者任何其它这种配置。
本文所公开的实施例可以包含在硬件中和存储在硬件中的指令中，并且可以驻留在例如随机存取存储器(RAM)、闪存、只读存储器(ROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)、寄存器、硬盘、可移动盘、CD-ROM、或本领域中所知的任何其他形式的储存介质中。示例性的存储介质耦合到处理器，使得处理器能够从/向储存介质读写信息。在替代方案中，储存介质可以被整合到处理器。处理器和储存介质可以驻留在ASIC中。ASIC可以驻留在远程站中。在替代方案中，处理器和储存介质可以作为分立部件驻留在远程站、基站或服务器中。
还应当指出，对在本文的示例性实施例的任何一个中所描述的操作步骤进行描述，以便提供示例和讨论。所描述的操作可以以除了所示出的顺序以外的许多不同顺序来执行。此外，在单个操作步骤中所描述的操作实际上可以在多个不同步骤中执行。另外，在示例性实施例中所讨论的一个或多个操作步骤可以进行组合。要理解的是，如对本领域技术人员来说将是显而易见的，在流程图中所示出的操作步骤可以经受许多不同的修改。本领域技术人员还将理解，信息和信号可以使用各种不同技术和技艺中的任意一项来表示。例如，贯穿上面的描述可以引用的数据、指令、命令、信息、信号、比特、符号和芯片可以由电压、电流、电磁波、磁场或磁粒子、光场或光粒子或它们的任意组合来表示。
提供了对本公开内容的以上描述以使得本领域任何技术人员能够实施或使用本公开内容。对于本领域技术人员来说，对本公开内容的各种修改将是显而易见的，并且在不脱离本公开内容的精神或范围的情况下，可以将本文所定义的一般性原理应用于其它变型。因此，本公开内容并非旨在限于本文所描述的示例和设计，而是要求保护与本文所公开的原理和新颖特征相一致的最广泛的范围。
Claims (20)
1.一种单片三维(3-D)集成电路(3DIC)，包括：
包括第一部件的第一半导体集成电路层级；
包括第二部件的第二半导体集成电路层级，所述第二部件相对于所述第一半导体集成电路层级垂直设置；以及
至少一层石墨烯层，所述至少一层石墨烯层被设置在所述第一半导体集成电路层级与所述第二半导体集成电路层级之间，以使得所述至少一层石墨烯层既不是所述第一部件的部分也不是所述第二部件的部分。
2.根据权利要求1所述的单片3DIC，其中，所述至少一层石墨烯层耦合到地，并提供所述第一半导体集成电路层级与所述第二半导体集成电路层级之间的电磁屏蔽。
3.根据权利要求1所述的单片3DIC，其中，所述至少一层石墨烯层被配置为传导热量离开在所述第一半导体集成电路层级和所述第二半导体集成电路层级中内部设置的有源元件。
4.根据权利要求1所述的单片3DIC，其中，所述至少一层石墨烯层定义至少一个孔隙。
5.根据权利要求4所述的单片3DIC，还包括传导过孔，所述传导过孔穿过所述至少一个孔隙，并耦合所述第一半导体集成电路层级中的第一有源部件与所述第二半导体集成电路层级中的第二有源部件。
6.根据权利要求1所述的单片3DIC，还包括热过孔，所述热过孔与所述至少一层石墨烯层热相接。
7.根据权利要求4所述的单片3DIC，其中，所述单片3DIC包括外部边缘，并且所述至少一个孔隙邻近所述外部边缘。
8.根据权利要求4所述的单片3DIC，其中，所述单片3DIC包括中心，并且所述至少一个孔隙邻近所述中心。
9.根据权利要求4所述的单片3DIC，其中，所述单片3DIC包括外部边缘，并且所述至少一个孔隙与所述外部边缘在内部是有间隔的。
10.根据权利要求7所述的单片3DIC，还包括穿过所述至少一个孔隙的热过孔。
11.根据权利要求1所述的单片3DIC，还包括将所述第一半导体集成电路层级与所述第二半导体集成电路层级进行接合的接合层，并且其中，所述至少一层石墨烯层位于所述第一半导体集成电路层级中的所述接合层的下方。
12.根据权利要求1所述的单片3DIC，还包括将所述第一半导体集成电路层级与所述第二半导体集成电路层级进行接合的接合层，并且其中，所述至少一层石墨烯层位于所述第二半导体集成电路层级中的所述接合层的上方。
13.根据权利要求11所述的单片3DIC，其中，所述接合层包括经退火的氧化层。
14.根据权利要求1所述的单片3DIC，所述单片3DIC被集成到半导体管芯中。
15.根据权利要求1所述的单片3DIC，还包括选自由以下构成的组的设备，并且所述单片3DIC被集成到所述设备中：机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、计算机、便携式计算机、台式计算机、个人数字助理(PDA)、监控器、计算机监控器、电视机、调谐器、收音机、卫星收音机、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器、以及便携式数字视频播放器。
16.一种单片三维(3-D)集成电路(3DIC)，包括：
第一单元，所述第一单元用于提供包括第一部件的半导体层级；
第二单元，所述第二单元用于提供包括第二部件的半导体层级，所述第二部件相对于用于提供所述半导体层级的所述第一单元垂直设置；以及
至少一层石墨烯层，将所述至少一层石墨烯层设置在用于提供半导体层级的所述第一单元与所述第二单元之间，以使得所述至少一层石墨烯层既不是所述第一部件的部分也不是所述第二部件的部分。
17.一种形成单片三维(3-D)集成电路(3DIC)的方法，包括：
提供包括第一部件的第一半导体层级；
将至少一层石墨烯设置在所述第一半导体层级的表面上；
将所述第一部件与所述至少一层石墨烯电隔离；以及
在所述至少一层石墨烯的上方提供包括第二部件的第二半导体层级，以使得所述至少一层石墨烯位于所述第一半导体层级与所述第二半导体层级之间，并且，所述第二部件与所述至少一层石墨烯电隔离。
18.根据权利要求17所述的方法，还包括在所述至少一层石墨烯中提供孔隙。
19.根据权利要求18所述的方法，还包括：传导过孔穿过所述孔隙以电耦合所述第一半导体层级中的第一元件与所述第二半导体层级中的第二元件。
20.根据权利要求18所述的方法，还包括：热过孔穿过所述孔隙以传导所述单片3DIC内的热量。
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| CN111403415A (zh) * | 2018-06-29 | 2020-07-10 | 长江存储科技有限责任公司 | 具有屏蔽层的三维存储器件及其形成方法 |
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| CN116598312B (zh) * | 2023-07-18 | 2024-06-28 | 苏州华太电子技术股份有限公司 | 一种三维集成电路 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20140225235A1 (en) | 2014-08-14 |
| WO2014126800A1 (en) | 2014-08-21 |
| US9536840B2 (en) | 2017-01-03 |
| JP6125669B2 (ja) | 2017-05-10 |
| JP2016511542A (ja) | 2016-04-14 |
| EP2956961A1 (en) | 2015-12-23 |
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