CN104252555A - 导线图案化 - Google Patents

导线图案化 Download PDF

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CN104252555A
CN104252555A CN201310439610.7A CN201310439610A CN104252555A CN 104252555 A CN104252555 A CN 104252555A CN 201310439610 A CN201310439610 A CN 201310439610A CN 104252555 A CN104252555 A CN 104252555A
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刘如淦
谢东衡
蔡宗杰
吴俊毅
李亮峣
丁至刚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供的方法包括在布局中放置两条导线。在布局中的两条导线的至少一部分上方放置两条切割线。切割线表示两条导线的切割部分，且在制造工艺限制内切割线彼此间隔开。在布局中连接两条切割线。在物理集成电路中，使用两条连接的平行切割线在衬底上方图案化两条导线。两条导线具有导电性。本发明提供了一种导线结构以及一种计算机可读介质。

Description

导线图案化
技术领域
本发明总体涉及集成电路领域，更具体地，涉及导线图案化。
背景技术
对于集成电路布局中，具有诸如最小间距或间隔的尺寸限制。在一些布局中，使用多晶硅切割（cut poly）（CPO）图案来切割诸如多晶硅线的导线，但是随着集成电路尺寸的缩小，一些布局方法受到光刻工艺的限制。期望提供克服本领域现状的缺点的方法。
发明内容
根据本发明的一个方面，提供了一种方法，包括：在布局中放置两条模制导线；在布局中的两条模制导线的至少一部分上方放置两条切割线，切割线指定两条模制导线的切割部分，并且切割线在制造工艺限制内彼此隔离；在布局中连接两条切割线；以及使用所连接的两条切割线，对设置在物理集成电路中的衬底上方的两条物理导线进行图案化。
优选地，该方法还包括：在衬底上方形成两条物理导线。
优选地，该方法还包括：在与两条模制导线不同的层中的两条切割线之间的位置处将连接导线放置在布局中的两条模制导线之间。
优选地，该方法还包括：在物理集成电路的衬底上方形成物理连接导线，物理连接导线在与两条物理导线不同的层中位于两条物理导线之间。
优选地，该方法还包括：在物理集成电路中的物理连接导线上方形成至少一个通孔，至少一个通孔电连接至物理连接导线。
优选地，图案化两条物理导线包括在位于衬底上方的两条物理导线上蚀刻掉与连接的两条切割线相对应的区域。
优选地，图案化的两条物理导线中的每一条都具有第一切角以及与第一切角不同的第二切角。
优选地，相对于两条导线的直角线，第一切角为0度。
优选地，相对于两条导线的直角线，第二切角介于10度至45度的范围内。
优选地，两条物理导线是多晶硅线。
优选地，两条物理导线是金属线。
根据本发明的另一方面，提供了一种导线结构，包括：衬底；以及两条导线，形成在衬底上方，其中，两条导线中的每一条都具有切割部分，切割部分具有第一切角和与第一切角不同的第二切角。
优选地，该导线结构还包括：位于两个导线的切割部分之间并且位于与两个导线在不同层中的连接导线。
优选地，该导线结构还包括：位于连接导线上方的至少一个通孔，至少一个通孔电连接至连接导线。
优选地，相对于两条导线的直角线，第一切角为0度。
优选地，相对于两条导线的直角线，第二切角介于10度至45度的范围内。
优选地，两条导线为多晶硅线。
优选地，两条导线为金属线。
根据本发明的又一方面，提供了一种计算机可读介质，计算机可读介质包括集成电路布局，集成电路布局包括：两条导线；两条切割线，设置在两条导线的至少一部分的上方，两条切割线彼此的间隔在制造工艺限制内，并且切割线指定两条导线的切割部分；以及连接切割线，连接两条切割线。
优选地，集成电路布局还包括：位于两个导线的切割部分之间并且位于与两个导线在不同层中的连接导线。
附图说明
现结合附图参考以下描述，其中：
图1A是根据一些实施例的导线结构的示例性集成电路布局的示图；
图1B是根据一些实施例的根据图1A中导线结构的示例性集成电路布局而制造的示例性物理集成电路的截面图；以及
图2A至图2D是生成图1A中的示例性集成电路布局和制造图1B中的示例性集成电路的中间步骤。
具体实施方式
下面详细论述本发明各个实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
此外，本发明可以在不同实例中重复参考数字和/或字母。这种重复用于简化和清楚的目的，并且其本身不表示所论述的不同实施例和/或布置之间的关系。此外，在本发明中，一个部件形成在、连接至和/或偶接至另一个部件上可以包括两个部件以直接接触的方式形成的实施例，也可以包括附加的部件可以形成在两个部件之间，使得两个部件不直接接触的实施例。并且，可以使用空间相对位置术语，例如，“下面”、“上面”、“水平”、“垂直”、“在….上方”、“在…上面”、“在…下方”、“在…下面”、“在…之上”、“在…之下”、“在…顶部”、“在…底部”等以及它们的衍生词（例如，“水平地”、“向下地”、“向上地”等），以便于描述如本发明中所示的一个部件与另一个部件之间的关系。空间相对位置术语旨在涵盖包括这些部件的器件的不同方位。
图1A是根据一些实施例的导线结构的示例性集成电路布局100的示图。集成电路布局100包括有源区102（其中形成有诸如晶体管的器件）、模制导线104（诸如多晶硅）、切割线106（诸如多晶硅切割（CPO）图案）、位于另一层的其他导线108（诸如金属层图案）以及通孔110。可以通过基于计算机的系统生成集成电路布局100，并且将其储存在计算机可读介质中。
布局100中模制导线104表示将要形成在衬底上方的物理集成电路中的电导线。模制导线104可以包括多晶硅或诸如金属层中的金属的其他导电材料。根据集成电路的设计，切割线106表示将在此位置的模制导线104去除以用于电连接/断开的切割部分或图案化区。
在示例性布局区111中，具有两条模制导线104以及覆盖两条模制导线104的一部分的两条切割线106a。在制造工艺中，两条切割线106a彼此的间距在制造工艺的限制内。例如，在一些实施例中，布局100中切割线106a之间的最小间距为0.08μm并且小于对切割线106a的光刻工艺限制。两条切割线106a的彼此间隔在0.13μm的工艺限制内。
为了有助于制造工艺，在布局100中，通过连接的切割线106b来连接两条切割线106a。如以下结合图2C至图2D所述，在制造工艺中，将连接后的切割线106a和106b一起蚀刻掉。
图1B是根据一些实施例的根据图1A中的导线结构的示例性集成电路布局100制造的示例性物理集成电路的截面图。截面图是沿着切割线A-A’截取的。
衬底101包括有源区102，并且包括硅或其他任何合适的材料。浅沟槽隔离（STI）区103位于有源区102之间以用于电隔离，并且浅槽隔离（STI）区103包括二氧化硅或其他任何合适的材料。示出的物理导线104具有用介电材料填充的切割部分105。切割部分105由在布局100中示出的切割线106a生成，这表示在制造工艺期间，将去除切割线106a区内的图1A中的模制导线104。在一些实施例中，物理导线104可以是多晶硅线。在其他实施例中，物理导线104可位于金属层中。
示出了在诸如金属层的不同层中的另一导线108a。金属层中的连接导线108a可以电连接多晶硅层中的两条物理导线104。示出的通孔110用于电连接至导线108（例如，金属层）。在一些实施例中，至少有一个通孔110设置在连接导线108的上方，其中该至少一个通孔110电连接至连接导线108。介电层109用于绝缘并且包括二氧化硅、氮化硅或其他任何合适的材料。
图2A至图2D是生成图1A中的示例性集成电路布局100和制造图1B中的示例性集成电路的中间步骤。在图2A中，在与图1A中的布局100相似的集成电路布局中示出了两条模制导线104和两条切割线106a。
在一些实施例中，两条模制导线104彼此平行，两条切割线106a彼此平行，并且两条模制导线104与两条切割线106a相交成直角。例如，模制导线104可以是多晶硅线或金属线。
切割线106a彼此的间隔在制造工艺的限制内。例如，在一些实施例中，对切割线106a的光刻工艺限制为0.13μm，而布局中切割线106a的最小间距为0.08μm。两条切割线106a彼此的间隔在0.13μm的工艺限制内。
在图2B中，两条切割线106a通过布局中的连接切割线106b连接以帮助制造工艺。在一些实施例中，将连接导线置于两条模制导线104之间并且其所在位置位于与两条模制导线104不同层（诸如另一个金属层）的两条切割线106a之间。
在图2C中，在集成电路制造中，合并的切割部分201基于切割线106a和106b。使用光刻工艺从物理导线104中一起蚀刻掉合并的切割部分201。值得注意的是，实际切除的部分并非如布局图案呈直线和直角。正如本领域所公知的，这是由于诸如光刻和蚀刻工艺的制造工艺所引入的不精确性而造成的。
在图2D中，继图2C中的蚀刻工艺之后，示出的两条物理导线104具有切角线202和204。在一些实施例中，切角线202是直线并且相对于导线104形成直角。在这种情况下，切角线202的切角为0度。作为比较，切角线204的切角θ1和θ2与切角线202的切角不同。在一些实施例中，切角θ1和θ2在10度至45度的范围内。
在一些实施例中，可使用在后续工艺中在不同层中制造的连接导线108来电连接两条物理导线104。
例如，可以将图2A至图2D中的技术应用于布局规则受限的高密度器件的栅极图案化。物理导线104可以是多晶硅栅极线，而连接导线108可以是金属层中的金属线。在其他实施例中，物理导线104可以是金属层中的金属线，而连接导线108可以是另一个金属层中的金属线。
使用上述方法，当切割图案的间距小于蚀刻工艺的间距限制时，可以实施诸如CPO图案的导线切割图案。例如，可以使用小于制造工艺限制（0.13μm）的0.080μm的CPO图案间距。
根据一些实施例，一种方法包括将两条模制导线放置在布局中。两条平行的切割线放置在布局中两条模制导线的至少一部分的上方。切割线指定两条导线的切割部分，并且切割线的彼此间距在制造工艺的限制内。在布局中，两条切割线是连接的。使用两条连接且平行的切割线在物理集成电路中的衬底上方图案化两条物理导线。
根据一些实施例，导线结构包括衬底和形成在衬底上方的两条物理导线。两条物理导线中的每一条都具有切割部分。切割部分具有第一切角和与第一切角不同的第二切角。
根据一些实施例，计算机可读介质包括集成电路布局。集成电路布局包括两条模制导线以及设置在两条模制导线的至少一部分的上方的两条平行的切割线。两条平行的切割线的彼此间隔在制造工艺限制内。切割线指定两条模制导线的切割部分。连接切割线连接两条平行的切割线。
本领域技术人员应该理解本发明可具有许多实施例的变形。尽管已经详细地描述了实施例及其优势，但应该理解，在不背离实施例的精神和范围的情况下，可以对本发明做各种不同的改变，替换和修改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器装置、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域普通技术人员应理解，根据本发明，可以利用现有的或今后将被开发的用于实施与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器装置、制造、物质组成、工具、方法或步骤。
上述方法实施例示出了示例性的步骤，但是没有必要按照所示顺序实施这些步骤。根据本发明的实施例的精神和范围，可以适当地对这些步骤进行添加、替换、改变顺序和/或删除。结合了不同权利要求的实施例和/或不同的实施例都在本发明的范围内并且在本领域的技术人员阅读完本发明之后，这些实施例对本领域的技术人员是显而易见的。

Claims (10)

1.一种方法，包括：
在布局中放置两条模制导线；
在所述布局中的所述两条模制导线的至少一部分上方放置两条切割线，所述切割线指定所述两条模制导线的切割部分，并且所述切割线在制造工艺限制内彼此隔离；
在所述布局中连接所述两条切割线；以及
使用所连接的所述两条切割线，对设置在物理集成电路中的衬底上方的两条物理导线进行图案化。
2.根据权利要求1所述的方法，还包括：在所述衬底上方形成所述两条物理导线。
3.根据权利要求1所述的方法，还包括：在与所述两条模制导线不同的层中的所述两条切割线之间的位置处将连接导线放置在所述布局中的所述两条模制导线之间。
4.根据权利要求3所述的方法，还包括：在所述物理集成电路的所述衬底上方形成物理连接导线，所述物理连接导线在与所述两条物理导线不同的层中位于所述两条物理导线之间。
5.根据权利要求4所述的方法，还包括：在所述物理集成电路中的所述物理连接导线上方形成至少一个通孔，所述至少一个通孔电连接至所述物理连接导线。
6.根据权利要求1所述的方法，其中，图案化所述两条物理导线包括在位于所述衬底上方的所述两条物理导线上蚀刻掉与连接的所述两条切割线相对应的区域。
7.根据权利要求1所述的方法，其中，图案化的所述两条物理导线中的每一条都具有第一切角以及与所述第一切角不同的第二切角。
8.一种导线结构，包括：
衬底；以及
两条导线，形成在所述衬底上方，
其中，所述两条导线中的每一条都具有切割部分，所述切割部分具有第一切角和与所述第一切角不同的第二切角。
9.根据权利要求8所述的导线结构，还包括：位于所述两个导线的所述切割部分之间并且位于与所述两个导线在不同层中的连接导线。
10.一种计算机可读介质，所述计算机可读介质包括集成电路布局，所述集成电路布局包括：
两条导线；
两条切割线，设置在所述两条导线的至少一部分的上方，所述两条切割线彼此的间隔在制造工艺限制内，并且所述切割线指定所述两条导线的切割部分；以及
连接切割线，连接所述两条切割线。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107305862A (zh) * 2016-04-19 2017-10-31 台湾积体电路制造股份有限公司 集成电路制造方法
CN107851613A (zh) * 2015-07-17 2018-03-27 高通股份有限公司 用于连接使用栅极切割分开的栅极区的器件和方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431381B2 (en) 2014-09-29 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. System and method of processing cutting layout and example switching circuit
US9837353B2 (en) * 2016-03-01 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Middle end-of-line strap for standard cell
CN110690215A (zh) * 2019-11-13 2020-01-14 上海华力微电子有限公司 基于FinFET小面积标准单元的版图结构
CN113517274A (zh) 2020-07-24 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1881223A (zh) * 2005-04-06 2006-12-20 Lsi罗吉克公司 具有可重定位处理器硬核的集成电路
US20090114903A1 (en) * 2007-05-25 2009-05-07 Kalburge Amol M Integrated Nanotube and CMOS Devices For System-On-Chip (SoC) Applications and Method for Forming The Same
US20100159685A1 (en) * 2008-12-19 2010-06-24 Harry Chuang Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut
US20110037175A1 (en) * 2009-08-13 2011-02-17 International Business Machines Corporation Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1201887B (de) * 1964-08-01 1965-09-30 Telefunken Patent Verfahren und Vorrichtung zum Einloeten von Transistoren od. dgl.
US4319118A (en) * 1980-06-18 1982-03-09 Gti Corporation Method of welding tantalum lead wires to tantalum capacitor anodes
US5247197A (en) 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
US5667940A (en) * 1994-05-11 1997-09-16 United Microelectronics Corporation Process for creating high density integrated circuits utilizing double coating photoresist mask
US7118988B2 (en) 1994-08-15 2006-10-10 Buerger Jr Walter Richard Vertically wired integrated circuit and method of fabrication
US6096636A (en) * 1996-02-06 2000-08-01 Micron Technology, Inc. Methods of forming conductive lines
US6242346B1 (en) 1997-08-13 2001-06-05 United Microelectronics Corporation Metallization for uncovered contacts and vias
TW417165B (en) * 1999-06-23 2001-01-01 Taiwan Semiconductor Mfg Manufacturing method for reducing the critical dimension of the wire and gap
US20110256308A1 (en) 2001-03-30 2011-10-20 Buerger Jr Walter Richard Algorithmic processing to create features
US6492073B1 (en) * 2001-04-23 2002-12-10 Taiwan Semiconductor Manufacturing Company Removal of line end shortening in microlithography and mask set for removal
US7169696B2 (en) 2003-06-24 2007-01-30 California Institute Of Technology Method for making a system for selecting one wire from a plurality of wires
US9070623B2 (en) 2004-12-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling gate formation for high density cell layout
JP4485460B2 (ja) 2004-12-16 2010-06-23 三井金属鉱業株式会社 フレキシブルプリント配線板
US7343570B2 (en) * 2005-11-02 2008-03-11 International Business Machines Corporation Methods, systems, and media to improve manufacturability of semiconductor devices
US8247846B2 (en) * 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
JP4866652B2 (ja) 2006-05-10 2012-02-01 ルネサスエレクトロニクス株式会社 半導体記憶装置
TW200818402A (en) * 2006-10-03 2008-04-16 Powerchip Semiconductor Corp Non-volatile memory, fabricating method and operating method thereof
US7691549B1 (en) * 2007-02-15 2010-04-06 Kla-Tencor Technologies Corporation Multiple exposure lithography technique and method
US20090127723A1 (en) 2007-11-21 2009-05-21 Zhang Fenghong AIM-Compatible Targets for Use with Methods of Inspecting and Optionally Reworking Summed Photolithography Patterns Resulting from Plurally-Overlaid Patterning Steps During Mass Production of Semiconductor Devices
EP2098293B1 (en) * 2008-02-22 2013-04-24 Qiagen Instruments AG Microtitre plate
US8043964B2 (en) 2009-05-20 2011-10-25 Micron Technology, Inc. Method for providing electrical connections to spaced conductive lines
FR2960657B1 (fr) 2010-06-01 2013-02-22 Commissariat Energie Atomique Procede de lithographie a dedoublement de pas
KR101692407B1 (ko) * 2010-08-19 2017-01-04 삼성전자주식회사 라인 패턴 구조물의 형성 방법
EP2562790A1 (de) 2011-08-26 2013-02-27 Espros Photonics AG Verfahren zur Herstellung von Halbleiterbauelementen auf einem Substrat sowie Substrat mit Halbleiterbaulelementen
JP2013061575A (ja) * 2011-09-14 2013-04-04 Toshiba Corp 配線レイアウトの設計方法、半導体装置及び配線レイアウトの設計を支援するプログラム
US8309462B1 (en) 2011-09-29 2012-11-13 Sandisk Technologies Inc. Double spacer quadruple patterning with self-connected hook-up
JP2013143398A (ja) 2012-01-06 2013-07-22 Toshiba Corp 半導体装置の製造方法
US8802510B2 (en) 2012-02-22 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for controlling line dimensions in spacer alignment double patterning semiconductor processing
US8637406B1 (en) 2012-07-19 2014-01-28 International Business Machines Corporation Image transfer process employing a hard mask layer
US9140976B2 (en) * 2012-09-14 2015-09-22 Macronix International Co., Ltd. Mask design with optically isolated via and proximity correction features
WO2014119230A1 (ja) * 2013-01-29 2014-08-07 シャープ株式会社 入力装置及びその製造方法、並びに電子情報機器
US9781842B2 (en) * 2013-08-05 2017-10-03 California Institute Of Technology Long-term packaging for the protection of implant electronics

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1881223A (zh) * 2005-04-06 2006-12-20 Lsi罗吉克公司 具有可重定位处理器硬核的集成电路
US20090114903A1 (en) * 2007-05-25 2009-05-07 Kalburge Amol M Integrated Nanotube and CMOS Devices For System-On-Chip (SoC) Applications and Method for Forming The Same
US20100159685A1 (en) * 2008-12-19 2010-06-24 Harry Chuang Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut
US20110037175A1 (en) * 2009-08-13 2011-02-17 International Business Machines Corporation Interconnection between sublithographic-pitched structures and lithographic-pitched structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107851613A (zh) * 2015-07-17 2018-03-27 高通股份有限公司 用于连接使用栅极切割分开的栅极区的器件和方法
CN107305862A (zh) * 2016-04-19 2017-10-31 台湾积体电路制造股份有限公司 集成电路制造方法
US11637064B2 (en) 2016-04-19 2023-04-25 Taiwan Semiconductor Manufacturing Company Limited Advanced metal connection with metal cut

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