CN106257641A - 用于制造高电阻率绝缘体上半导体衬底的方法 - Google Patents

用于制造高电阻率绝缘体上半导体衬底的方法 Download PDF

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CN106257641A
CN106257641A CN201610412569.8A CN201610412569A CN106257641A CN 106257641 A CN106257641 A CN 106257641A CN 201610412569 A CN201610412569 A CN 201610412569A CN 106257641 A CN106257641 A CN 106257641A
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high resistivity
semiconductor layer
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比什-因·阮
弗雷德里克·阿利伯特
克里斯托夫·马勒维尔
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Abstract

本发明涉及一种用于制造高电阻率绝缘体上半导体衬底的方法，该方法包括以下步骤：a)在高电阻率衬底1上方形成介电层2和半导体层3，使得介电层2被设置在高电阻率衬底1与半导体层3之间；b)在半导体层3上方形成硬掩膜或抗蚀剂4，其中，硬掩膜或抗蚀剂4在预定位置处具有至少一个开口5；c)通过硬掩膜或抗蚀剂4的所述至少一个开口5、半导体层3和介电层2经由杂质元素的离子注入在高电阻率衬底1中形成至少一个掺杂区域7；d)去除硬掩膜或抗蚀剂4；以及e)在半导体层3中和/或半导体层3上形成射频RF电路，该射频RF电路与高电阻率衬底1中的至少一个掺杂区域(7)至少部分交叠。

Description

用于制造高电阻率绝缘体上半导体衬底的方法
技术领域
本发明涉及一种用于制造高电阻率(HR)绝缘体上半导体(SOI)衬底的方法，涉及经由这种方法获得的高电阻率绝缘体上半导体衬底以及涉及半导体器件。
背景技术
复合半导体衬底可以通过组合两层或更多层来制造。一类这样设计的衬底是绝缘体上半导体衬底，其中，在载体衬底上形成顶部半导体层，介电层在顶部半导体层与载体衬底之间。对于顶部半导体层和载体衬底，通常使用硅并且介电层通常是氧化物层(典型地，二氧化硅)。
目前研究了尤其是所谓的高电阻率(HR)衬底，以便由于它们降低的衬底损耗和耦合而用于射频(RF)应用。
然而，已经发现在高电阻率衬底与薄介电层之间可以形成所谓的寄生导电层，这损害了RF性能，具体地，衬底损耗和耦合的期望效益。
已经提出了对于该问题的各种解决方案。例如，已经建议隐埋氧化物层之下的连续富陷阱层(trap-rich layer)(Kerr等人的“Identification of RF Harmonic Distortion on SiSubstrates and its Reduction Using a trap-rich Layer”，IEEE，2008)。然而，该单个富陷阱层具有连接到背栅形成工艺的负面影响。具体地，由于在背栅中较大的横向掺杂扩散和高界面陷阱密度，可能出现所获得的结构的可变性的问题并且从而可靠性的问题。
此外，根据US 8,492,868，已知一种形成集成电路结构的方法，其中，形成具有沟槽结构和离子杂质注入物的硅衬底层。然后，绝缘体层被设置在硅衬底层上并且与硅衬底层接触，其中，绝缘体层还填充沟槽结构。然后，电路层被设置在隐埋绝缘体层上并且与隐埋绝缘体层接触。离子杂质注入物允许避免上述寄生导电层。然而，因为该方法首先在衬底中形成沟槽，然后在衬底上形成隐埋氧化物层，所以隐埋氧化物层上的半导体层的后续形成可能是复杂的。此外，该教导不考虑例如数字电路的共同集成。
发明内容
因此，本发明的目的是提供一种用于制造高电阻率绝缘体上半导体衬底的改进方法、一种相应改进的高电阻率绝缘体上半导体衬底、以及一种包括这种高电阻率绝缘体上半导体衬底的改进的半导体器件。
利用根据权利要求1所述的方法、根据权利要求7所述的高电阻率绝缘体上半导体衬底和根据权利要求8所述的半导体器件来实现该目的。在从属权利要求中指定了优选实施方式。
通过使用硬掩膜或抗蚀剂通过半导体层和介电层进行局部注入，能够在高电阻率衬底中形成局部富陷阱区域。具体地，能够仅在RF电路下形成富陷阱区域。该富陷阱区域可以避免RF电路下的上述寄生导电层，使得不降低RF性能。可以设置电路的附加模拟或数字部分，然而，在该部分下不形成富陷阱区域。因为数字/模拟部分经常需要有效的反向偏压，所以这可以特别有益。为了实现这种有效的反向偏压，数字/模拟部分下方的富陷阱层将会具有缺点。
因此，本发明还提供了在RF电路下方的高电阻率绝缘体上半导体衬底中使用局部掺杂层，以避免在RF电路下方的区域中在高电阻率衬底与介电层之间形成寄生导电层，其中，通过硬掩膜或抗蚀剂的开口、通过半导体层以及通过介电层经由杂质元素的离子注入形成局部掺杂层。
附图说明
现在将结合所附附图描述有利的实施方式。
图1示出了根据本发明的方法的简化的流程图；
图2示出了根据本发明的制造方法的中间步骤；
图3示出了根据本发明的方法的另一个中间步骤；
图4示出了根据本发明的方法的进一步步骤；
图5示出了根据本发明的示例性半导体衬底；以及
图6示出了根据本发明的示例性半导体器件。
具体实施方式
现在将参照图1描述用于制造具体地具有RF电路的高电阻率绝缘体上半导体衬底的示例性方法。
首先，在步骤100中，在衬底上形成介电层和半导体层。衬底是高电阻率衬底。高电阻率衬底可以包括硅，尤其是多晶硅和/或单晶硅。高电阻率衬底的电阻率可以是1kΩ·cm或更高。
高电阻率衬底的至少一部分可以兼做背栅，尤其在被掺杂之后。具体地，高电阻率衬底的上部(即，高电阻率衬底面向半导体层的部分)可以兼做背栅，尤其在被掺杂之后。
为了形成背栅，例如，可以使用砷或硼作为掺杂物执行高电阻率衬底的掺杂。
半导体层还可以包括硅。介电层可以对应于隐埋氧化物(BOX)层，并且可以具体地包括硅氧化物(SiO2)。
用于上述层的其它材料也是可能的。例如，可以使用锗、硅锗(SiGe)或III-V化合物，具体地用于半导体层。高电阻率衬底不需要全部由半导体构成。具体地通过植入物或掺杂物能够仅形成具有从高电阻率切换到低电阻率的能力的材料的上部(即，面向半导体层的部分)。
BOX层可以是包括沉积低k电介质(如用于后段工艺(BEOL))或甚至高k电介质(例如，铪(IV)氧化物(HfO2))的任何绝缘材料。
可以使用任何已知的技术(例如，使用“智能切割”技术)在高电阻率衬底上形成介电层和半导体层。
在“智能切割”技术中，将介电层和/或半导体层从施主衬底转移到高电阻率衬底。在包括半导体层的半导体材料的施主衬底上形成介电层之后，形成施主衬底内的预定分离区域。该预定分离区域通过离子注入步骤形成，在该离子注入步骤期间，如氢或稀有气体离子(氦、氩等)的离子被注入到施主衬底中。预定分离区域的深度可以通过注入的离子的能量来确定。在将施主衬底附接到(具体地通过接合)高电阻率衬底(还称为处理衬底)之后，执行机械处理和/或热处理，使得半导体层连同隐埋介电层一起的分离发生在预定分离区域处，使得该两层被转移到高电阻率衬底上。
在介电层和半导体层被形成在高电阻率衬底上之后，在步骤200中硬掩膜或抗蚀剂被形成在半导体层上。
在步骤300中，可以在硬掩膜或抗蚀剂中在预定位置处形成至少一个开口。至少一个开口可以通过已知技术(诸如，光刻技术或通过蚀刻)来形成。可以形成至少一个开口，以指定或覆盖预定区域。具体地，至少一个开口可以是具有预定宽度和长度的矩形。
形成至少一个开口的预定位置可以具体地与形成包括有源器件和无源器件的RF电路的位置对应。至少一个开口的尺寸可以适应于RF电路的尺寸。
在处理半导体衬底的随后步骤，硬掩膜或抗蚀剂应当具体地覆盖半导体层的旨在包括模拟和/或数字电路的那些区域。
在步骤400中，通过硬掩膜或抗蚀剂的至少一个开口、通过半导体层、以及通过介电层执行杂质元素的离子注入，以在高电阻率衬底中形成至少一个掺杂区域。杂质元素可以具体地包括碳(C)、锗(Ge)、氧(O)、硅(Si)、氩(Ar)、钼(Mo)和/或氟(F)。更具体地，杂质元素可以包括满足以下条件中的一项或更多项的任意元素：
-在具有非常低扩散率的同时在硅中生成深能级(deep-level state)状态。
-具有无需电激活而使硅非晶化的能力。
-具有将硅转换成(半)绝缘材料的能力。
必须根据介电层和半导体层的厚度以及杂质元素来选择掺杂能量。类似地，剂量取决于工作条件并且可以大于1x1011cm-2或大于1x1013cm-2。
高电阻率衬底中的至少一个掺杂区域由此可以具体与设置在预定位置处的富陷阱区域对应。掺杂区域的横向延伸与至少一个开口的区域对应。换言之，至少一个掺杂区域位于具有预定尺寸的预定位置处，具体地如由至少一个开口的尺寸限定的区域以及具体地取决于在离子注入步骤期间使用的能量和剂量的深度。
当从顶部观看半导体衬底时，可以具体地由两个坐标来指定预定位置。开口的预定位置然后可以与开口的角中的一个的坐标或开口的中心的坐标对应。
图2示出了在制造方法期间获得高电阻率绝缘体上半导体衬底的示例性中间步骤。所示出的高电阻率绝缘体上半导体衬底包括以该顺序排列的高电阻率衬底1、隐埋氧化物层2和半导体层3。此外，硬掩膜或抗蚀剂4被形成在半导体层3上，半导体层3在预定位置处(即，在预定的X和Y坐标处)包括开口5。开口5具有预定几何形状和尺寸。
图3示出了后续制造步骤，其中，通过开口5、半导体层3和隐埋氧化物层2执行利用杂质元素6的离子注入，以在衬底1中形成掺杂区域7。掺杂区域7被形成在预定位置处，换言之，在与硬掩膜或抗蚀剂4中的开口5相同的X和Y坐标处。掺杂区域7具有与开口5相同的几何形状和(横向)尺寸。以这种方式，由此，形成局部富陷阱区域。
可以具体地以指定顺序执行如权利要求1中指定并在图1中所示的方法步骤。该时间顺序允许注入的区域和后续形成的RF电路有效的对准。可以以这种方式实现甚至自对准。此外，可以以这种方式形成通用绝缘体上半导体衬底，可以根据所选掩膜或抗蚀剂对该衬底进行图案化，而不是在器件集成顺序期间实现绝缘体上半导体制造。这提高了灵活性和成本效率。
图4示出了可以在图1的步骤400之后执行的进一步步骤。具体地，在步骤500中，可以去除硬掩膜或抗蚀剂。可以通过已知技术(诸如，蚀刻)来执行该去除。
在步骤600中，射频(RF)电路(具体包括有源器件和/或无源器件)可以被形成在预定位置处，换言之，在掺杂区域7上。当从上方(从设置RF电路的一侧)看时，RF电路由此与掺杂区域7至少部分交叠。RF电路可以具体地与掺杂区域7完全交叠。换言之，RF电路可以在垂直方向上与掺杂区域7对准。
可以不与掺杂区域7交叠形成模拟电路和/或数字电路。由此，上述方法允许射频电路和模拟和/或数字电路的共同集成。因为掺杂区域不形成在模拟和/或数字电路之下，所以有效的反向偏压是可能的。
如这里所使用的，有源器件是可以被接通和断开的器件。例如，有源器件可以包括或对应于晶体管。无源器件可以包括或对应于传输线、电感或电阻器。
在图5中，示出了如上所述的方法期间作为中间产品而获得的高电阻率绝缘体上半导体衬底。该高电阻率绝缘体上半导体衬底包括高电阻率衬底1、高电阻率衬底1上方的介电层2以及介电层2上方的半导体层3。在高电阻率衬底中在预定位置处形成掺杂区域7。掺杂区域具体包括碳(C)、锗(Ge)、氧(O)和/或氟(F)，特别地，并入到高电阻率衬底1的多晶硅或单晶硅中。
图6示出了包括如图5所示的半导体衬底的半导体器件。另外，RF电路8被形成在掺杂区域7上方的半导体层3中和/或半导体层3上(即，与掺杂区域7至少部分交叠)。此外，类似地在半导体层3中和/或半导体层3上在高电阻率衬底1中没有掺杂区域被设置在下方的区域中或位置处形成模拟电路或数字电路9。
虽然已经单独描述了之前讨论的本发明的实施方式和示例，但将理解的是，上述特征中的一些或所有还可以以不同方式组合。所讨论的实施方式不旨在限制，而是用作示出本发明的特征和优点的示例。

Claims (9)

1.一种用于制造高电阻率绝缘体上半导体衬底的方法，该方法包括以下步骤：
a)在高电阻率衬底(1)上方形成介电层(2)和半导体层(3)，使得所述介电层(2)被设置在所述高电阻率衬底(1)与所述半导体层(3)之间；
b)在所述半导体层(3)上方形成硬掩膜或抗蚀剂(4)，其中，所述硬掩膜或抗蚀剂(4)在预定位置处具有至少一个开口(5)；
c)通过所述硬掩膜或抗蚀剂(4)的所述至少一个开口(5)、所述半导体层(3)和所述介电层(2)经由杂质元素的离子注入在所述高电阻率衬底(1)中形成至少一个掺杂区域(7)；
d)去除所述硬掩膜或抗蚀剂(4)；以及
e)在所述半导体层(3)中和/或所述半导体层(3)上形成射频RF电路，所述射频RF电路与所述高电阻率衬底(1)中的所述至少一个掺杂区域(7)至少部分交叠。
2.根据权利要求1所述的方法，其中，经由步骤d)中的离子注入而注入的所述杂质元素包括C、Ge、O、Si、Ar、Mo和/或F。
3.根据权要求1或2所述的方法，其中，所述高电阻率衬底(1)包括硅，特别地，多晶硅和/或单晶硅。
4.根据前述权利要求中的一项所述的方法，其中，所述介电层(2)是隐埋氧化物BOX层。
5.根据前述权利要求中的一项所述的方法，其中，所述半导体层(3)包括硅。
6.根据前述权利要求中的一项所述的方法，该方法还包括以下步骤f)：在所述半导体层(3)中和/或所述半导体层(3)上在不与所述高电阻率衬底(1)中的所述掺杂区域(7)交叠的区域中形成模拟电路和/或数字电路。
7.一种由根据前述权利要求中的一项的方法获得的高电阻率绝缘体上半导体衬底。
8.一种半导体器件，该半导体器件包括：
高电阻率衬底(1)；
介电层(2)，其在所述高电阻率衬底(1)上方；以及
半导体层(3)，其在所述介电层(2)上方；
其中，所述半导体层(3)包括射频RF电路以及数字电路和/或模拟电路；
其中，所述高电阻率衬底(1)包括与所述射频RF电路至少部分交叠的至少一个掺杂区域(7)；并且
其中，在所述半导体层(3)中和/或所述半导体层(3)上在不与所述高电阻率衬底(1)中的所述至少一个掺杂区域(7)交叠的区域中设置所述数字电路和/或所述模拟电路。
9.根据权利要求8所述的半导体器件，其中，所述掺杂区域包括C、Ge、O和/或F。
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