WO2023159077A1 - Methods for generation of a trap-rich layer in a soi substrate - Google Patents

Methods for generation of a trap-rich layer in a soi substrate Download PDF

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Publication number
WO2023159077A1
WO2023159077A1 PCT/US2023/062674 US2023062674W WO2023159077A1 WO 2023159077 A1 WO2023159077 A1 WO 2023159077A1 US 2023062674 W US2023062674 W US 2023062674W WO 2023159077 A1 WO2023159077 A1 WO 2023159077A1
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layer
substrate
silicon
region
trap
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PCT/US2023/062674
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French (fr)
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Sebastien Kouassi
Sinan Goktepeli
Simon Edward Willard
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Psemi Corporation
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Publication of WO2023159077A1 publication Critical patent/WO2023159077A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H01L21/26553—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Definitions

  • the present disclosure is related to semiconductor technology, and more particularly to generation of a trap-rich layer in a silicon-on-insulator (SOI) substrate via implantation.
  • SOI silicon-on-insulator
  • FIG. 1A shows an SOI substrate (100A) that includes a thin layer of silicon (Si, 110, also referred to as SOI layer) overlying an insulating BOX layer (120, e.g., SiO2).
  • Si silicon
  • BOX layer e.g., SiO2
  • performance of RF devices e.g., transistors
  • PSC parasitic surface conduction
  • PSC may be due to fixed positive charges within the BOX layer (120) near the interface with the bulk substrate (150) attracting free carriers and thereby reducing effective resistivity of the bulk substrate (150) and resulting in increased loss and nonlinearity.
  • Provision of a trap-rich layer (130) between the BOX layer and the bulk substrate (150) as shown in the SOI substrate (100B) of FIG. IB may reduce the PSC effect and therefore increase performance of the RF devices.
  • presence of the trap-rich layer (130) may produce a traprich effect that includes trapping of free charges (e.g., electrons, carriers) underneath the BOX layer (120), thereby preventing flow of current that may produce undesired coupling of signals to/between the RF devices formed in the thin layer of silicon (110).
  • teachings according to the present disclosure describe methods for generation of the trap-rich layer (130) in a prefabricated SOI substrate.
  • a method for generation of a trap-rich (TR) functionality in a silicon-on-insulator (SOI) substrate comprising: providing a SOI substrate comprising, in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate; implanting a species into the silicon substrate; based on the implanting, producing an implantation concentration profile in a target region of the base silicon substrate immediately below the BOX layer; and based on the producing, generating a damaged region in the target region, the damaged region providing the trap-rich functionality.
  • a silicon-on-insulator (SOI) substrate comprising: in sequence, athin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate, wherein the SOI substrate further comprises: a damaged region immediately below the BOX layer that provides a trap-rich functionality based on implanted species that include any one of carbon, germanium, fluorine, xenon, or neon.
  • SOI silicon-on-insulator
  • FIG. 1A shows a silicon-on-insulator (SOI) substrate.
  • FIG. IB shows a silicon-on-insulator (SOI) substrate comprising a trap-rich layer.
  • FIG. 2 shows figures representative of process steps according to an embodiment of the present disclosure for generation of a trap-rich layer in the SOI substrate of FIG. 1 A.
  • FIG. 3A shows a SOI substrate comprising a region with a trap-rich functionality and a region without the trap-rich functionality.
  • FIG. 3B shows figures representative of process steps according to an embodiment of the present disclosure for generation of the SOI substrate of FIG. 3A.
  • FIG. 4 is a process chart showing various steps of a method according to the present disclosure for generation of a trap-rich functionality in a SOI substrate.
  • teachings according to the present disclosure allow forming of the substrate ( 100B) of FIG. IB from a prefabricated SOI substrate/wafer, such as the SOI substrate (100A) of FIG. 1A.
  • the BOX layer (120) and the traprich layer (130) are formed not by physically adding such layers atop a bulk silicon substrate (e.g., 150) in a sequential manner, but rather by a process that includes implantation of species (e.g., carbon, germanium, fluorine, xenon, neon) penetrating a layered (crystalline) structure of a prefabricated SOI substrate (e.g., 100A of FIG.
  • the trap-rich functionality in (localized) targeted regions of a substrate that may include RF devices and not as a global “blanket” layer (e.g., 130 of FIG. IB) formed in the substrate.
  • a substrate may include RF devices and not as a global “blanket” layer (e.g., 130 of FIG. IB) formed in the substrate.
  • teachings according to the present disclosure allow forming of such targeted regions starting from a prefabricated SOI substrate. Accordingly, in an exemplary embodiment of the present disclosure, such targeted regions may be formed during a device fabrication process (e.g., CMOS fabrication) and therefore after acquisition of the SOI substrate (e.g., 100A) of FIG. 1A).
  • a high-resistivity silicon (HR-Si) substrate is a silicon substrate with a resistivity of 200 Ohm cm or higher.
  • FIG. 2 shows figures representative of process steps (e.g., a and b) according to an embodiment of the present disclosure for generation of the trap-rich layer (130) in a (prefabricated) SOI substrate (110, 120, 150) comprising a BOX layer (120) arranged between the bulk/base Si substrate (150) and a thin silicon layer (110).
  • process steps may be used to generate, under and adj acent to the BOX layer ( 120) having a thickness in a range from about few 10 ’ s of nm (e .g .
  • the process starts (denoted as process step a) with implantation of species (e.g., ions of C, Ge, F, Xe or Ne) into a top surface of the SOI substrate (110, 120, 150).
  • species e.g., ions of C, Ge, F, Xe or Ne
  • the top surface of the SOI substrate (e.g., top/extemal surface of the layer 110) may be (optionally) protected against impact energy of the implants with a sacrificial layer (115, e.g., oxide layer) according to methods that are well-known in the art.
  • a sacrificial layer 115, e.g., oxide layer
  • the species implantation forms a damaged region (e.g., 130) which includes species atoms that may have damaged a portion of the crystalline structure of the base substrate (150) immediately underneath the BOX layer (120), e.g., by displacing Si atoms from their crystalline positions.
  • the species used for implantation may include any one of C (carbon), Ge (germanium), F (fluorine), Xe (xenon) or Ne (neon).
  • the energy and dosage of species used for implantation can be tuned in order to limit the damage to the silicon layer (110) and create a sufficiently damaged layer, or an amorphous layer, in the silicon immediately below the BOX layer (120).
  • a sufficiently damaged layer may contain a trap density of about le8 at.cm-2 or higher.
  • electrically active species such as boron, arsenic, phosphorus, or indium may not be suitable species for implantation. Examples ranges of implantation energy and dosage of species are given in Table 1 below.
  • the process parameters forthe implantation ofthe species may be further selected (e.g., via multiple/sequential species implantations at different energy and/or dose) such that the concentration of the implanted species may be according to a desired profile.
  • teachings according to the present disclosure may not be limited to a single implantation cycle, rather multiple sequential implantation cycles using same or different species may be used to obtain a desired (final) implantation concentration profile (e.g., depth profile) for generation of the damaged region (e.g., 130).
  • the term “damaged”, as used for example in the expressions “damaged region” or “damaged layer”, may refer to a region or a layer of a silicon substrate (e.g., 150 of FIG. 2) that includes defects imparted specifically to (locally) damage the crystalline structure of the silicon and trap free carriers. Such damage may extend from a partial damage wherein some of the crystalline structure is maintained outside the defects, to a full damage that is substantially devoid of a crystalline structure, and which may therefore be referred to an amorphous (damaged) structure.
  • the defects imparted may include implanted or diffused atoms of an implanted species, and/or random bonding of such atoms with silicon.
  • the sacrificial layer (115) may be removed via a corresponding process step (e.g., denoted as step b) such as to obtain the SOI substrate with trap-rich layer (130) shown in the bottom right comer of FIG. 2. Removal of the sacrificial layer (115) may include any known in the art etching process for selective removal of a material (e.g., used in the layer 115).
  • teachings according to the present disclosure may be used to generate selected/targeted (damaged) regions with trap-rich functionality.
  • the trap-rich functionality according to the present disclosure may not necessarily be provided within a global layer (e.g., 130 of FIG. 1) that covers an entire cross section of the SOI substrate (and therefore comprising a contiguous region laterally extending through an entire bottom surface of the BOX layer). Rather, as shown in FIG.
  • the present teachings may equally be used to generate (non-contiguous, separate, non-overlapping) regions with trap-rich functionality (e.g., regions R1 and R3) and regions without trap-rich functionality (e.g., region R2) that are electrically isolated from one another.
  • regions with trap-rich functionality e.g., regions R1 and R3
  • regions without trap-rich functionality e.g., region R2
  • the SOI substrate shown in FIG. 3A can optimize performance of devices fabricated in the thin silicon layer (110) according to their expected functionalities (e.g., functionality as RF or lower frequencies devices, including DC).
  • RF devices may be fabricated in regions (e.g., R1 or R3) that include trap-rich functionality (e.g., via corresponding regions 130), and non-RF devices may be fabricated in regions (e.g., R2) that do not include trap-rich functionality.
  • regions selected/targeted to include the trap-rich functionality may be generated/realized/fabricated on the fly during the (e.g., CMOS device) fabrication process and after (locations/arrangement of) the devices/circuits are mapped onto the substrate (e.g., surface of the layer 110).
  • the different regions may be separated, or laterally (electrically) isolated within the thin silicon layer (110), via shallow trench isolation (STI) regions (360) as known in the art.
  • STI shallow trench isolation
  • trap-rich functionality in the regions R1 and R3 may be provided throughout the regions, or in other words, for each of the regions R1 an R2, an entirety of a bottom surface of a corresponding region of the BOX layer (120, regions delimited by STI) is in contact with a corresponding trap-rich region/layer (130). Accordingly, any (RF) device fabricated in a corresponding region of the thin silicon layer (110) may be protected against the PSC effect.
  • FIG. 3B shows figures representative of process steps (e.g., a, b, and c) according to an embodiment of the present disclosure for generation of the SOI substrate of FIG. 3 A.
  • a pattern of isolation trenches (360’, corresponding to locations of the regions Rl, R2 and R3) is etched into the substrate (110, 120, 150), each trench (360’) fully penetrating the layer (110) and fully or partially penetrating the layer (120).
  • formation of the pattern of trenches (360’) may include provision of (sacrificial) layers (115a, e.g., oxide) and (115b, e.g., nitride) for creation of a hard mask that may further include provision of a layer of photoresist (not shown in the figures).
  • sacrificial layers 115a, e.g., oxide
  • 115b e.g., nitride
  • the pattern of trenches (360’) may be filled with an insulating material, such as, for example, oxide, and etched/polished (e.g., for removal of layers 115a/b and/or other residues) using a known in the art processes, such as, for example, chemical vapor deposition (CVD) and/or chemical mechanical polishing (CMP), to obtain the STI regions (360) that separate the regions Rl, R2 and R3.
  • an insulating material such as, for example, oxide
  • etched/polished e.g., for removal of layers 115a/b and/or other residues
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing
  • a mask e.g., photoresist or silicon nitride, SiN
  • a mask e.g., photoresist or silicon nitride, SiN
  • openings provided by the mask (370) may project onto regions of the base substrate (150) that are targeted to include damaged regions (e.g., 130 of regions Rl and R3 shown in FIG. 3A), whereas obstmctions (closed areas) provided by the mask (370) may project onto regions of the base substrate (150) devoid of damaged regions (e.g., region R2 of FIG. 3A).
  • outer edges of the opening (or of the obstmctions) provided by the pattern of the mask (370) coincide with STI regions (360).
  • such opening extends above an entirety of a corresponding region of the layer (110) as well as portions of the STI regions (360) that delimit the region R1.
  • each portion of the thin silicon layer (110) included in regions R1 and R3, includes a trap-rich functionality via a corresponding damaged region immediately below a corresponding BOX layer (120) region.
  • a projection of each portion of the thin silicon layer (110) included in regions R1 and R3 onto a plane of the base silicon substrate (150) immediately below the BOX layer (120) is fully encompassed in a corresponding damaged region (130).
  • Energy and dosage for the implantation of the species for each of the target regions may be similar to that described above with reference to FIG. 2.
  • the mask (370) may be removed/etched away to obtain the substrate (110, 120, 130, 150) shown in FIG. 3A.
  • Table 1 summarizing process steps according to the present teachings and in contrast to a prior art process steps used for forming an SOI substrate that does not include a trap-rich layer.
  • FIG. 4 is a process chart (400) showing various steps of a method according to the present disclosure for generation of a trap-rich functionality in a silicon-on-insulator (SOI) substrate.
  • steps comprise: providing a SOI substrate comprising, in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate, per step (410); implanting a species into the silicon substrate, per step (420); based on the implanting, producing an implantation concentration profile in a target region of the base silicon substrate immediately below the BOX layer, per step (430); and based on the producing, generating a damaged region in the target region, the damaged region providing the trap-rich functionality, per step (440).
  • SOI substrate comprising, in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate, per step (410); implanting a species into the silicon substrate, per step (420); based on the implanting, producing an implantation concentration profile in a target region of the base silicon substrate
  • MOSFET includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure.
  • FET field effect transistor
  • metal-like include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
  • radio frequency refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems.
  • An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
  • Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice.
  • Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms.
  • IC integrated circuit
  • Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS).
  • embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies.
  • embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz).
  • Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
  • Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices).
  • Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents.
  • Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
  • Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices.
  • Embodiments of the present invention may be fabricated as integrated circuits (Ics), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance.
  • Ics integrated circuits
  • IC embodiments of this invention are often used in modules in which one or more of such Ics are combined with other circuit blocks (e.g. , filters, amplifiers, passive components, and possibly additional Ics) into one package.
  • the Ics and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher- level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc.
  • an end product such as a cellular telephone, laptop computer, or electronic tablet
  • a higher- level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc.
  • modules and assemblies such Ics typically enable a mode of communication, often wireless communication.

Abstract

Methods for generation of a trap-rich layer or region in a silicon-on-insulator (SOI) substrate are presented. According to one aspect, species penetrate a layered crystalline structure of the SOI substrate is implanted in the SOI substrate such as to form a concentration profile of atoms of the species having a peak at a target depth of the trap-rich layer or region. According to another aspect, the concentration profile forms a damaged layer or region immediately below the BOX layer, the damaged layer or region having a functionality of a trap-rich layer or region. According to another aspect, a mask is used to direct the implantation only to targeted regions immediately below the BOX layer that are used for fabrication of RF devices.

Description

Methods for Generation of a Trap-Rich Layer in a SOI Substrate
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to and the benefit of co-pending US provisional patent application Serial No. 63/312,193 entitled “Methods for Generation of a Trap-Rich Layer in a SOI Substrate”, filed on February 21, 2022, the disclosure of which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
[0002] The present disclosure is related to semiconductor technology, and more particularly to generation of a trap-rich layer in a silicon-on-insulator (SOI) substrate via implantation.
BACKGROUND
[0003] FIG. 1A shows an SOI substrate (100A) that includes a thin layer of silicon (Si, 110, also referred to as SOI layer) overlying an insulating BOX layer (120, e.g., SiO2). In some cases, performance of RF devices (e.g., transistors) formed in the thin layer of silicon (110) may be affected by the well-known in the art parasitic surface conduction (PSC) effect at the interface between the BOX layer (120) and the bulk substrate (150) that is due to the capacitorlike configuration a SOI stack creates. As known to a person skilled in the art, PSC may be due to fixed positive charges within the BOX layer (120) near the interface with the bulk substrate (150) attracting free carriers and thereby reducing effective resistivity of the bulk substrate (150) and resulting in increased loss and nonlinearity. Provision of a trap-rich layer (130) between the BOX layer and the bulk substrate (150) as shown in the SOI substrate (100B) of FIG. IB may reduce the PSC effect and therefore increase performance of the RF devices. As known to a person skilled in the art, presence of the trap-rich layer (130) may produce a traprich effect that includes trapping of free charges (e.g., electrons, carriers) underneath the BOX layer (120), thereby preventing flow of current that may produce undesired coupling of signals to/between the RF devices formed in the thin layer of silicon (110). Teachings according to the present disclosure describe methods for generation of the trap-rich layer (130) in a prefabricated SOI substrate. SUMMARY
[0004] According to a first aspect of the present disclosure, a method for generation of a trap-rich (TR) functionality in a silicon-on-insulator (SOI) substrate is presented, the method comprising: providing a SOI substrate comprising, in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate; implanting a species into the silicon substrate; based on the implanting, producing an implantation concentration profile in a target region of the base silicon substrate immediately below the BOX layer; and based on the producing, generating a damaged region in the target region, the damaged region providing the trap-rich functionality.
[0005] According to a second aspect of the present disclosure, a silicon-on-insulator (SOI) substrate is presented, comprising: in sequence, athin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate, wherein the SOI substrate further comprises: a damaged region immediately below the BOX layer that provides a trap-rich functionality based on implanted species that include any one of carbon, germanium, fluorine, xenon, or neon.
[0006] Further aspects of the disclosure are provided in the description, drawings and claims of the present application.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
[0008] FIG. 1A shows a silicon-on-insulator (SOI) substrate.
[0009] FIG. IB shows a silicon-on-insulator (SOI) substrate comprising a trap-rich layer.
[0010] FIG. 2 shows figures representative of process steps according to an embodiment of the present disclosure for generation of a trap-rich layer in the SOI substrate of FIG. 1 A.
[0011] FIG. 3A shows a SOI substrate comprising a region with a trap-rich functionality and a region without the trap-rich functionality.
[0012] FIG. 3B shows figures representative of process steps according to an embodiment of the present disclosure for generation of the SOI substrate of FIG. 3A.
[0013] FIG. 4 is a process chart showing various steps of a method according to the present disclosure for generation of a trap-rich functionality in a SOI substrate.
[0014] Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
[0015] Teachings according to the present disclosure allow forming of the substrate ( 100B) of FIG. IB from a prefabricated SOI substrate/wafer, such as the SOI substrate (100A) of FIG. 1A. In other words, in contrast to some prior art processes, the BOX layer (120) and the traprich layer (130) are formed not by physically adding such layers atop a bulk silicon substrate (e.g., 150) in a sequential manner, but rather by a process that includes implantation of species (e.g., carbon, germanium, fluorine, xenon, neon) penetrating a layered (crystalline) structure of a prefabricated SOI substrate (e.g., 100A of FIG. 1A), thereby forming a damaged region under, and adjacent to, the BOX layer (120) with trap-rich functionality (e.g., trapping free carriers attracted to positively charged Si/SiOa interface provided by the bulk substrate 150 and the BOX layer 120, thereby limiting/preventing the PSC effect).
[0016] In some applications it may be advantageous to include the trap-rich functionality in (localized) targeted regions of a substrate that may include RF devices and not as a global “blanket” layer (e.g., 130 of FIG. IB) formed in the substrate. As described later with reference to, for example, FIGs. 3A-3B, teachings according to the present disclosure allow forming of such targeted regions starting from a prefabricated SOI substrate. Accordingly, in an exemplary embodiment of the present disclosure, such targeted regions may be formed during a device fabrication process (e.g., CMOS fabrication) and therefore after acquisition of the SOI substrate (e.g., 100A) of FIG. 1A).
[0017] Teachings according to the present disclosure may equally apply to regular (bulk) silicon substrates and to high-resistivity silicon (HR-Si) substrates (e.g., 150 of FIG. 1A- IB). It should be noted that in some RF applications, use of HR-Si substrate may be preferred for an increase RF performance of devices (e.g., transistors) formed on the substrate. Generation of the trap-rich layer (130) based on the methods according to present teachings can substantially reduce cost of the produced SOI substrate and therefore allow for a simpler and cheaper solution to parasitic-surface-conduction suppression in RF SOI and reduced loss and improved linearity as a consequence. As used herein, a high-resistivity silicon (HR-Si) substrate is a silicon substrate with a resistivity of 200 Ohm cm or higher.
[0018] FIG. 2 shows figures representative of process steps (e.g., a and b) according to an embodiment of the present disclosure for generation of the trap-rich layer (130) in a (prefabricated) SOI substrate (110, 120, 150) comprising a BOX layer (120) arranged between the bulk/base Si substrate (150) and a thin silicon layer (110). According to an exemplary embodiment of the present disclosure, such process steps may be used to generate, under and adj acent to the BOX layer ( 120) having a thickness in a range from about few 10 ’ s of nm (e .g . , 20 nm) to about few 100’s of nm (e.g., 500 nm), the trap-rich layer (130) having a thickness in a range from about few 10’s of nm (e.g., 20 nm) to about few microns (e.g., 2-3 pm). As shown in the top left comer of FIG. 2, the process starts (denoted as process step a) with implantation of species (e.g., ions of C, Ge, F, Xe or Ne) into a top surface of the SOI substrate (110, 120, 150). In some embodiments, as shown in the top left comer of FIG. 2, the top surface of the SOI substrate (e.g., top/extemal surface of the layer 110) may be (optionally) protected against impact energy of the implants with a sacrificial layer (115, e.g., oxide layer) according to methods that are well-known in the art. As shown in the top right comer of FIG. 2, the species implantation forms a damaged region (e.g., 130) which includes species atoms that may have damaged a portion of the crystalline structure of the base substrate (150) immediately underneath the BOX layer (120), e.g., by displacing Si atoms from their crystalline positions.
[0019] According to an embodiment of the present disclosure, the species used for implantation may include any one of C (carbon), Ge (germanium), F (fluorine), Xe (xenon) or Ne (neon). The energy and dosage of species used for implantation can be tuned in order to limit the damage to the silicon layer (110) and create a sufficiently damaged layer, or an amorphous layer, in the silicon immediately below the BOX layer (120). A sufficiently damaged layer may contain a trap density of about le8 at.cm-2 or higher. In those embodiments where it may be preferable to keep the resistance of the substrate sufficiently high, electrically active species such as boron, arsenic, phosphorus, or indium may not be suitable species for implantation. Examples ranges of implantation energy and dosage of species are given in Table 1 below.
[0020] According to another embodiment of the present disclosure, the process parameters forthe implantation ofthe species may be further selected (e.g., via multiple/sequential species implantations at different energy and/or dose) such that the concentration of the implanted species may be according to a desired profile. In other words, teachings according to the present disclosure may not be limited to a single implantation cycle, rather multiple sequential implantation cycles using same or different species may be used to obtain a desired (final) implantation concentration profile (e.g., depth profile) for generation of the damaged region (e.g., 130). [0021] As used herein, the term “damaged”, as used for example in the expressions “damaged region” or “damaged layer”, may refer to a region or a layer of a silicon substrate (e.g., 150 of FIG. 2) that includes defects imparted specifically to (locally) damage the crystalline structure of the silicon and trap free carriers. Such damage may extend from a partial damage wherein some of the crystalline structure is maintained outside the defects, to a full damage that is substantially devoid of a crystalline structure, and which may therefore be referred to an amorphous (damaged) structure. The defects imparted may include implanted or diffused atoms of an implanted species, and/or random bonding of such atoms with silicon.
[0022] With continued reference to FIG. 2, once the damaged layer (130) with trap-rich functionality is generated, the sacrificial layer (115) may be removed via a corresponding process step (e.g., denoted as step b) such as to obtain the SOI substrate with trap-rich layer (130) shown in the bottom right comer of FIG. 2. Removal of the sacrificial layer (115) may include any known in the art etching process for selective removal of a material (e.g., used in the layer 115).
[0023] Teachings according to the present disclosure, including process steps described above with reference to FIG. 2, may be used to generate selected/targeted (damaged) regions with trap-rich functionality. In other words, the trap-rich functionality according to the present disclosure may not necessarily be provided within a global layer (e.g., 130 of FIG. 1) that covers an entire cross section of the SOI substrate (and therefore comprising a contiguous region laterally extending through an entire bottom surface of the BOX layer). Rather, as shown in FIG. 3A, the present teachings may equally be used to generate (non-contiguous, separate, non-overlapping) regions with trap-rich functionality (e.g., regions R1 and R3) and regions without trap-rich functionality (e.g., region R2) that are electrically isolated from one another.
[0024] With reference to FIG. 3A, the SOI substrate shown in FIG. 3A can optimize performance of devices fabricated in the thin silicon layer (110) according to their expected functionalities (e.g., functionality as RF or lower frequencies devices, including DC). For example, RF devices may be fabricated in regions (e.g., R1 or R3) that include trap-rich functionality (e.g., via corresponding regions 130), and non-RF devices may be fabricated in regions (e.g., R2) that do not include trap-rich functionality. Furthermore, regions selected/targeted to include the trap-rich functionality may be generated/realized/fabricated on the fly during the (e.g., CMOS device) fabrication process and after (locations/arrangement of) the devices/circuits are mapped onto the substrate (e.g., surface of the layer 110). As shown in FIG. 3A, the different regions may be separated, or laterally (electrically) isolated within the thin silicon layer (110), via shallow trench isolation (STI) regions (360) as known in the art. Furthermore, as shown in FIG. 3A, trap-rich functionality in the regions R1 and R3 may be provided throughout the regions, or in other words, for each of the regions R1 an R2, an entirety of a bottom surface of a corresponding region of the BOX layer (120, regions delimited by STI) is in contact with a corresponding trap-rich region/layer (130). Accordingly, any (RF) device fabricated in a corresponding region of the thin silicon layer (110) may be protected against the PSC effect.
[0025] FIG. 3B shows figures representative of process steps (e.g., a, b, and c) according to an embodiment of the present disclosure for generation of the SOI substrate of FIG. 3 A. As shown in the top left comer of FIG. 3B, during a first process step (denoted as step a) a pattern of isolation trenches (360’, corresponding to locations of the regions Rl, R2 and R3) is etched into the substrate (110, 120, 150), each trench (360’) fully penetrating the layer (110) and fully or partially penetrating the layer (120). As shown in FIG. 3B, formation of the pattern of trenches (360’) may include provision of (sacrificial) layers (115a, e.g., oxide) and (115b, e.g., nitride) for creation of a hard mask that may further include provision of a layer of photoresist (not shown in the figures).
[0026] As shown in the top right comer of FIG. 3B, the pattern of trenches (360’) may be filled with an insulating material, such as, for example, oxide, and etched/polished (e.g., for removal of layers 115a/b and/or other residues) using a known in the art processes, such as, for example, chemical vapor deposition (CVD) and/or chemical mechanical polishing (CMP), to obtain the STI regions (360) that separate the regions Rl, R2 and R3.
[0027] Next, as shown in the bottom right comer (step b) of FIG. 3B, a mask (370, e.g., photoresist or silicon nitride, SiN) is laid over the surface of the substrate (110, 120, 150) having a pattern that corresponds to the locations of the regions Rl, R2 and R3. For example, openings provided by the mask (370) may project onto regions of the base substrate (150) that are targeted to include damaged regions (e.g., 130 of regions Rl and R3 shown in FIG. 3A), whereas obstmctions (closed areas) provided by the mask (370) may project onto regions of the base substrate (150) devoid of damaged regions (e.g., region R2 of FIG. 3A). Accordingly, and as shown in FIG. 3B, outer edges of the opening (or of the obstmctions) provided by the pattern of the mask (370) coincide with STI regions (360). For example, considering the opening of the mask (370) in the region Rl, as shown in FIG. 3B such opening extends above an entirety of a corresponding region of the layer (110) as well as portions of the STI regions (360) that delimit the region R1.
[0028] Next, as shown in the bottom right comer (step c) of FIG. 3B, species are implanted into the substrate (110, 120, 150) through the mask (370) to generate the damaged regions (130) for the regions R1 and R3. Accordingly, each portion of the thin silicon layer (110) included in regions R1 and R3, includes a trap-rich functionality via a corresponding damaged region immediately below a corresponding BOX layer (120) region. In other words, a projection of each portion of the thin silicon layer (110) included in regions R1 and R3 onto a plane of the base silicon substrate (150) immediately below the BOX layer (120) is fully encompassed in a corresponding damaged region (130). Energy and dosage for the implantation of the species for each of the target regions (e.g., immediately below BOX layer in regions R1 and R3) may be similar to that described above with reference to FIG. 2. Although not shown in FIG. 3B, the mask (370) may be removed/etched away to obtain the substrate (110, 120, 130, 150) shown in FIG. 3A.
[0029] Below is a table (Table 1) summarizing process steps according to the present teachings and in contrast to a prior art process steps used for forming an SOI substrate that does not include a trap-rich layer.
[0030] Table 1:
Figure imgf000010_0001
[0031] FIG. 4 is a process chart (400) showing various steps of a method according to the present disclosure for generation of a trap-rich functionality in a silicon-on-insulator (SOI) substrate. As shown in FIG. 4 such steps comprise: providing a SOI substrate comprising, in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate, per step (410); implanting a species into the silicon substrate, per step (420); based on the implanting, producing an implantation concentration profile in a target region of the base silicon substrate immediately below the BOX layer, per step (430); and based on the producing, generating a damaged region in the target region, the damaged region providing the trap-rich functionality, per step (440).
[0032] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal -like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
[0033] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
[0034] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
[0035] Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
[0036] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (Ics), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such Ics are combined with other circuit blocks (e.g. , filters, amplifiers, passive components, and possibly additional Ics) into one package. The Ics and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher- level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such Ics typically enable a mode of communication, often wireless communication.
[0037] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.
[0038] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

1. A method for generation of a trap-rich (TR) functionality in a silicon-on-insulator (SOI) substrate, the method comprising: providing a SOI substrate comprising, in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate; implanting a species into the silicon substrate; based on the implanting, producing an implantation concentration profde in a target region of the base silicon substrate immediately below the BOX layer; and based on the producing, generating a damaged region in the target region, the damaged region providing the trap-rich functionality.
2. The method according to claim 1, wherein: the target region is a contiguous region that extends through an entire surface of the BOX layer.
3. The method according to claim 1, wherein: the silicon substrate is a high resistivity silicon substrate.
4. The method according to claim 3, wherein: the high resistivity is provided by a resistivity of the silicon substrate that is equal to or higher than 200 Ohm cm.
5. The method according to claim 1, wherein: atoms of the species include any one of carbon, germanium, fluorine, xenon, or neon.
6. The method according to claim 1, wherein: the target region includes a plurality of separate and non-overlapping target regions.
7. The method according to claim 6, wherein: the plurality of separate and non-overlapping target regions are formed via a pattern of a mask provided on a top surface of the SOI substrate prior to the implanting of the species.
8. The method according to claim 6, wherein: each separate target region of the plurality of separate target regions forms the trap-rich functionality for a corresponding thin silicon region of the thin silicon layer. he method according to claim 8, wherein: a projection of the corresponding thin silicon region onto a plane of the base silicon substrate immediately below the BOX layer is fully encompassed in said separate target region. . The method according to claim 8, further comprising: fabricating a transistor device configured for radio frequency (RF) operation in the corresponding thin silicon region. . The method according to claim 10, further comprising: fabricating a transistor device that is not configured for radio frequency (RF) operation in a region of the thin silicon layer that is devoid of a trap-rich functionality. . The method according to claim 8, wherein: the corresponding thin silicon region is electrically isolated via shallow trench isolation (STI) regions. . The method according to claim 1, wherein: the damaged region includes defects imparted to a crystalline structure of the base silicon substrate. . The method according to claim 1, wherein: the damaged region consists of an amorphous structure that is devoid of a crystalline structure. . The method according to claim 1, wherein: the damaged region includes a trap density of about le8 cm'2 or higher. . The method according to claim 1, wherein: the implanting of the species includes a dosage of the species that is in a range from lel5 cm'2 to 3el7 cm'2.
. The method according to claim 1, wherein: the implanting of the species includes an implanting energy that is in a range from 50 KeV to 200 KeV. . The method according to claim 1, wherein: a thickness of the target region is in a range from 20 nm to 3 pm. . A silicon-on-insulator wafer, comprising: a silicon-on-insulator substrate comprising a buried oxide (BOX) layer and a trap rich (TL) layer, wherein the TL layer is generated according to the method of claim 1. . A silicon-on-insulator (SOI) substrate, comprising: in sequence, a thin silicon layer, a buried oxide (BOX) layer, and a base silicon substrate, wherein the SOI substrate further comprises: a damaged region immediately below the BOX layer that provides a trap-rich functionality based on implanted species that include any one of carbon, germanium, fluorine, xenon, or neon. . The silicon-on-insulator (SOI) substrate according to claim 20, wherein: the damaged region includes defects imparted to a crystalline structure of the base silicon substrate. . The silicon-on-insulator (SOI) substrate according to claim 20, wherein: the damaged region consists of an amorphous structure that is devoid of a crystalline structure. . The silicon-on-insulator (SOI) substrate according to claim 20, wherein: the damaged region includes a trap density of about le8 cm'2 or higher.
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Citations (3)

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US20210280452A1 (en) * 2020-03-05 2021-09-09 Qualcomm Incorporated Creating an implanted layer in a silicon-on-insulator (soi) wafer through crystal orientation channeling

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US20160372484A1 (en) * 2015-06-17 2016-12-22 Soitec Method for manufacturing a high-resistivity semiconductor-on-insulator substrate
US20180069079A1 (en) * 2016-09-02 2018-03-08 Qualcomm Incorporated Semiconductor devices including trap rich layer regions
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