CN104253164B - 带有集成肖特基二极管的mosfet - Google Patents

带有集成肖特基二极管的mosfet Download PDF

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Publication number
CN104253164B
CN104253164B CN201410277657.2A CN201410277657A CN104253164B CN 104253164 B CN104253164 B CN 104253164B CN 201410277657 A CN201410277657 A CN 201410277657A CN 104253164 B CN104253164 B CN 104253164B
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groove
schottky
conductive material
junction structure
schottky junction
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CN104253164A (zh
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高立德
李亦衡
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明的各个方面提出了一种肖特基结构，其中两个沟槽形成在半导体材料中。沟槽通过台面结构相互间隔开。每个沟槽都有第一和第二导电部分，内衬第一和第二侧壁。第一和第二部分导电材料在每个沟槽中相互电绝缘。肖特基接头形成在最外面的导电部分之间的任意位置。肖特基结构形成在器件晶片的有源区或端接区中。要强调的是，本摘要必须使研究人员或其他读者快速掌握技术说明书的主旨内容，本摘要符合以上要求。应明确，本摘要将不用于解释或局限权利要求书的范围或意图。

Description

带有集成肖特基二极管的MOSFET
技术领域
本发明主要涉及功率器件结构以及制备器件的方法。确切地说，本发明是关于在含有有源和被动器件的系统中集成肖特基二极管的配置方法，所有的器件都依据该方法制成。
背景技术
金属-氧化物-半导体场效应晶体管（MOSFET）用于放大或切换电子信号。用于功率切换的MOSFET器件有时也称为功率MOSFET。功率MOSFET器件通常含有多个单独的MOSFET结构，排布在有源晶胞中。MOSFET器件的开关频率受到器件性能（主要是电容）的限制，在特殊应用的情况下，即直流-直流转换器，在所有功率MOSFET器件结构中寄生二极管的本征恢复。在后一种情况下，肖特基二极管通常与MOSFET器件并联，以改善器件开关动作的二极管恢复部分。另外，肖特基二极管还具有较低的正向二极管电压降等优势，可抑制器件运行时非开关部分的功率损耗。
然而，使用肖特基二极管与MOSFET器件并联的确有一些不足之处。首先，肖特基二极管通常具有很高的反向偏置漏电流，对器件的性能产生不良的影响。另外，在MOSFET器件中集成肖特基二极管，使用了晶片中原本可以用于其他有源器件的宝贵空间。其次，由于必须使用额外的掩膜，制备肖特基二极管，因此集成肖特基二极管会增加制造MOSFET器件的成本。有必要提出一种具有最小漏电流的肖特基二极管，无需额外掩膜，就可以以空间形式集成在器件中。
正是在这一前提下，提出了本发明的实施例。
发明内容
本发明提供一种带有集成肖特基二极管的MOSFET，降低肖特基二极管的漏电流，降低制造成本。
为实现上述目的，本发明提供一种肖特基结构，其特点是，其包含：
两个形成在半导体材料中的沟槽，通过台面结构相互间隔开，其中每个沟槽都内衬电介质材料，其中第一部分导电材料沿每个沟槽的第一侧壁沉积，第二部分导电材料沿每个沟槽的第二侧壁沉积，其中第一和第二部分导电材料相互电绝缘；以及
一个或若干个肖特基接头，形成在两个沟槽的最外面侧壁之间。
两个上述沟槽形成在MOSFET器件的一有源区中。
上述第一沟槽中的第一部分导电材料维持在栅极电势，第一沟槽中的第二部分导电材料维持在源极电势，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在栅极电势。
两个上述沟槽形成在MOSFET器件的端接区中。
上述第一沟槽中的第一部分导电材料维持在栅极电势，第一沟槽中的第二部分导电材料维持在源极电势，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在漏极电势。
两个上述沟槽之间的台面结构宽度等于半导体材料中形成的器件沟槽之间的台面结构宽度。
两个上述沟槽之间的台面结构宽度小于分隔器件沟槽的器件台面结构。
两个上述沟槽之间的台面结构宽度在器件台面结构宽度的四分之一和四分之三之间。
上述肖特基接头形成在两个沟槽之间的台面结构中。
上述肖特基接头还接触台面结构附近的每个沟槽中的导电部分。
上述肖特基接头形成在第一导电部分和第二导电部分之间的其中一个沟槽中。
上述肖特基接头形成在第一导电部分和第二导电部分之间的两个沟槽中。
至少一个上述肖特基接头停用，通过用掺杂物选择性地掺杂半导体材料，防止形成肖特基二极管。
上述第一肖特基接头形成在两个沟槽之间的台面结构中，第二肖特基接头形成在第一导电部分和第二导电部分之间的至少一个沟槽中。
上述第二肖特基接头配置成为一个封闭式晶胞结构。
上述肖特基结构集成在双极晶体管、绝缘栅双极晶体管、结型场效应晶体管、二极管、电阻器或电容器中。
一种用于制备肖特基结构的方法，其特点是，包含：
a）在台面结构分隔的半导体材料中制备两个沟槽；
b）用电介质材料内衬沟槽的侧壁和底面；
c）在沟槽中沉积导电材料，其中沉积的导电材料内衬侧壁和底面上的电介质材料；
d）除去沟槽底面上的导电材料，其中第一部分导电材料仍然在每个沟槽的第一侧壁上，其中第二部分导电材料仍然在每个沟槽的第二侧壁上，其中导电材料的第一和第二部分导电材料相互电绝缘；
e）用沟槽填充绝缘材料，填充第一和第二部分导电材料之间的空间；并且
f）在两个沟槽最外面的侧壁之间，制备一个肖特基接头。
两个上述沟槽形成在MOSFET器件的有源区中，其中第一沟槽中的第一部分导电材料维持在栅极电势，第一沟槽中的第二部分导电材料维持在源极电势，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在栅极电势。
两个上述沟槽形成在MOSFET器件的端接区中，其中第一沟槽中的第一部分导电材料维持在栅极电势，第一沟槽中的第二部分导电材料维持在源极电势，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在漏极电势。
上述肖特基接头形成在两个沟槽之间的台面结构中。
上述肖特基接头还接触台面结构附近的每个沟槽中的导电部分。
上述肖特基接头形成在第一导电部分和第二导电部分之间的其中一个沟槽中。
本发明带有集成肖特基二极管的MOSFET和现有技术相比，其优点在于，本发明降低肖特基二极管的漏电流，制备肖特基二极管无需额外掩膜，降低制造成本。
附图说明
图1A为依据本发明的一个方面，肖特基结构形成在有源区中器件晶片的布局俯视图；
图1B-1C为依据本发明的各个方面，图1A所示肖特基结构的放大视图；
图2A为依据本发明的一个方面，肖特基结构形成在端接区中的器件晶片布局的俯视图；
图2B-2C为依据本发明的各个方面，图2A所示肖特基结构的放大视图；
图3A-3G为依据本发明的各个方面，肖特基结构的剖面图；
图3H为依据本发明的一个方面，肖特基结构的俯视图；
图3I为图3H的剖面图；
图3J为依据本发明的一个方面，肖特基结构的俯视图；
图3K为图3J的剖面图；
图4A-4M为依据本发明的一个方面，各种制备步骤中肖特基结构的剖面图；
图5A-5B为依据本发明的一个其他方面，制备过程中肖特基结构的剖面图；
图6A-6B为依据本发明的一个其他方面，制备过程中肖特基结构的剖面图；
图7A-7B为依据本发明的一个其他方面，制备过程中肖特基结构的剖面图；
图8A-8B为依据本发明的一个其他方面，制备过程中肖特基结构的剖面图。
具体实施方式
本申请案是关于共同受让的、共同待决的申请序列号13/ 776,523的申请案，于2013年2月25日存档的题为《用于功率MOSFET应用的端接沟槽》，特此引用其全文，以作参考。
尽管为了解释说明，以下详细说明包含了许多具体细节，但是本领域的技术人员应明确以下细节的各种变化和修正都属于本发明的范围。因此，提出以下本发明的典型实施例，并没有使所声明的方面损失任何普遍性，也没有提出任何局限。
在以下详细说明中，参照附图，表示本发明可以实施的典型实施例。就这一点而言，根据图中所示方向，使用“顶部”、“底部”、“正面”、“背面”、“向前”、“向后”等方向术语。由于本发明实施例的零部件，可以位于各种不同方向上，因此所用的方向术语仅用于解释说明，不用于局限。应明确，无需偏离本发明的范围，就能实现其他实施例，做出结构或逻辑上的变化。因此，以下详细说明不用于局限，本发明的范围应由所附的权利要求书限定。
另外，本文中的浓度、数量以及其他数据都在范围格式中表示。要理解的是，此范围格式的目的仅仅为了方便简洁，应灵活理解为不仅包含明确列出的范围极限值，而且还包含所有的独立数值或范围内所包含的子范围，也就是说每个数值和子范围都明确列出。例如，1nm左右至200nm左右的厚度范围，应认为不仅包含1nm左右和200nm左右明确列出的极限值，还包含单独的数值，包含但不限于2nm、3nm、4nm以及子范围，例如10nm至50nm、20nm至100nm等都在所指的范围内。
在下文中，带有N-型外延层和P-型顶层的器件用于解释说明。使用相同的工艺，相反的导电类型，可以制备出类似的器件。
如图1A所示，形成在半导体衬底101上的器件结构100的俯视图。器件结构100包含一个形成在最外面的虚线框内的有源区102。虚线框外的区域可认为是端接区103。一个或多个端接沟槽位于端接区中。在器件结构100中，一个单独的端接沟槽（图中没有表示出）具有两个单独的导电部分115A和115B，形成在沟槽内。一个或多个端接沟槽中导电部分115A和115B的其中之一，可以连接到漏极接头108。最靠近有源区102的端接沟槽中的导电部分115A，可以连接到栅极接头128。作为示例，但不作为局限，端接沟槽可以与上述2013年2月25日存档的相关专利申请案号13/776,523的Lee等人发明的题为《用于功率MOSFET应用的端接沟槽》的专利中提出的端接沟槽基本类似，特此引用其全文。
在有源区102中，表示出有源器件结构的栅极电极114。有源区中的器件沟槽内衬电介质材料（图中没有表示出），并用导电材料填充，以形成栅极电极114。栅极电极114可以通过栅极接头128，连接到栅极金属（图中没有表示出）。栅极电极114呈条纹方向，但是本发明的可选方面还包含可选择的器件布局，例如，但不局限于封闭式晶胞方向。栅极接头128可以用导电材料（例如钨）制成。栅极接头128可以垂直于图平面延伸，以便与栅极金属（图中没有表示出）电接触。栅极金属可以初步作为与源极金属（图中没有表示出）相同的金属层的一部分。栅极金属可以通过掩膜、刻蚀和电介质填充等常用工艺，与源极金属电绝缘。另外，肖特基结构180形成在有源区102中。在图1A中，仅表示出了肖特基结构180的导电部分115A和115B。图1B和1C表示依据本发明的各个方面，不同肖特基结构的放大俯视图。
如图1B所示，两个沟槽113A和113B相互平行。两个通道可以通过台面结构M相互间隔开。台面结构M的宽度小于或等于将器件沟槽相互间隔开的器件台面结构的宽度。选择台面结构M的宽度，使沿台面结构M附近的沟槽113A和113B侧面形成的耗尽区合并在一起，从而允许合适的控制反向闭锁状态漏电流，但是对于大幅增大（二极管的）二极管正向电压并没有过度约束，从而防止肖特基二极管作为减少（功率）损耗的有效方式。作为示例，但不作为局限，台面结构M的宽度约在有源器件结构之间的台面结构宽度的四分之一和四分之三之间。每个沟槽的侧壁都内衬电介质材料111。导电材料115可以沉积在每个内衬的沟槽壁附近。同样地，每个沟槽都有一个第一和第二导电部分。每个沟槽中的两个导电部分115都通过绝缘材料（例如氧化物）117相互电绝缘。如图1B所示，在沟槽113A中，第一导电部分115A1与第二导电部分115A2分开，在沟槽113B中，第一导电部分115B1与第二导电部分115B2分开。导电部分115和栅极电极114可以由同样的材料制成，例如多晶硅，在同一工艺步骤中，形成在相应的沟槽中。两个沟槽之间，形成一个肖特基接头182。作为示例，但不作为局限，肖特基接头182可以由通过CVD沉积的钨制成。
如图1C所示，依据本发明的一个其他方面，肖特基结构180’的俯视图。结构180’中除了改变了肖特基接头182的位置之外，其他都与肖特基结构180基本类似。肖特基接头182不是形成在台面结构M中，而是形成在第一和第二导电部分115B1和115B2之间。肖特基接头182穿过沟槽113B的底部，以便与沟槽底部的衬底101接触。虽然图1C表示出了一个单独的肖特基接头182，但是本发明的各个方面还包含一种结构，在该结构中沟槽113A和113B中的第一和第二部分115之间有一个肖特基接头182。依据本发明的其他方面，肖特基接头182可以形成在台面结构M中，如图1B所示，以及形成在一个或两个沟槽113A和113B中的导电部分115之间。另外，虽然图1A中将肖特基结构180表示成一个单独的条形，但是根据器件100的说明，也可能有一个以上的条形，或仅有一个单独条形的一部分。
如图2A所示，本发明的一个其他方面的俯视图，其中器件200具有一个肖特基结构181，形成在端接区103中。在图2A中，有源区102中的有源器件结构与上述图1A-1C所示的有源器件结构基本类似。图2A仅表示了第一沟槽113A的导电部分115A1、115A2，以及第二沟槽113B的导电部分115B1和115B2。将肖特基结构置于端接区103中，节省了有源区102中的空间，用于其他的有源器件结构。在图2A所示示例中，导电部分115A2和115B1可以通过导电短路183相互电连接，从而将内部导电部分115A2短接至源极电势。
如图2B所示，依据本发明的一个方面，端接肖特基结构181处的放大视图。两个沟槽113A和113B相互平行。两个沟槽通过台面结构M相互间隔开。台面结构M的宽度小于或等于将器件沟槽相互间隔开的器件台面结构的宽度。选择台面结构M的宽度，使沿台面结构M附近的沟槽113A和113B侧面形成的耗尽区合并在一起，从而允许合适的控制反向闭锁状态漏电流，但是对于大幅增大（二极管的）二极管正向电压并没有过度约束，从而防止肖特基二极管作为减少（功率）损耗的有效方式。作为示例，但不作为局限，台面结构M的宽度约在有源器件结构之间的台面结构宽度的四分之一和四分之三之间。每个沟槽的侧壁都内衬电介质材料111。导电材料115可以沉积在每个内衬的沟槽壁附近。同样地，每个沟槽都有一个第一和第二导电部分。每个沟槽中的两个导电部分115都通过绝缘材料（例如氧化物）117相互电绝缘。如图2B所示，在沟槽113A中，第一导电部分115A1与第二导电部分115A2分开，在沟槽113B中，第一导电部分115B1与第二导电部分115B2分开。导电部分115和栅极电极114可以由同样的材料制成，例如多晶硅，在同一工艺步骤中，形成在相应的沟槽中。两个沟槽之间，形成一个肖特基接头182。作为示例，但不作为局限，肖特基接头182可以由通过CVD沉积的钨制成。
如图2C所示，依据本发明的一个其他方面，肖特基结构181’的俯视图。结构181’中除了改变了肖特基接头182的位置之外，其他都与肖特基结构180基本类似。肖特基接头182不是形成在台面结构M中，而是形成在第一和第二导电部分115B1和115B2之间。肖特基接头182穿过沟槽113B的底部，以便与沟槽底部的衬底101接触。虽然图1C表示出了一个单独的肖特基接头182，但是本发明的各个方面还包含一种结构，在该结构中沟槽113A和113B中的第一和第二部分115之间有一个肖特基接头182。依据本发明的其他方面，肖特基接头182可以形成在台面结构M中，如图2B所示，以及形成在一个或两个沟槽113A和113B中的导电部分115之间。
如图3A所示，为图1B所示的肖特基结构180沿线3A-3A的剖面图。肖特基结构180形成在半导体衬底301上。另外，按照相同的半导体制备工艺，可以在同一个衬底中形成多个这样的肖特基结构180。衬底301可以适当掺杂成为N-型或P-型衬底。作为示例，但不作为局限，半导体衬底301可以是N-型硅衬底。半导体衬底可以重掺杂N+漏极区305。作为示例，但不作为局限，漏极区305的掺杂浓度约为1019cm-3或更大。漏极区305可以电连接到形成在半导体衬底底面上的漏极电极（图中没有表示出）。漏极区305上方可以是一个轻掺杂的N-漏极区306。作为示例，漏极区306的掺杂浓度约在1015cm-3至1017cm-3之间。漂流区306上方，除了在台面结构部分M中，可以形成一个第二导电类型的适当掺杂的本体区319，第二导电类型与半导体衬底的第一导电类型相反。第一导电类型的源极区320形成在本体层319的顶部。作为示例，正如本发明的其他部分所述，半导体衬底301可以是N-型半导体衬底，本体区319可以为P-型，源极区320可以为N-型，
两个沟槽313A和313B形成在衬底301中。沟槽313A和313B的深度与有源区102中的器件沟槽深度大致相同。沟槽的宽度313A和313B大于有源器件结构的宽度。选择肖特基结构180中沟槽313的宽度，使得当沟槽填充材料填充的器件沟槽形成栅极电极114时，沟槽填充材料仅仅内衬沟槽313A和313B的侧壁和底部。作为示例，但不作为局限，沟槽的宽度至少是器件沟槽宽度的两倍，例如如果器件沟槽的宽度约为0.5微米，那么沟槽313A和313B的宽度就是1.0微米或以上。每个沟槽313A和313B都具有顶部373和底部374。电介质材料311内衬沟槽壁。电介质材料311在沟槽374底部的厚度为T2，电介质材料在沟槽373顶部的厚度为T1。依据本发明的其他方面，厚度T1小于厚度T2。
离台面结构M最远的内衬沟槽313A侧壁的沟槽填充材料，可以称为第一部分导电材料315A1，靠近台面结构M的内衬沟槽315A侧壁的沟槽填充材料，可以称为第二部分导电材料315A2。最靠近台面结构M的内衬沟槽313B侧壁的沟槽填充材料，可以称为第一部分导电材料315B1，离台面结构M最远的内衬沟槽315B侧壁的沟槽填充材料，可以称为第二部分导电材料315B2。
在每个沟槽中，第一和第二部分导电材料通过绝缘材料317相互电绝缘。作为示例，绝缘材料317可以是氧化物。第一和第二部分导电材料相互电绝缘，使得每一部分都维持在独立的电压。当肖特基结构180集成在器件100的有源区中时，最外面的导电部分（即沟槽313A中的第一导电部分315A1以及沟槽313B中的第二导电部分315B2）必须维持在栅极电势。这使得有源晶体管器件形成在肖特基结构180和肖特基结构180附近的器件沟槽之间。内部导电部分（即沟槽313A中的第二导电部分315A2以及沟槽313B中的第一导电部分315B1）维持在源极电势。由于内部导电部分315A2、315B1延伸到沟槽的整个长度，因此实现了对肖特基接头最大程度的保护。
依据本发明的其他方面，电场线调谐区316可以选择形成在沟槽下方。通过用P-型掺杂物（例如硼）掺杂沟槽313下方的半导体衬底301，形成电场线调谐区316。调节掺杂剂量，以便进一步控制肖特基结构180中的电场线分布。例如，在30至80KeV的能量下，注入剂量范围为2e11至5e12个原子/cm2的硼。
第一绝缘垫片321沿绝缘层322上方的绝缘材料317的每个垂直边缘沉积。作为示例，但不作为局限，第一绝缘垫片321的材料与绝缘材料317相同。另外，第二绝缘层323形成在绝缘材料317上方，并且沿第一绝缘垫片321的裸露侧壁。作为示例，但不作为局限，第一绝缘垫片321可以由抵抗刻蚀剂的材料制成，刻蚀剂能够选择除去制成第二绝缘层323的材料。作为示例，第一绝缘垫片321可以是氧化物，第二绝缘层323可以是氮化物。氧化物可抵抗热磷酸，而氮化物将被热磷酸选择性地刻蚀掉。另外，第一绝缘垫片321和第二绝缘层323可以由同一种绝缘材料（例如氮化物）制成。
沿最外面的导电部分315A1、315B2上方的第一绝缘垫片321的裸露侧壁，形成的第一绝缘垫片321和第二绝缘层323的组合，使得垂直连接329在肖特基结构180和及其附近的器件沟槽之间自对准。外部绝缘物324可以形成在第二绝缘层323上方。作为示例，但不作为局限，外部绝缘物324可以是硼磷硅玻璃（BPSG）。在沟槽313A、313B之间，形成一个肖特基接头382。肖特基接头382将源极金属层331连接到衬底301。作为示例，但不作为局限，肖特基接头382可以由钨等导电材料制成。依据本发明的一些方面，肖特基接头382可以内衬钛或氮化钛等势垒金属383。将肖特基接头382置于两个沟槽之间，通过沟槽313A和313B之间的耦合，可以降低肖特基接头的漏电流。为了提升肖特基接头的性能，可以在肖特基接头附近的衬底301中注入掺杂物，形成肖特基调谐区384。可以使用N型和P型掺杂物，调节肖特基二极管的性能。
如图3B所示，为沿图1C所示的线3B-3B，肖特基结构180’的剖面图。肖特基结构180’中除了肖特基接头382的位置之外，其他都与图3A所示的肖特基结构180基本类似。除了形成在沟槽315B中的第一和第二部分导电材料315B1、315B2之外，可以通过绝缘材料317制备一个垂直连接，形成肖特基接头382。肖特基接头可以电连接到源极金属331，并且穿过外部绝缘物324、第二绝缘层323、沟槽绝缘物317以及电介质材料311延伸，从而将源极金属331连接到漂流区306和/或沟槽结构下方的场调谐区316。另外，掺杂物可以插入到沟槽底部，以形成一个肖特基调谐区384，提升肖特基二极管的性能。
如图3C所示，为沿图2B所示的线3C-3C，肖特基结构181的剖面图。肖特基结构181中除了维持导电部分315的电势之外，其他都与图3A所示的肖特基结构180基本类似。由于肖特基结构181形成在端接区中，离有源区102最远的最外面的导电部分315B2维持在漏极电势。离有源区102最近的导电部分315A1维持在栅极电势。靠近台面结构M的两个导电部分315A2、315B1维持在源极电势。利用（例如图2A所示的）导电短路结构，完成上述结构。另外，由于肖特基结构181位于端接区103中，因此形成在肖特基结构外部的源极320和本体层319可以忽略。然而，为使最靠近端接结构的有源器件成为功能器件，源极319和本体层320可以形成在沟槽315A附近。
如图3D所示，为沿图2C所示的线3D-3D，肖特基结构181’的剖面图。肖特基结构181’中除了肖特基接头382的位置之外，其他都与图3C所示的肖特基结构181基本类似。通过沟槽313B的底部，形成肖特基接头382。除了形成在沟槽315B中的第一和第二部分导电材料315B1、315B2之外，可以通过绝缘材料317制备一个垂直连接，形成肖特基接头382。肖特基接头可以电连接到源极金属331，并且穿过外部绝缘物324、第二绝缘层323、沟槽绝缘物317以及电介质材料311延伸，从而将源极金属331连接到漂流区306和/或沟槽结构下方的场调谐区316。另外，掺杂物可以插入到沟槽底部，以形成一个肖特基调谐区384，提升肖特基二极管的性能。
如图3E所示，为依据本发明的一个其他方面，肖特基结构180”的剖面图。肖特基结构180”与图3B所示的肖特基结构180’基本类似，一个额外的肖特基接头182形成在沟槽313A中。额外的肖特基接头382包含一个肖特基调谐区384。还可选择，用会使肖特基二极管失效的掺杂物，代替一个或两个肖特基调谐区384。因此，可以使用同一个掩膜装置，制备带有一个、两个或零个肖特基二极管的器件。在一个示例中，P-型掺杂物可以用于使肖特基接头失效。尤其是，可以使表面浓度高于1e18/cm3的p-型剂量（例如硼），足以使肖特基接头失效。
如图3F所示，为依据本发明的另一个其他方面，肖特基结构180”’的剖面图。肖特基结构180”’与肖特基结构180基本类似，引入了一个额外的肖特基接头382。第二个肖特基接头382与肖特基结构180’中使用的肖特基接头382基本类似。因此，肖特基结构180”’使用了位于台面结构M中的肖特基接头以及一个或两个沟槽313A和/或313B下方的衬底301。
在图3A-3F中，通过剖面图中没有表示出来的三维连接，使内部导电部分（例如315A2和315B1）维持在源极电势。依据本发明的其他方面，可以在图中所示的剖面图中，形成到源极金属的连接。图3G所示的肖特基结构185是一种这样的器件。可以加宽，而不是在三维方向上连接肖特基接头182，以便通过沟槽313A、313B中的一部分绝缘材料317部分刻蚀。因此，源极金属331也可以连接到沟槽313A的第二导电部分315A2，以及沟槽313B的第一导电部分315B1。沿沟槽侧壁的外部绝缘内衬311仍然处于合适的地方。
如图3H-3K所示，为依据本发明的各个方面，封闭式晶胞肖特基结构的示例。图3H为第一封闭式晶胞肖特基结构的俯视图，图3I表示沿线3H-3H，图3H所示结构的剖面图。图3H-3I所示结构与图3A、图3C和图3F所示剖面图类似。然而，与图1B和图2B所示结构不同，沟槽315A、315B之间的肖特基接头382’并不是一个连续条形。与之相反，由图3H可见，沟槽315A、315B之间的肖特基接头382’是一个短接的封闭式晶胞垂直接头，配置沟槽和单独的导电部分315A2、315B1，在短接的肖特基接头382’周围形成回路。
如图3J所示，一种可选的封闭式晶胞肖特基结构的俯视图，图3K表示沿线3J-3J，图3J所示结构的剖面图。图3J-3K所示结构与图3G所示的剖面图类似。确切地说，图3J所示的封闭式晶胞肖特基结构包含一个沟槽315A、315B之间的肖特基接头382’。肖特基接头382’覆盖了导电部分315AB。然而，沟槽315A、315B之间的肖特基接头382’并不是一个连续条形。另外，肖特基接头382’被电连接到源极电势的导电部分315AB包围着，构成一个封闭式晶胞肖特基接头。
图4A-4M表示依据本发明的一个方面，一种用于制备器件100的方法，其中肖特基结构形成在有源区102中。
如图4A所示，为半导体器件结构100。该器件结构形成在衬底301上，衬底301适当掺杂成为N-型或P-型衬底。作为示例，但不作为局限，半导体衬底301可以为N-型硅衬底。其中所述的器件结构100的衬底可以表示为N-型硅衬底。该半导体衬底301包含一个轻掺杂的漂流区306，形成在衬底顶部，以及一个重掺杂的漏极接触区305，形成在半导体衬底的底部。在轻掺杂漂流区306顶部，可以形成一个氧化物-氮化物-氧化物（ONO）硬掩膜层。作为示例，但不作为局限，底部氧化层307可以为200Å左右，氮化层308可以为3500 Å左右，顶部氧化层309可以为1400 Å左右。
如图4B所示，为多个初始处理工艺后的器件结构100。首先，利用沟槽掩膜和刻蚀工艺，形成沟槽313A和313B的顶部。沟槽刻蚀工艺包含用于除去ONO硬掩膜层307、308、309的蚀刻剂，以便使衬底的顶面裸露出来，以及用于形成沟槽313A和313B顶部的第二刻蚀工艺。作为示例，但不作为局限，沟槽313A和313B的顶部约为0.5μm深。沟槽313A和313B可以比有源区102中的有源器件结构中所用的沟槽更宽。选择沟槽313A和313B的宽度，使有源区中的器件沟槽，在后续沟槽填充工艺中，用导电材料完全填充，而相同的沟槽填充工艺仅使沟槽313A和313B内衬导电材料。作为示例，但不作为局限，沟槽313A和313B可以比器件沟槽大两倍。一旦形成沟槽之后，则在每个沟槽313中热生长大约100Å厚的衬垫氧化物311a。生长衬垫氧化物311a之后，可以在衬底氧化物311a上方沉积一个氮化层312。作为示例，但不作为局限，氮化层312约为500 Å厚。
图4C表示制备沟槽的底部。首先，通过一个或多个扩散工艺，除去沟槽底面上的氮化层312和氧化层311a。然后，刻蚀沟槽顶部下方的漂流区306，以增大沟槽313A和313B的深度。作为示例，但不作为局限，沟槽顶部和底部的总深度约为1.0μm。另外，作为示例，但不作为局限，沟槽313的纵横比（即沟槽深度除以沟槽宽度）在1和100之间。然后，在沟槽底部裸露的硅中热生长一个衬垫氧化物311b。作为示例，沟槽313底部的衬垫氧化物生长至600 Å左右的厚度T2。沿沟槽顶部侧壁的氮化层312作为掩膜，减小沟槽底部的宽度。
在图4D中，通过湿浸，除去沟槽顶部侧壁的氮化物312和衬垫氧化物311a。然后，在沟槽313顶部侧壁上的裸露硅上，生长栅极氧化物311c至所需厚度T1。作为示例，但不作为局限，对于12V器件来说，氧化物311c的厚度T1约为265Å。因此，沟槽底部的氧化物311的厚度T2大于沟槽顶部的厚度T1。虽然上述说明所提出的氧化物311的厚度可以根据沟槽的深度变化，但是具有均匀栅极氧化物的厚度311仍然在本发明的范围内。
然后，在图4D中，沟槽313用导电材料315部分填充。作为示例，但不作为局限，导电材料可以是N+-掺杂多晶硅，多晶硅可以通过化学气相沉积（CVD）沉积。在沟槽中沉积导电材料315可以与在有源区102中形成栅极电极114同时进行。由于沟槽313比栅极电极114的沟槽更宽，因此沟槽313中的导电材料315仅内衬底部和侧壁。要注意的是，为了表示清楚，忽略了器件的沟槽和栅极电极114的剖面细节。在于2013年2月25日存档的共同受让的、共同待决的美国申请序列号13/776,523的申请案（代理人案号ANO-061/US）提出了有源器件的结构和制备的详细示例，特此引用其全文，以作参考。
在图4E中，利用化学机械抛光（CMP）使导电材料315与硬掩膜的表面相平。然后，如图4E所示，将导电材料315回刻到半导体衬底的表面。作为示例，但不作为局限，可以利用干刻蚀工艺进行刻蚀。在这个过程中，除去内衬沟槽313底部的导电材料315，从而在每个沟槽中形成导电材料的两个独立部分。在第一沟槽313A中的第一导电部分标记为315A1，第二导电部分标记为315A2。在第二沟槽313B中的第一导电部分标记为315B1，第二导电部分标记为315B2。导电材料的第一和第二部分相互电绝缘，使每个部分都维持在不同的电压。当在器件100的有源区中集成肖特基结构180时，必须使最外面的导电部分（即沟槽313A中的第一导电部分315A1，以及沟槽313B中的第二导电部分315B2）维持在栅极电势。使得有源晶体管器件（例如MOSFET器件、双极晶体管、绝缘栅双极晶体管、结型场效应晶体管或二极管），或非有源器件（例如电阻器或电容器），形成在肖特基结构180及其附近的器件沟槽之间。内部导电部分（即沟槽313A中的第二导电部分315A2，以及沟槽313B中的第一导电部分315B1）维持在源极电势。由于内部导电部分315A2、315B1延伸沟槽的整个长度，因此对于肖特基接头的屏蔽达到最大化。
依据本发明的一个其他方面，其中器件200包含一个位于端接区103中的肖特基结构181（如图3C所示），导电部分的电势可以变化。由于肖特基结构181形成在端接区中，因此离有源区102最远的最外面的导电部分315B2维持在漏极电势。离有源区102最近的导电部分315A1维持在栅极电势。靠近台面结构M的两个导电部分315A2、315B1维持在源极电势。
另外，除去沟槽313底部的导电材料315之后，可以在沟槽313A、313B下方形成一个场线调谐区316。通过注入导电类型与漂流区306相反的掺杂物，形成场线调谐区316。作为示例，但不作为局限，在30至80KeV左右的能量下，注入剂量范围在2e11至5e12个原子/cm2的硼。
在图4F中，用绝缘材料317填充沟槽313A、313B。作为示例，但不作为局限，绝缘材料317可以是氧化物。绝缘材料317使沟槽313A中的第一和第二部分导电沟槽材料315A1和315A2电绝缘，以及第一和第二部分导电沟槽材料315B1和315B2电绝缘。一旦形成绝缘材料317之后，通过CMP除去ONO硬掩膜的顶部氧化层309。通过CMP，还可以使绝缘材料317与氮化层308相平。
在图4G中，除去ONO硬掩膜的氮化层308。作为示例，但不作为局限，通过热磷酸湿浸，可以选择性地除去硬掩膜。然后，形成本体区319。作为示例，但不作为局限，通过本体掩膜和全面注入，或通过离子注入系统的选择性注入离子，制成本体区319。图4G还表示制备源极区320。作为示例，但不作为局限，通过源极掩膜和全面注入，或通过离子注入系统的选择性注入离子，制成源极区320。防止沟槽313之间的台面结构M接受本体注入和源极注入。
图4G’表示依据本发明的一个其他方面，制备源极和本体区，其中器件200包含一个位于端接区103中的肖特基结构181（如图3C所示）。本体和源极掩膜还能防止掺杂物注入到最外面的导电部分315B2附近。源极和本体注入之后，肖特基结构181的后续工艺与肖特基结构180基本类似。
图4H表示沉积一个厚牺牲绝缘层321’。作为示例，牺牲绝缘层的厚度约为1,100Å。作为示例，绝缘层321’可以是用源极气（例如TEOS）通过CVD沉积的氧化物。还可选择，绝缘层321’可以是用SiH4和NH3气体混合物通过CVD工艺沉积的氮化物材料。然后，在图4I中，利用各向异性刻蚀（例如干刻蚀工艺）刻蚀厚绝缘层321’，以便沿裸露的绝缘材料317侧面形成第一绝缘垫片321。作为示例，绝缘垫片321的厚度约为1000 Å左右。当绝缘层321’为氧化物时，刻蚀工艺终止在硅衬底表面，从而除去ONO硬掩膜上不在第一绝缘垫片321下方的那部分底部氧化层307。然后，在衬底表面上生长一个衬垫氧化物322。作为示例，但不作为局限，衬垫氧化物的厚度约为100 Å左右。
还可选择，利用类似的工艺，在使用氮化物材料作为牺牲绝缘层321’的器件中制备第一绝缘垫片321。在这种情况下，可以通过各向异性地刻蚀工艺，选择性地刻蚀掉氮化物材料，在合适的位置保留ONO硬掩膜的底部氧化层307。因此，无需生长衬垫氧化物322。一旦形成第一绝缘垫片321之后，制备具有由氮化物材料制成的第一绝缘垫片的器件工艺，按照上述由氧化物制成的第一绝缘垫片321基本相同的工艺继续进行。
制成第一绝缘垫片321之后，在如图4J所示的表面上方沉积一个牺牲氮化层323。作为示例，氮化层323的厚度约为300Å左右。利用SiH4和NH3气体混合物，通过CVD工艺沉积氮化层323。如图4K所示，一层很厚的含有硼酸的硅玻璃（BPSG）324，通过CVD工艺，沉积在氮化层323上方。
在图4L中，使用一个接触掩膜，制备肖特基沟槽325，提供导电垂直连接台面结构M的接口，以形成肖特基接头382。刻蚀工艺使用三个独立的刻蚀步骤。首先，使用除去BPSG层324，而不除去BPSG下方氮化层323的蚀刻剂。由于存在氮化物终止层323，没有机会过度刻蚀，因此必须快速刻蚀。利用第二种蚀刻剂，选择性地通过氮化层323刻蚀。然后，使用对氧化物具有高度选择性的第三种蚀刻剂，穿通衬垫氧化层323。另外，在台面结构M的顶面上形成一个肖特基调谐区384。作为示例，但不作为局限，通过在台面结构的顶面上注入掺杂物，形成肖特基调谐区384。利用注入调节肖特基的性能，这种注入有时也称为香农注入，可用于调节肖特基界面的势垒高度。这通常可以通过降低但不反转金属-硅界面处的局域掺杂浓度来完成。在这种情况下，注入类型与轻掺杂漂流区的类型相反。对于n-型漂流层的情况，可以在30KeV左右的能量下，注入剂量范围在1e11至1e12的硼或BF2。这仅是其中一个示例，注入参数的其他组合也可能达到相同的目的。
在图4M中，在肖特基沟槽325的表面上方，沉积一个势垒金属383。作为示例，但不作为局限，势垒金属可以是通过物理气相沉积（PVD）沉积的钛，或者通过CVD或PVD沉积的TiN等合金。沉积势垒金属之后，可以沉积导电材料，以形成肖特基接头382。作为示例，但不作为局限，肖特基接头382可以由通过CVD沉积的钨制成。一旦沉积一层钨之后，则进行回刻，以便保留主要在垂直接触孔中的钨。然后，在整个表面上方沉积金属，为源极和栅极提供合适的接头。最后，利用一个金属掩膜，刻蚀掉那部分沉积的金属，从而使源极金属331和栅极金属（图中没有表示出）中的接触区电绝缘。
如图5A-5B所示，为使用的额外步骤，以便制备带有图3B所示肖特基结构180’的器件100。器件100’按照图4A-4K所示相同的工艺。然而，肖特基沟槽325不是形成在台面结构M上方，而是如图5A所示，通过每个沟槽313B的中心，形成肖特基沟槽。在肖特基沟槽325的底部，注入肖特基调谐区384。适当掺杂的肖特基调谐区会使肖特基接头正常运转。但是，如果改变了肖特基调谐区的掺杂浓度，那么肖特基接头可以选择停用。这样做十分有益的原因在于，带有或不带有肖特基接头的器件都可以利用单独的掩膜组制备。
形成肖特基沟槽325之后，在肖特基调谐区注入所需的掺杂物，形成肖特基接头。在图5B中，在沟槽325的侧壁和底面上，沉积一个势垒金属383。作为示例，但不作为局限，势垒金属可以是通过物理气相沉积（PVD）沉积的钛，或者是通过CVD或PVD沉积的TiN等合金。沉积势垒金属之后，可以沉积导电材料，以便形成肖特基接头382。作为示例，但不作为局限，肖特基接头382可以由通过CVD沉积的钨制成。一旦沉积了一层钨之后，则进行回刻，以便保留主要在垂直接触孔中的钨。然后，在整个表面上方沉积金属，为源极和栅极提供合适的接头。最后，利用一个金属掩膜，刻蚀掉那部分沉积的金属，从而使源极金属331和栅极金属（图中没有表示出）中的接触区电绝缘。
如图6A-6B所示，表示使用的额外步骤，以便制备带有图3E所示肖特基结构180”的器件100。肖特基结构180”按照图4A-4K所示相同的工艺。然而，肖特基沟槽325不是形成在台面结构M上方，而是如图6A所示，通过每个沟槽313A和313B的中心，形成两个肖特基沟槽。在一个或两个肖特基沟槽325的底部，注入肖特基调谐区384。控制沟槽底部的掺杂，允许器件中拥有一个、两个或零个肖特基接头。适当掺杂的肖特基调谐区会使肖特基接头正常运转。但是，如果改变了肖特基调谐区的掺杂浓度，那么肖特基接头可以选择停用。这样做十分有益的原因在于，带有或不带有肖特基接头的器件都可以利用单独的掩膜组制备。
形成肖特基沟槽325之后，在肖特基调谐区注入所需的掺杂物，形成肖特基接头。在图6B中，在沟槽325的侧壁和底面上，沉积一个势垒金属383。作为示例，但不作为局限，势垒金属可以是通过物理气相沉积（PVD）沉积的钛，或者是通过CVD或PVD沉积的TiN等合金。沉积势垒金属之后，可以沉积导电材料，以便形成肖特基接头382。作为示例，但不作为局限，肖特基接头382可以由通过CVD沉积的钨制成。一旦沉积了一层钨之后，则进行回刻，以便保留主要在垂直接触孔中的钨。然后，在整个表面上方沉积金属，为源极和栅极提供合适的接头。最后，利用一个金属掩膜，刻蚀掉那部分沉积的金属，从而使源极金属331和栅极金属（图中没有表示出）中的接触区电绝缘。
如图7A-7B所示，表示使用的额外步骤，以便制备带有图3F所示肖特基结构180”’的器件100。肖特基结构180”’按照图4A-4K所示相同的工艺。然而，肖特基沟槽325不是形成在台面结构M上方，而是如图7A所示，通过一个或两个沟槽313A和313B的中心，形成一个额外的肖特基沟槽。形成沟槽325之后，可以按照与上述制备肖特基接头382基本相同的方式继续进行。与7B表示最终的带有肖特基接头382的肖特基结构180’”，肖特基接头382接触台面结构M以及沟槽313B下方的衬底301。与本发明的可选方面中所述的肖特基接头类似，肖特基沟槽325内衬势垒金属383，肖特基调谐区384形成在肖特基接头下方。
图8A-8B表示表示使用的额外步骤，以便制备带有图3G所示肖特基结构185的器件100。肖特基结构185按照图4A-4K所示相同的工艺。然而，肖特基沟槽325不是形成在台面结构M上方，而是肖特基沟槽325较宽，使得如图8A所示，与沟槽313A中的第二部分导电材料315A2电接触，以及与沟槽313B中的第一部分导电材料315B1电接触。图8B表示最终的带有肖特基接头382的肖特基结构185，肖特基接头382接触台面结构M以及导电部分313A2和313B1。与本发明的可选方面中所述的肖特基接头类似，肖特基沟槽325内衬势垒金属383，肖特基调谐区384形成在台面结构M中的肖特基接头下方。
本发明提出了一种器件结构，以及在含有有源和被动器件的系统中集成肖特基二极管的方法。作为示例，但不作为局限，鉴于功率MOSFET在行业中的普遍存在以及在功率电子学中的重要性，可以选择功率MOSFET作为本发明所述的初级有源器件。按照本发明所述方法制成的任意器件结构，都将作为与上述肖特基二极管集成的备选器件。这种器件包含，但不限于双极晶体管、绝缘栅双极晶体管（IGBT）、结型场效应晶体管（JFET）以及二极管等有源器件，以及电阻器和电容器等被动器件。尽管以上是本发明的较佳实施例的完整说明，但是也有可能使用各种可选、修正和等效方案。因此，本发明的范围不应局限于以上说明，而应由所附的权利要求书及其全部等效内容决定。任何可选件（无论首选与否），都可与其他任何可选件（无论首选与否）组合。在以下权利要求中，除非特别声明，否则不定冠词“一 个”或“一种”都指下文内容中的一个或多个项目的数量。除非在指定的权利要求中用“意思是”特别指出，否则所附的权利要求书应认为是包含意义及功能的限制。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (24)

1.一种肖特基结构，其特征在于，其包含：
两个形成在半导体材料中的沟槽，通过台面结构相互间隔开，其中每个沟槽都内衬电介质材料，其中第一部分导电材料沿每个沟槽的第一侧壁沉积，第二部分导电材料沿每个沟槽的第二侧壁沉积，其中第一和第二部分导电材料相互电绝缘；以及
一个或若干个肖特基接头，形成在两个沟槽的最外面侧壁之间；
第一沟槽中的第一部分导电材料维持在栅极电势；
第一沟槽中的第二部分导电材料维持在源极电势。
2.如权利要求1所述的肖特基结构，其特征在于，两个所述沟槽形成在MOSFET器件的一有源区中。
3.如权利要求2所述的肖特基结构，其特征在于，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在栅极电势。
4.如权利要求1所述的肖特基结构，其特征在于，两个所述沟槽形成在MOSFET器件的端接区中。
5.如权利要求4所述的肖特基结构，其特征在于，所述第一沟槽中的第一部分导电材料维持在栅极电势，第一沟槽中的第二部分导电材料维持在源极电势，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在漏极电势。
6.如权利要求1所述的肖特基结构，其特征在于，两个所述沟槽之间的台面结构宽度等于半导体材料中形成的器件沟槽之间的台面结构宽度。
7.如权利要求1所述的肖特基结构，其特征在于，两个所述沟槽之间的台面结构宽度小于分隔器件沟槽的器件台面结构。
8.如权利要求7所述的肖特基结构，其特征在于，两个所述沟槽之间的台面结构宽度在器件台面结构宽度的四分之一和四分之三之间。
9.如权利要求1所述的肖特基结构，其特征在于，所述肖特基接头形成在两个沟槽之间的台面结构中。
10.如权利要求9所述的肖特基结构，其特征在于，所述肖特基接头还接触台面结构附近的每个沟槽中的导电部分。
11.如权利要求1所述的肖特基结构，其特征在于，所述肖特基接头形成在第一导电部分和第二导电部分之间的其中一个沟槽中。
12.如权利要求1所述的肖特基结构，其特征在于，所述肖特基接头形成在第一导电部分和第二导电部分之间的两个沟槽中。
13.如权利要求12所述的肖特基结构，其特征在于，至少一个所述肖特基接头停用，通过用掺杂物选择性地掺杂半导体材料，防止形成肖特基二极管。
14.如权利要求1所述的肖特基结构，其特征在于，所述肖特基接头中，第一肖特基接头形成在两个沟槽之间的台面结构中，第二肖特基接头形成在第一导电部分和第二导电部分之间的至少一个沟槽中。
15.如权利要求1所述的肖特基结构，其特征在于，所述肖特基接头中，第二肖特基接头配置成为一个封闭式晶胞结构。
16.如权利要求1所述的肖特基结构，其特征在于，所述肖特基结构集成在双极晶体管、结型场效应晶体管、二极管、电阻器或电容器中。
17.如权利要求16所述的肖特基结构，其特征在于，所述双极晶体管为绝缘栅双极晶体管。
18.一种用于制备肖特基结构的方法，其特征在于，包含：
a）在台面结构分隔的半导体材料中制备两个沟槽；
b）用电介质材料内衬沟槽的侧壁和底面；
c）在沟槽中沉积导电材料，其中沉积的导电材料内衬侧壁和底面上的电介质材料；
d）除去沟槽底面上的导电材料，其中第一部分导电材料仍然在每个沟槽的第一侧壁上，其中第二部分导电材料仍然在每个沟槽的第二侧壁上，其中导电材料的第一和第二部分导电材料相互电绝缘；
e）用沟槽填充绝缘材料，填充第一和第二部分导电材料之间的空间；并且
f）在两个沟槽最外面的侧壁之间，制备一个肖特基接头；
其中，第一沟槽中的第一部分导电材料维持在栅极电势；
第一沟槽中的第二部分导电材料维持在源极电势。
19.如权利要求18所述的方法，其特征在于，两个所述沟槽形成在MOSFET器件的有源区中，其中第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在栅极电势。
20.如权利要求18所述的方法，其特征在于，两个所述沟槽形成在MOSFET器件的端接区中，其中第一沟槽中的第一部分导电材料维持在栅极电势，第一沟槽中的第二部分导电材料维持在源极电势，第二沟槽中的第一部分导电材料维持在源极电势，第二沟槽中的第二部分导电材料维持在漏极电势。
21.如权利要求18所述的方法，其特征在于，所述肖特基接头形成在两个沟槽之间的台面结构中。
22.如权利要求21所述的方法，其特征在于，所述肖特基接头还接触台面结构附近的每个沟槽中的导电部分。
23.如权利要求18所述的方法，其特征在于，所述肖特基接头形成在第一导电部分和第二导电部分之间的其中一个沟槽中。
24.一种肖特基结构，其特征在于，其包含：
两个形成在半导体材料中的沟槽，通过台面结构相互间隔开，其中每个沟槽都内衬电介质材料，其中第一部分导电材料沿每个沟槽的第一侧壁沉积，第二部分导电材料沿每个沟槽的第二侧壁沉积，其中第一和第二部分导电材料相互电绝缘；以及
一个或若干个肖特基接头，形成在两个沟槽的最外面侧壁之间；
至少一个所述肖特基接头停用，通过用掺杂物选择性地掺杂半导体材料，防止形成肖特基二极管。
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