CN104900693B - 非平面锗量子阱装置 - Google Patents

非平面锗量子阱装置 Download PDF

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CN104900693B
CN104900693B CN201510197870.7A CN201510197870A CN104900693B CN 104900693 B CN104900693 B CN 104900693B CN 201510197870 A CN201510197870 A CN 201510197870A CN 104900693 B CN104900693 B CN 104900693B
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layer
germanium
fin structure
silicon
quantum well
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CN104900693A (zh
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R.皮拉里塞蒂
J.T.卡瓦列罗斯
W.雷奇马迪
U.沙
B.楚-孔
M.拉多沙夫耶维奇
N.穆克赫吉
G.德维
B.Y.金
R.S.乔
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Intel Corp
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Abstract

本申请涉及“非平面锗量子阱装置”。公开用于形成非平面锗量子阱结构的技术。具体来说，量子阱结构能够采用IV或III‑V族半导体材料来实现，并且包括锗鳍式结构。在一个示例情况下，提供一种非平面量子阱装置，该装置包括具有衬底(例如硅上的SiGe或GaAs缓冲部分)、IV或III‑V材料势垒层(例如SiGe或GaAs或AlGaAs)、掺杂层(例如δ掺杂/调制掺杂)和未掺杂锗量子阱层的量子阱结构。未掺杂锗鳍式结构在量子阱结构中形成，并且顶部势垒层在鳍式结构之上沉积。栅金属能够跨鳍式结构来沉积。漏区/源区能够在鳍式结构的相应端部形成。

Description

非平面锗量子阱装置
本分案申请的母案申请日为2010年11月18日、申请号为 201080059031.4、发明名称为“非平面锗量子阱装置”。
技术领域
本申请涉及非平面锗量子阱装置。
背景技术
在外延生长的半导体异质结构中、通常在III-V或硅锗/锗(SiGe/Ge)材料系统中形成的量子阱晶体管装置因低有效质量连同因δ掺杂引起的已降低杂质散射而在晶体管沟道中提供异常高的载流子迁移率。另外，这些装置提供异常高的驱动电流性能。但是，由于量子阱晶体管在外延生长的异质结构中形成，所以所产生的结构由若干垂直外延层组成，从而仅允许形成平面类型的量子阱装置。
发明内容
根据第一实施例，本发明提供了一种非平面半导体器件，其包括：
硅衬底；
量子阱结构，在所述硅衬底上，包括：
硅锗势垒层，其在所述硅衬底上；
所述硅锗势垒层之上或之内的区域，所述区域包含p型或n型掺杂剂；
未掺杂的锗层，其在包含所述p型或n型掺杂剂的所述区域上，其中所述锗层的至少一部分包括锗鳍式结构，其具有顶表面和横向相对的侧壁表面；以及
硅覆盖层，其在所述锗鳍式结构的至少一部分上，其中所述硅覆盖层覆盖所述锗鳍式结构的顶表面和侧壁表面；
栅电介质，其在所述硅覆盖层上，所述栅电介质在覆盖所述锗鳍式结构的顶表面的硅覆盖层的部分的顶上并且邻近覆盖所述锗鳍式结构的侧壁表面的硅覆盖层的部分；以及
栅电极，其在所述栅电介质上。
根据第二实施例，本发明提供了一种非平面半导体器件，其包括：
硅衬底；
量子阱结构，在所述硅衬底上，包括：
硅锗势垒层，其在所述硅衬底上；
所述硅锗势垒层之上或之内的区域，所述区域包含p型或n型掺杂剂；
未掺杂的锗层，其在包含所述p型或n型掺杂剂的所述区域上，其中所述锗层的至少一部分包括锗鳍式结构，其具有顶表面和横向相对的侧壁表面；以及
硅覆盖层，其在所述锗鳍式结构的至少一部分上，其中所述硅覆盖层覆盖所述锗鳍式结构的顶表面和侧壁表面；
栅电介质，其包括二氧化铪并且在所述硅覆盖层上，所述栅电介质在覆盖所述锗鳍式结构的顶表面的硅覆盖层的部分的顶上并且邻近覆盖所述锗鳍式结构的侧壁表面的硅覆盖层的部分；
栅电极，其包括在所述栅电介质上的钛；以及
在所述锗鳍式结构的相应位置处的漏区和源区。
根据第三实施例，本发明提供了一种非平面半导体器件，其包括：
硅衬底；
量子阱结构，在所述硅衬底上，包括：
硅锗势垒层，其在所述硅衬底上；
所述硅锗势垒层之上或之内的区域，所述区域包含p型或n型掺杂剂；
未掺杂的锗层，其在包含p型或n型掺杂剂的所述区域上，其中所述锗层的至少一部分包括锗鳍式结构，其具有顶表面和横向相对的侧壁表面；
硅覆盖层，其在所述锗鳍式结构的至少一部分上，其中所述硅覆盖层覆盖所述锗鳍式结构的顶表面和侧壁表面；
栅电介质，其包括二氧化铪并且在所述硅覆盖层上，所述栅电介质在覆盖所述锗鳍式结构的顶表面的硅覆盖层的部分的顶上并且邻近覆盖所述锗鳍式结构的侧壁表面的硅覆盖层的部分；
栅电极，其包括在所述栅电介质上的钛；
在所述锗鳍式结构的相应位置处的漏区和源区；以及
所述锗鳍式结构附近的浅沟槽隔离(STI)中的介电材料；
其中所述硅锗势垒层和硅覆盖层中的每个配置有比其之间的锗层更高的带隙。
根据第四实施例，本发明提供了一种微电子装置，其包括上述非平面半导体器件，其中所述微电子装置是中央处理器（CPU）、存储器阵列、芯片上高速缓存或逻辑门。
附图说明
图1示出按照本发明的一个实施例、能够用于产生非平面锗量子阱装置的示例量子阱生长结构的截面侧视图。
图2示出按照本发明的一个实施例、从图1的量子阱生长结构中去除盖层(cappinglayer)。
图3示出按照本发明的一个实施例、图2的量子阱生长结构上硬掩模的沉积和形成图案。
图4示出按照本发明的一个实施例、在图3的量子阱生长结构上形成锗鳍式结构的浅沟槽隔离(STI)蚀刻。
图5示出按照本发明的一个实施例、在图4的量子阱生长结构的锗鳍式结构周围介电材料的沉积和平面化。
图6示出按照本发明的一个实施例、使图5的量子阱生长结构的STI介电材料凹进的蚀刻。
图7示出按照本发明的一个实施例、图6的量子阱生长结构的锗鳍式结构上的栅电极形成。
图8示出按照本发明的一个实施例所配置的、图7所示的装置的透视图。
图9示出按照本发明的一个实施例、用于形成基于锗鳍(fin)的调制掺杂量子阱结构的方法。
具体实施方式
公开用于形成非平面锗量子阱结构的技术。具体来说，该量子阱结构能够采用IV或III-V族半导体材料来实现，并且包括锗鳍式结构，以使得有效地提供混合结构。这些技术例如能够用于改进调制掺杂/δ掺杂非平面装置中的短沟道效应和栅极长度(Lg)可缩放性。实现基于鳍的装置的静电益处，而同时保留调制/δ掺杂装置的高迁移率益处。
一般概述
如前面所述，在外延生长的半导体异质结构中、通常在III-V材料系统中形成的量子阱晶体管装置因低有效质量连同因调制δ掺杂引起的已降低杂质散射而在晶体管沟道中提供极高的载流子迁移率。这些常规装置提供异常高的驱动电流性能。这类量子阱系统通常采用平面架构来制造。
非平面晶体管架构、例如FinFET结构(例如双栅结构、三栅结构和环绕栅结构)能够用于改进静电效应和短沟道效应，并且因此实现Lg可缩放性。但是，这类非平面架构一般被认为与外延生长的异质结构中形成的高质量、高迁移率、掺杂量子阱晶体管不兼容。
因此，并且按照本发明的一个实施例，提供一种调制掺杂非平面Ge量子阱晶体管装置。该装置可由诸如Ge、SiGe、Si和/或砷化镓(GaAs)、或砷化铝(AlAs)之类的半导体异质结构来形成。采用IV或III-V族材料所制造的任何数量的外延生长的异质结构能够配置有基于锗鳍的沟道。该装置可包括例如调制掺杂较低带隙材料的、较大带隙材料中的δ掺杂。较低带隙材料在较大带隙材料和δ掺杂之后外延生长。该异质结构能够被形成图案并且蚀刻为一个或多个窄鳍，并且那些鳍中的δ掺杂/调制掺杂的较低带隙材料形成装置的有源主体。
用于制造该装置的工艺流程能够例如按照与制造常规的硅基非平面装置中使用的相似方式来实现，包括浅沟槽隔离(STI)、栅叠层、源区/漏区和触点形成。但是，与在装置的有源主体中包含高掺杂等级的常规非平面装置相反，锗鳍式结构的有源主体没有包含掺杂剂(因为该装置经过调制/δ掺杂)，这因改进的库仑散射而提供对载流子迁移率的显著增强。
非平面未掺杂基于Ge鳍的装置一般而言相对于半导体异质结构中形成的常规调制掺杂平面量子阱装置呈现改进的装置静电，包括显著Lg和阈值电压(Vt)可缩放性。根据本公开，其它优点将是显而易见的。例如，按照本发明的一个实施例所配置的III-V/Ge混合系统的一个优点在于，III-V材料(在势垒层中)与Ge(在鳍式结构中)之间的蚀刻选择性可用于浅沟槽隔离(STI)工艺，其中仅对Ge/III-V界面进行STI蚀刻。
因此，在给定预期Ge量子阱结构的情况下，鳍式结构(连同栅区、源区和漏区以及触点等一起)能够按照本发明的一个实施例来形成。因此，按照一个示例实施例，调制掺杂非平面Ge量子阱晶体管装置的形成一般而言可包括在Ge鳍式结构的形成之前基础量子阱结构(或者其任何部分)的生长。一个备选实施例假定量子阱结构提前预先形成，并且Ge鳍式结构随后在其中形成。
量子阱结构
图1示出按照本发明的一个实施例、能够用于产生非平面锗量子阱装置的示例Ge量子阱生长结构的截面侧视图。量子阱生长结构能够是例如具有盖层的常规SiGe/Ge或GaAs/Ge量子阱结构。但是，如前面所述，要注意，按照本发明的一个实施例所形成的调制/δ掺杂非平面Ge量子阱晶体管装置能够采用配置有各种IV或III-V材料、掺杂层和缓冲层的、任何数量的量子阱生长结构来实现，这根据本公开将是显而易见的。要求保护的本发明并不是要局限于任何特定量子阱生长配置。
在图1中能够看到，量子阱生长结构包括衬底，衬底上形成核化和缓冲层。该结构还包括IV或III-V族材料势垒层，势垒层上形成掺杂层，在掺杂层上形成分隔层，在分隔层上形成Ge量子阱层。盖层设置在Ge量子阱层上。将依次论述这些示例层中的每个层。其它实施例可包括更少层(例如更少缓冲层和/或没有盖层)或更多层(例如量子阱层之下的附加分隔和/或掺杂层)或者不同层(例如采用不同半导体材料、配方和/或掺杂剂来形成)。这些层可采用任何适当的层厚度和其它预期层参数、使用已建立的半导体工艺(例如金属有机化学气相沉积、分子束外延、光刻或其它这类适当工艺)来实现，并且可渐变(例如按照线性或步进方式)以改进原本晶格相异材料的相邻层之间的晶格常数匹配。一般来说，该结构的特定层和尺寸将取决于诸如预期装置性能、制造能力以及所使用的半导体材料之类的因素。
该衬底可按典型情况下所做的那样来实现，并且在这里能够使用任何数量的适当衬底类型和材料(例如p型、n型、中性型、硅、锗、高或低电阻率、不标准尺寸(off-cut)或者非不标准尺寸、块体、绝缘体上硅等)。在一个示例实施例中，该衬底是块体Si衬底。在另一个示例实施例中，该衬底是块体Ge衬底。其它实施例可使用绝缘体上半导体配置，例如绝缘体上硅(SOI)或绝缘体上锗(GeOI)或绝缘体上SiGe(SiGeOI)。
核化和缓冲层在衬底上形成，并且也可按典型情况下所做的那样来实现。在一个具体示例实施例中，核化和缓冲层由SiGe(例如60%的Ge)或GaAs来制成，并且总厚度为大约0.5 μm至2.0 μm(例如大约25 nm至50 nm厚的核化层以及大约0.3 μm至1.9 μm厚的缓冲层)。大家知道，核化和缓冲层能够用于填充具有例如III-V材料、诸如GaAs材料的原子双层的最低衬底阶地(substrate terrace)。核化层能够用于创建反相无领域虚拟极衬底(anti-phase domain-free virtual polar substrate)，并且缓冲层可用于提供位错滤波缓冲部分，位错滤波缓冲部分能够提供量子阱结构的压缩应变和/或对衬底与势垒层之间的晶格失配的控制。缓冲层还可包括渐变缓冲部分，渐变缓冲部分也能够按常规上所做的那样来实现。大家知道，通过形成渐变缓冲层，位错可沿其中的相对对角平面滑动，以使得有效控制衬底与IV/III-V材料势垒层(和/或任何中间层)之间的晶格失配。将会显而易见，这类渐变层能够用于量子阱结构或叠层的其它位置或量子阱结构或叠层内的其它位置。注意，能够获益于本发明的一个实施例的其它量子阱结构可在没有核化和/或缓冲层的情况下实现。例如，具有采用具有充分相似晶格常数的材料来实现的衬底和势垒层的实施例可在没有渐变缓冲部分的情况下实现。
在这个示例实施例中，IV/III-V势垒层在核化和缓冲层上形成，并且也能够按常规上所做的那样来实现。在一个具体示例实施例中，势垒层采用Si1-xGex(其中x在40至80的范围之内，例如60)或GaAs或Al1-xGaxAs(其中x在50至90的范围之内，例如70)来实现，并且厚度在4 nm至120 nm的范围之内(例如100 nm，+/-20 nm)。一般来说，势垒层由其带隙比形成覆盖量子阱层的材料的带隙要高的材料来形成，并且具有充分厚度以对晶体管沟道中的电荷载流子提供电位势垒。将会理解，势垒层的实际构成和厚度将取决于诸如衬底和量子阱层材料和/或厚度之类的因素。在这里能够使用许多这类势垒材料和配置，这是根据本公开将会理解的。
在这个示例量子阱生长结构中，掺杂层在势垒层上(或之内)形成，并且也能够按常规所做的那样来实现。一般来说，能够通过掺杂层来掺杂势垒层，以便向量子阱层提供载流子。掺杂层能够是例如δ掺杂的(或调制掺杂的)。对于利用SiGe材料势垒层的n型装置，该掺杂可例如使用硼和/或碲杂质来实现，而对于p型装置，该掺杂层可例如使用铍(Be)和/或碳来实现。掺杂层的厚度将取决于诸如掺杂的类型以及所使用的材料之类的因素。例如，在一个示例实施例中，掺杂层是厚度在大约3 至15之间的硼δ掺杂Si40Ge60的层。在另一个实施例中，掺杂层是厚度在大约15至60之间的Be调制掺杂GaAs的层。该掺杂能够例如基于在Ge量子阱层的沟道中有用的表面载流子浓度来选择。根据本公开将会理解，本发明的一个实施例可采用具有一个或多个任何类型适当掺杂层的量子阱结构来实现。
分隔层在掺杂层上(或之上)形成，并且也能够按常规所做的那样来实现。在一个具体示例实施例中，分隔层采用Si1-xGex(其中x在40至80的范围之内，例如60)或GaAs或Al1-xGaxAs(其中x在50至90的范围之内，例如70)来实现，并且厚度在0.2 nm至70 nm的范围之内(例如5 nm)。一般来说，分隔层能够配置成向量子阱层提供压缩应变(在它充当半导电沟道时)。注意，能够获益于本发明的一个实施例的其它量子阱结构可在没有分隔层的情况下实现。
量子阱层也能够按常规所做的那样来实现。一般来说，量子阱层采用示例厚度大约为20至500的未掺杂锗来实现。在这里能够使用许多其它量子阱层配置，这是将会理解的。在更一般的意义上，量子阱层具有比IV/III-V势垒层的带隙更小的带隙，是未掺杂的，并且具有充分厚度以便为给定应用、例如存储器单元或逻辑电路的晶体管提供足够的沟道电导。可由势垒层、上势垒层或者两者引起量子阱层的应变。
在如前面所述通过量子阱层来形成一般包括衬底的装置叠层之后，盖层能够在量子阱层之上形成。在一个具体示例实施例中，盖层采用SiGe或Si来实现，并且厚度在2 nm至10 nm的范围之内(例如6 nm)。将会理解，其它适当盖层材料可用于保护基础锗量子阱层。
基于Ge鳍且调制掺杂的量子阱装置
图2至图8以截面和透视图来示出按照本发明的一个实施例所配置的基于Ge鳍的量子阱结构的形成。将会理解，基于鳍的结构能够在图1所示的装置叠层或者具有未掺杂Ge沟道的任何数量的其它调制/δ掺杂量子阱生长结构上形成。注意，中间处理、例如平面化(例如化学机械抛光或CMP)和后续清洁工艺可包含在整个形成工艺中，即使这种处理可能没有明确论述也是如此。
图2示出按照本发明的一个实施例、从图1的量子阱生长结构中去除盖层。在一个这种实施例中，盖层是SiGe(例如60%的Ge)或Si。在任何情况下，能够例如通过蚀刻(湿式蚀刻和/或干式蚀刻)去除盖层，以暴露基础Ge量子阱层。
图3示出按照本发明的一个实施例、图2的量子阱生长结构上硬掩模的沉积和形成图案。用于浅沟道隔离(STI)形成的这种形成图案能够使用标准光刻来执行，包括硬掩模材料(例如，诸如二氧化硅、氮化硅和/或其它适当的硬掩模材料)的沉积、在硬掩模的将暂时保留以保护基础鳍式结构(本例中为Ge沟道)的一部分上对抗蚀剂形成图案、蚀刻以去除硬掩模的未遮蔽(无抗蚀剂)部分(例如使用干式蚀刻或者其它适当的硬掩模去除工艺)以及然后剥离形成图案的抗蚀剂。在图3所示的示例实施例中，所产生的硬掩模是装置叠层的中心并且在一个位置中形成，但是在其它实施例中，硬掩模可偏移到叠层的一侧和/或位于叠层上的多个地方，这取决于特定有源装置。
图4示出按照本发明的一个实施例、在图3的量子阱生长结构上形成锗鳍式结构的浅沟槽隔离(STI)蚀刻，以及图5示出按照本发明的一个实施例的锗鳍式结构周围的介电材料的沉积和平面化。这也能够使用标准光刻来执行，包括用于去除叠层的没有受到硬掩模保护的部分的蚀刻(例如湿式蚀刻或干式蚀刻)以及介电材料(例如，诸如SiO2或其它适当的介电材料)的沉积。STI蚀刻的深度可以改变，但在一些示例实施例中是在Ge量子阱层的底部之下0至5000的范围之内。在这个示例实施例中，蚀刻深度几乎到达势垒层的底部。一般来说，该蚀刻应当到达允许量子阱沟道(例如与相邻组件或其它电位干扰源)电隔离的充分深度。在形成STI和沉积介电材料之后，沉积的介电材料能够经过抛光/平面化(例如使用CMP)。注意，硬掩模能够保留，以便保护锗沟道。
图6示出按照本发明的一个实施例、使图5的量子阱生长结构的STI介电材料凹进(recess)的蚀刻。这也能够使用标准光刻来执行，包括用于去除介电材料的蚀刻(例如使用湿式蚀刻，但是也可使用干式蚀刻)。凹进蚀刻的深度可以改变，但是一般而言在锗量子阱层(沟道)的底部与掺杂层的上方之间。能够看到，在这个示例实施例中，凹进蚀刻深度到达锗量子阱层(沟道)的底部。注意，硬掩模仍然在适当位置，以便保护Ge鳍式结构(或沟道)。
图7示出按照本发明的一个实施例、图6的量子阱生长结构的锗鳍式结构上的栅电极形成。图8的透视图所示的所产生结构实际上是配置为FinFET装置的Ge量子阱结构(因此是非平面的)。大家知道，FinFET是在半导体材料的细带(一般称作鳍)周围构建的晶体管。FinFET装置包括标准场效应晶体管(FET)结点，包括栅极、栅电介质(通常为高k)、源区和漏区(图8中仅概括性地示出源区/漏区之一)。装置的导电沟道驻留在栅电介质下面的鳍的外侧。具体来说，电流沿鳍的两个侧壁(与衬底表面垂直的侧面)以及沿鳍的顶部(与衬底表面并行的侧面)流动。由于这类配置的导电沟道基本上沿鳍的三个不同外部平面区域存在，所以这种FinFET设计有时称作三栅FinFET。其它类型的FinFET配置也是可用的，例如所谓的双栅FinFET，其中导电沟道主要仅沿鳍的两个侧壁(而没有沿鳍的顶部)存在。
在图7中能够看到，去除硬掩模(例如湿式蚀刻或干式蚀刻)，并且顶部势垒沉积在未借助掺杂层掺杂的Ge沟道之上。这个顶部势垒能够是例如沉积的层Si/SiGe。顶部势垒层的厚度能够是例如10至100(例如50)。一般来说，顶部势垒层能够由其带隙比形成基础量子阱沟道的Ge材料的带隙要高的任何适当材料来形成，并且具有充分厚度以对晶体管沟道中的电荷载流子提供电位势垒。沉积在顶部势垒上的高k栅电介质能够是例如厚度在10至50(例如20)的范围之内的膜，并且能够例如采用氧化铪、矾土、五氧化二钽、氧化锆、铝酸镧、钪酸钆、氧化铪硅、氧化镧、氧化镧铝、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌或者介电常数比例如二氧化硅的介电常数要大的其它这类材料来实现。沉积在高k栅电介质之上的栅金属能够是例如镍、金、铂、铝、钛、钯、钛镍或其它适当栅金属或合金。能够按照对于FinFET结构常规所做的那样来形成源区和漏区，并且源区和漏区可配置有与栅极相同的金属或其它适当触点金属。根据本公开将会理解，顶部势垒、高k栅电介质、栅金属和源/漏区能够使用标准FinFET处理来实现。
因此，本文所提供的技术在非平面架构的上下文中采用通常用于制造平面量子阱叠层的调制掺杂技术来提供具有未掺杂Ge沟道的FinFET装置。该装置能够使用诸如SiGe、GaAs或AlGaAs之类的若干适当IV/III-V材料来实现。所示的所产生集成电路装置能够用作可安装在诸如中央处理器、存储器阵列、芯片上高速缓存或逻辑门之类的多种微电子装置的任一个中的晶体管。同样，许多系统级应用能够采用本文所述的集成电路。
方法
图9示出按照本发明的一个实施例、用于形成基于锗鳍的调制/δ掺杂量子阱结构的方法。量子阱结构能够根据需要来配置，并且一般包括如下叠层，该叠层包括衬底、IV/III-V势垒层、掺杂层(调制/δ掺杂)和量子阱层。
该方法包括去除901量子阱结构的盖层(若适用的话)，以便暴露基础Ge量子阱结构。能够例如使用湿式蚀刻或干式蚀刻去除盖层。该方法继续进行对硬掩模形成图案903，用于浅沟槽隔离(STI)形成图案。形成图案可包括例如沉积硬掩模材料，在硬掩模的将暂时保留以便在STI蚀刻期间保护装置的基础鳍式结构的一部分上对抗蚀剂形成图案，蚀刻以去除硬掩模的未遮蔽(无抗蚀剂)部分(例如使用干式蚀刻或其它适当硬掩模去除工艺)，以及然后剥离形成图案的抗蚀剂，以便提供形成图案的STI硬掩模。
该方法继续进行将STI蚀刻905到Ge量子阱结构中，由此形成鳍式结构。在一个示例情况下，并且如前面所述，沟槽形成能够使用一个或多个干式蚀刻和/或湿式蚀刻来执行。该方法继续进行将介电材料沉积907到STI中，并且平面化介电材料。该方法继续进行蚀刻909以便使STI材料凹进(例如向下至Ge量子阱层的底部，而在掺杂层之前)。蚀刻能够例如采用湿式蚀刻来实现。
该方法继续进行在鳍式结构之上沉积911顶部势垒和可选高k栅电介质。如前面所述，顶部势垒能够由其带隙比形成基础量子阱沟道的Ge材料的带隙要高的任何适当材料(例如Si/SiGe)来形成，并且具有充分厚度以对晶体管沟道中的电荷载流子提供电位势垒。高k栅电介质能够是例如具有充分隔离金属栅的适当厚度并且介电常数比例如二氧化硅的介电常数要高的膜。在这里也能够使用其它适当栅电介质，并且在顶部势垒靠自己来提供充分隔离的一些实施例中，可以不需要栅电介质。该方法继续进行在顶部势垒之上并且跨形成装置沟道的隔离Ge鳍式结构来沉积913栅金属，以及在鳍式结构(沟道)的相应端部形成915漏区和源区。栅金属和源/漏区能够使用标准处理(沉积、遮蔽、蚀刻、平面化等)来实现。
因此，提供配置有未掺杂锗沟道的非平面调制/δ掺杂量子阱结构。该结构能够例如用作适合用于许多应用(例如处理器、存储器等)的FinFET装置(例如双栅FinFET或三栅FinFET)。
按照本公开，许多实施例和配置将是显而易见的。例如，本发明的一个示例实施例提供一种用于形成非平面量子阱结构的方法。该方法包括接收具有衬底、IV或III-V材料势垒层、掺杂层和未掺杂锗量子阱层的量子阱结构。该方法还包括有选择地蚀刻量子阱结构以形成锗鳍式结构，在鳍式结构之上沉积顶部势垒层，以及跨鳍式结构来沉积栅金属。在一个特定情况下，有选择地蚀刻量子阱结构包括在量子阱结构上对硬掩模形成图案用于浅沟槽隔离(STI)形成图案，将STI蚀刻到量子阱结构中，将介电材料沉积到STI中，以及平面化介电材料。在一个这种情况下，STI中的介电材料向下凹进到锗量子阱层的底部。该方法可包括在鳍式结构的相应端部形成漏区和源区。该方法可包括去除量子阱结构的盖层，以便暴露锗量子阱结构。在另一个特定情况下，在鳍式结构之上沉积顶部势垒层之后但在跨鳍式结构沉积栅金属之前，该方法还包括在顶部势垒层之上沉积高k栅介电层。量子阱结构能够是例如外延生长的异质结构。掺杂层可包括例如对未掺杂锗量子阱层进行调制掺杂的δ掺杂。在另一个特定情况下，未掺杂锗量子阱层能够在掺杂层之后外延生长。
本发明的另一个示例实施例提供一种非平面量子阱装置。该装置包括具有衬底、IV或III-V材料势垒层、掺杂层和未掺杂锗量子阱层的量子阱结构。该装置还包括在量子阱结构中形成的未掺杂锗鳍式结构、沉积在鳍式结构之上的顶部势垒层以及跨鳍式结构沉积的栅金属。该装置可包括例如鳍式结构附近的浅沟槽隔离(STI)中的凹进介电材料。在一个这种情况下，STI中的介电材料向下凹进到锗量子阱层的底部。该装置可包括在鳍式结构的相应端部所形成的漏区和源区。该装置可包括在顶部势垒层与栅金属之间沉积的高k栅电介质。在一个示例情况下，非平面量子阱结构包括FinFET装置。在另一个示例情况下，IV或III-V材料势垒层采用硅锗或砷化镓或砷化铝镓来实现，并且衬底包括硅上的硅锗或砷化镓缓冲部分。在另一个示例情况下，量子阱结构是外延生长的异质结构。在另一个示例情况下，掺杂层包括对未掺杂锗量子阱层进行调制掺杂的δ掺杂。在另一个示例情况下，未掺杂锗量子阱层在掺杂层(在势垒层上或之内)之后外延生长。
本发明的另一个示例实施例提供一种非平面量子阱装置。在这个示例中，该装置包括具有衬底、IV或III-V材料势垒层、掺杂层和未掺杂锗量子阱层的量子阱结构。量子阱结构是外延生长的异质结构，其中未掺杂锗量子阱层在掺杂层之后外延生长，并且掺杂层对未掺杂锗量子阱层进行调制掺杂。该装置还包括在量子阱结构中形成的未掺杂锗鳍式结构、沉积在鳍式结构之上的顶部势垒层以及跨鳍式结构沉积的栅金属。另外，该装置包括在鳍式结构的相应端部所形成的漏区和源区以及在顶部势垒层与栅金属之间沉积的高k栅电介质。
为了便于说明和描述而提供了本发明的示例实施例的以上描述。不是意在作为详尽的描述或者将本发明局限于所公开的准确形式。根据本公开，许多修改及变更都是可能的。预计本发明的范围不受本详细描述限制，而是受到所附权利要求书限制。

Claims (20)

1.一种非平面半导体器件，其包括：
硅衬底；
量子阱结构，在所述硅衬底上，包括：
硅锗势垒层，其在所述硅衬底上；
所述硅锗势垒层之上或之内的区域，所述区域包含p型或n型掺杂剂；
未掺杂的锗层，其在包含所述p型或n型掺杂剂的所述区域上，其中所述锗层的至少一部分包括锗鳍式结构，其具有顶表面和横向相对的侧壁表面；以及
硅覆盖层，其在所述锗鳍式结构的至少一部分上，其中所述硅覆盖层覆盖所述锗鳍式结构的顶表面和侧壁表面；
栅电介质，其在所述硅覆盖层上，所述栅电介质在覆盖所述锗鳍式结构的顶表面的硅覆盖层的部分的顶上并且邻近覆盖所述锗鳍式结构的侧壁表面的硅覆盖层的部分；以及
栅电极，其在所述栅电介质上。
2.如权利要求1所述的器件，其中所述栅电介质包括二氧化铪并且所述栅电极包括钛。
3.如权利要求1所述的器件，其中所述栅电介质包括高k栅介电材料，其具有大于二氧化硅的介电常数的介电常数。
4.如权利要求1所述的器件，其进一步包括：
在所述锗鳍式结构的相应位置处的漏区和源区。
5.如权利要求1所述的器件，其进一步包括所述锗鳍式结构附近的浅沟槽隔离(STI)中的介电材料。
6.如权利要求5所述的器件，其中所述STI中的介电材料从所述锗层下面的层延伸到所述锗层的底部，并且所述硅覆盖层、栅电介质、以及栅电极中的每一个都在所述STI中的所述介电材料上。
7.如权利要求1所述的器件，其中所述锗层通过所述硅锗势垒层、所述硅覆盖层或两者而应变。
8.如权利要求1所述的器件，其中所述器件的导电沟道包括在所述栅电介质下方的锗鳍式结构的顶和侧壁表面，并且所述硅锗势垒层和硅覆盖层中的每个配置有比其之间的锗层更高的带隙来向所述导电沟道中的电荷载流子提供势垒。
9.如权利要求1所述的器件，其中包含p型或n型掺杂剂的所述区域对所述锗层调制掺杂，所述器件还包括配置成向所述锗层提供压缩应变的分隔层。
10.如权利要求1所述的器件，其中所述硅覆盖层从所述锗鳍式结构的顶表面到浅沟槽隔离材料地覆盖所述锗鳍式结构的侧壁表面。
11.如权利要求1所述的器件，其中所述器件是双栅FinFET器件的部分。
12.如权利要求1所述的器件，其中所述器件是三栅FinFET器件的部分。
13.如权利要求1所述的器件，其中所述器件是中央处理器或存储器阵列的部分。
14.一种非平面半导体器件，其包括：
硅衬底；
量子阱结构，在所述硅衬底上，包括：
硅锗势垒层，其在所述硅衬底上；
所述硅锗势垒层之上或之内的区域，所述区域包含p型或n型掺杂剂；
未掺杂的锗层，其在包含所述p型或n型掺杂剂的所述区域上，其中所述锗层的至少一部分包括锗鳍式结构，其具有顶表面和横向相对的侧壁表面；以及
硅覆盖层，其在所述锗鳍式结构的至少一部分上，其中所述硅覆盖层覆盖所述锗鳍式结构的顶表面和侧壁表面；
栅电介质，其包括二氧化铪并且在所述硅覆盖层上，所述栅电介质在覆盖所述锗鳍式结构的顶表面的硅覆盖层的部分的顶上并且邻近覆盖所述锗鳍式结构的侧壁表面的硅覆盖层的部分；
栅电极，其包括在所述栅电介质上的钛；以及
在所述锗鳍式结构的相应位置处的漏区和源区。
15.如权利要求14所述的器件，其进一步包括所述锗鳍式结构附近的浅沟槽隔离(STI)中的介电材料，其中所述STI中的介电材料从所述锗层下面的层延伸到所述锗层的底部，并且所述硅覆盖层、栅电介质、以及栅电极中的每一个都在所述STI中的介电材料上。
16.如权利要求14所述的器件，其中所述器件的导电沟道包括在所述栅电介质下方的锗鳍式结构的顶和侧壁表面，并且所述硅锗势垒层和硅覆盖层中的每个配置有比其之间的锗层更高的带隙，并且所述硅覆盖层从所述锗鳍式结构的顶表面到浅沟槽隔离材料地覆盖所述锗鳍式结构的侧壁表面。
17.一种集成电路，其包括如权利要求14所述的器件，其中所述集成电路包括中央处理器（CPU）、存储器阵列、芯片上高速缓存、逻辑门或其组合。
18.一种非平面半导体器件，其包括：
硅衬底；
量子阱结构，在所述硅衬底上，包括：
硅锗势垒层，其在所述硅衬底上；
所述硅锗势垒层之上或之内的区域，所述区域包含p型或n型掺杂剂；
未掺杂的锗层，其在包含p型或n型掺杂剂的所述区域上，其中所述锗层的至少一部分包括锗鳍式结构，其具有顶表面和横向相对的侧壁表面；
硅覆盖层，其在所述锗鳍式结构的至少一部分上，其中所述硅覆盖层覆盖所述锗鳍式结构的顶表面和侧壁表面；
栅电介质，其包括二氧化铪并且在所述硅覆盖层上，所述栅电介质在覆盖所述锗鳍式结构的顶表面的硅覆盖层的部分的顶上并且邻近覆盖所述锗鳍式结构的侧壁表面的硅覆盖层的部分；
栅电极，其包括在所述栅电介质上的钛；
在所述锗鳍式结构的相应位置处的漏区和源区；以及
所述锗鳍式结构附近的浅沟槽隔离(STI)中的介电材料；
其中所述硅锗势垒层和硅覆盖层中的每个配置有比其之间的锗层更高的带隙。
19.如权利要求18所述的器件，其中所述硅覆盖层从所述锗鳍式结构的顶表面到STI中的介电材料的顶部地覆盖所述锗鳍式结构的侧壁表面。
20.一种微电子装置，其包括如权利要求18所述的器件，其中所述微电子装置是中央处理器（CPU）、存储器阵列、芯片上高速缓存或逻辑门。
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