CN103594512B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103594512B
CN103594512B CN201210293347.0A CN201210293347A CN103594512B CN 103594512 B CN103594512 B CN 103594512B CN 201210293347 A CN201210293347 A CN 201210293347A CN 103594512 B CN103594512 B CN 103594512B
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CN103594512A (zh
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马小龙
殷华湘
许淼
朱慧珑
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体器件制造方法，包括：在衬底上形成多个鳍片，其中鳍片沿第一方向延伸并且具有类菱形截面；在每个鳍片上形成栅极堆叠结构，栅极堆叠结构横跨多个鳍片并且沿第二方向延伸；其中，每个鳍片中位于栅极堆叠结构下方的部分构成器件的沟道区，每个鳍片中位于栅极堆叠结构沿第一方向的两侧的部分构成源漏区。依照本发明的半导体器件及其制造方法，采用类菱形鳍片提高了栅控能力以有效抑制短沟道效应，此外利用外延量子阱更好地限制载流子、提高了器件驱动能力。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体集成电路制造领域，更具体地，涉及一种具有、类菱形鳍片以及量子阱的FinFET及其制造方法。
背景技术
随着半导体器件的尺寸持续等比例缩小，出现了阈值电压随沟道长度减小而下降的问题，也即在半导体器件中产生了短沟道效应。为了抑制这种短沟道效应，业界采用了鳍片场效应晶体管(FinFET)的新结构，也即在SOI衬底的顶部薄硅层中形成多个相互平行的垂直于衬底的硅鳍片(Fin)，在这些硅Fin中部形成沟道区、以及在两端形成源漏区，而控制栅极则横跨这些多个硅Fin分布。
然而，现有技术的硅Fin由于刻蚀制造工艺限制，其截面均为矩形，相应地控制栅极也与之共型，因此表面积/体积比较小，栅极控制能力较弱，对于沟道持续缩减的器件而言，抑制短沟道效应能力有限。
此外，器件尺寸缩减之后，载流子疏运问题也相应突出，如何能够有效限制载流子、提高载流子迁移率，成为制约器件驱动能力提高的重要问题。
发明内容
有鉴于此，本发明的目的在于提供一种具有、类菱形鳍片以及量子阱的FinFET及其制造方法，克服上述缺陷，有效抑制短沟道效应并且提高器件沟道区载流子迁移率，从而改善器件整体性能。
实现本发明的上述目的，是通过提供一种半导体器件，包括：衬底上的多个鳍片，鳍片沿第一方向延伸，并且具有类菱形截面；栅极堆叠结构，横跨每个鳍片，沿第二方向延伸；沟道区，位于每个鳍片中栅极堆叠结构下方；源漏区，位于每个鳍片中栅极堆叠结构两侧。
其中，鳍片与栅极堆叠结构之间还包括量子阱层。
其中，量子阱层包括SiGe合金。
其中，栅极堆叠结构包括高k材料的栅极绝缘层和金属材料的栅极导电层。
其中，每个鳍片上栅极堆叠结构两侧还包括抬升源漏区。
其中，衬底为SOI，鳍片包括Si。
本发明还提供了一种半导体器件制造方法，包括：在衬底上形成多个鳍片，其中鳍片沿第一方向延伸并且具有类菱形截面；在每个鳍片上形成栅极堆叠结构，栅极堆叠结构横跨多个鳍片并且沿第二方向延伸；其中，每个鳍片中位于栅极堆叠结构下方的部分构成器件的沟道区，每个鳍片中位于栅极堆叠结构沿第一方向的两侧的部分构成源漏区。
其中，形成多个鳍片的步骤进一步包括：在衬底上形成多个鳍片，其中鳍片沿第一方向延伸并且具有矩形截面；在每个鳍片上形成外延层；刻蚀外延层和鳍片，形成具有类菱形截面的鳍片。
其中，采用KOH或TMAH湿法腐蚀鳍片。
其中，类菱形截面的鳍片的中部宽度大于底部宽度，顶部为锐角。
其中，形成具有类菱形截面的鳍片之后、形成栅极堆叠结构之前，还包括在鳍片上形成量子阱层。
其中，量子阱层包括SiGe合金。
其中，栅极堆叠结构包括高k材料的栅极绝缘层以及金属材料的栅极导电层。
其中，形成栅极堆叠结构之后，还包括：在栅极堆叠结构两侧形成栅极侧墙和抬升源漏区。
其中，衬底为SOI，鳍片包括Si。
其中，形成具有类菱形截面的鳍片之后，进一步对鳍片的角部进行圆润化处理。
依照本发明的半导体器件及其制造方法，采用类菱形鳍片提高了栅控能力以有效抑制短沟道效应，此外利用外延量子阱更好地限制载流子、提高了器件驱动能力。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1为根据本发明的半导体器件的顶视图；以及
图2至图9为根据本发明的半导体器件制造方法各步骤的剖视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
首先参照图1，说明了根据本发明的半导体器件的顶视图。
如图1所示，半导体器件包括在SOI衬底上的多个鳍片1，鳍片1沿平行于衬底平面的第一方向延伸并且彼此之间相互平行。多个鳍片1的中部构成器件的沟道区1C(虚线框所示)，多个鳍片的两端构成器件的源区1S或者漏区1D，在鳍片的两端分别具有抬升源区(或者源区接触)1RS和抬升漏区(或者漏区接触)1RD。栅极2与多个鳍片1相交，沿平行于衬底平面的第二方向延伸，其中第二方向优选地与第一方向垂直。栅极2沿第二方向在多个鳍片1之外的两端具有栅极连接2C。在后续附图中，某附图A代表器件沿图1中第二方向的AA’的剖面示意图(仅示出了单条鳍片)，某附图B代表器件沿图1中第一方向的BB’的剖面示意图(示出了图A对应的该条鳍片)。
参照图2A以及图2B，在衬底10上形成多个硅鳍片。衬底10优选地是SOI晶片，或者是在硅晶片上形成了氧化层以及顶部薄Si的复合衬底。光刻/刻蚀衬底10直至暴露SOI晶片的埋氧层或者复合衬底中部的氧化层，形成了相互平行沿第一方向延伸的多个鳍片11。其中鳍片11通常具有矩形截面，鳍片11也垂直于衬底表面分布。鳍片11与衬底10中顶部半导体材料是一致的，也即是Si。此外，也可以采用刻蚀之外的其他纳米线形成工艺，形成鳍片11。鳍片11高度例如是10～200nm，沿第二方向的宽度例如是5～50nm，沿第一方向的宽度例如是500～2000nm。
参照图3A以及图3B，在鳍片11上(也即顶部以及侧壁上)外延生长形成外延层12。外延层12与鳍片11材质相同，也相应地也沿第一方向延伸。由于鳍片11下部相接的是衬底10的绝缘氧化物表面，因此外延生长时在底部生长缓慢或者基本不生长，而在顶部生长较快。此外，在(111)面上生长较慢。因此，最终形成的外延层12通常具有类似于菱形的截面。
参照图4A以及图4B，刻蚀外延层12和鳍片11，形成类菱形鳍片13，也沿第一方向延伸。对于Si鳍片而言，可以采用KOH、TMAH等各向异性的腐蚀液，依次刻蚀外延层12和鳍片11。由于(111)晶面上刻蚀速率较慢，因此刻蚀会停止在(111)晶面上而形成如图4A所示的类菱形鳍片13。其中，前述的所谓的类菱形，指的是顶部宽度与底部宽度(此处宽度均指的是沿第二方向上的宽度)相近(例如顶部宽度小于等于底部宽度、并且优选地顶点为锐角)、并且中部宽度大于底部宽度和/或顶部宽度的这样一种多边形。简言之，类菱形是去除了底部一部分(或者还包括去除了顶部小部分)的菱形。类菱形鳍片13的最大宽度也即中部宽度，要小于等于矩形鳍片11的第二方向上的宽度，因此鳍片13的宽度优选地例如是4～40nm。类菱形鳍片13较之传统的矩形鳍片11，提高了表面积/体积比，可以实现单位平面面积上更大的有效沟道宽度，同时具有更强的栅控能力，有效抑制短沟道效应。优选地，形成类菱形鳍片13之后，进一步采用各向同性的干法或者湿法腐蚀对鳍片13的角部(顶角、侧边夹角以及底角)进行圆润化处理，以提高器件可靠性。
参照图5A以及图5B，在类菱形鳍片13上外延生长量子阱层20，同样地沿第一方向延伸而包围类菱形鳍片13。通过MBE、ALD、PECVD等工艺，控制外延生长的压力、温度、气流量等工艺参数，使得量子阱层20均匀包裹在类菱形鳍片13的各个侧面上，并且因此也共型地具有类菱形截面。量子阱层20的材质选用晶格常数与Si相近地材料，例如SiGe合金，其中Ge含量(原子数目百分比)在40～80％之间。量子阱层20可以是SiGe的单层，也可以是Ge含量不同的多层的层叠结构。量子阱层20利用能带工程，在导电沟道下方形成具有宽带隙的半导体材料，载流子就会被限制在窄带隙的沟道材料中输运，提高载流子迁移率，从而提高器件的驱动能力。
参照图6A以及图6B，在量子阱层20上形成沿第二方向延伸的栅极堆叠层30A/30B。采用LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规沉积方法，在量子阱层20上依次沉积栅极绝缘层30A和栅极导电层30B。栅极绝缘层30A是高k材料，包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1- xTiO3(BST))。栅极导电层30B是金属、金属氮化物及其组合，其中金属包括Al、Ti、Cu、Mo、W、Ta，金属氮化物包括TiN、TaN。栅极堆叠层30A/30B同样地沿第一方向延伸而包围类菱形鳍片13以及量子阱层20。值得注意的是，栅极堆叠层如图1所示地横跨多个鳍片13，因此将沿第二方向以及AA’方向延伸。
以下图7至图9均为沿图1中BB’方向的剖视图。
参照图7，其中，沿第一方向光刻/刻蚀栅极堆叠层，直至暴露量子阱层20，而形成栅极堆叠结构。如图7所示，栅极堆叠结构30A/30B下方的量子阱层20以及鳍片13的部分构成器件的沟道区1C，(沿第一方向的)两端则分别构成器件的源区1S或者漏区1D。
参照图8，在栅极堆叠结构(沿第一方向的)两侧的量子阱层20上形成栅极侧墙40。例如是PECVD、HDPCVD、溅射等方法沉积并且随后刻蚀形成的氮化硅、氮氧化硅、类金刚石无定形碳(DLC)材质的侧墙。
最后，参照图9，在栅极侧墙40(沿第一方向的)两侧的量子阱层20上形成抬升源区1RS和抬升漏区1RD。形成方法例如是MBE、CVD等外延技术。
依照本发明的半导体器件及其制造方法，采用类菱形鳍片提高了栅控能力以有效抑制短沟道效应，此外利用外延量子阱更好地限制载流子、提高了器件驱动能力。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (14)

1.一种半导体器件，包括：
衬底上的多个鳍片，鳍片沿第一方向延伸，并且具有类菱形截面；
量子阱层，在具有类菱形截面的鳍片上，均匀包裹在类菱形鳍片的各个侧面上，并且因此也共型地具有类菱形截面；
栅极堆叠结构，横跨每个鳍片，在量子阱层上沿第二方向延伸；
沟道区，位于每个鳍片中栅极堆叠结构下方，由具有类菱形截面的鳍片的一部分构成；
源漏区，位于每个鳍片中栅极堆叠结构两侧。
2.如权利要求1的半导体器件，其中，量子阱层包括SiGe合金。
3.如权利要求1的半导体器件，其中，栅极堆叠结构包括高k材料的栅极绝缘层和金属材料的栅极导电层。
4.如权利要求1的半导体器件，其中，每个鳍片上栅极堆叠结构两侧还包括抬升源漏区。
5.如权利要求1的半导体器件，其中，衬底为SOI，鳍片包括Si。
6.一种半导体器件制造方法，包括：
在衬底上形成多个鳍片，其中鳍片沿第一方向延伸并且具有类菱形截面；
在类菱形鳍片上外延生长量子阱层，均匀包裹在类菱形鳍片的各个侧面上，并且因此也共型地具有类菱形截面；
在每个鳍片上形成栅极堆叠结构，栅极堆叠结构横跨量子阱层并且沿第二方向延伸；
其中，每个鳍片中位于栅极堆叠结构下方的具有类菱形截面的部分构成器件的沟道区，每个鳍片中位于栅极堆叠结构沿第一方向的两侧的部分构成源漏区。
7.如权利要求6的半导体器件制造方法，其中，形成多个鳍片的步骤进一步包括：
在衬底上形成多个鳍片，其中鳍片沿第一方向延伸并且具有矩形截面；
在每个鳍片上形成外延层；
刻蚀外延层和鳍片，形成具有类菱形截面的鳍片。
8.如权利要求7的半导体器件制造方法，其中，采用KOH或TMAH湿法腐蚀鳍片。
9.如权利要求6或7的半导体器件制造方法，其中，类菱形截面的鳍片的中部宽度大于底部宽度，顶部为锐角。
10.如权利要求9的半导体器件制造方法，其中，量子阱层包括SiGe合金。
11.如权利要求6的半导体器件制造方法，其中，栅极堆叠结构包括高k材料的栅极绝缘层以及金属材料的栅极导电层。
12.如权利要求6的半导体器件制造方法，其中，形成栅极堆叠结构之后，还包括：在栅极堆叠结构两侧形成栅极侧墙和抬升源漏区。
13.如权利要求6的半导体器件制造方法，其中，衬底为SOI，鳍片包括Si。
14.如权利要求6的半导体器件制造方法，其中，形成具有类菱形截面的鳍片之后，进一步对鳍片的角部进行圆润化处理。
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