CN101965632A - 半导体的安装结构体及其制造方法 - Google Patents

半导体的安装结构体及其制造方法 Download PDF

Info

Publication number
CN101965632A
CN101965632A CN2009801082646A CN200980108264A CN101965632A CN 101965632 A CN101965632 A CN 101965632A CN 2009801082646 A CN2009801082646 A CN 2009801082646A CN 200980108264 A CN200980108264 A CN 200980108264A CN 101965632 A CN101965632 A CN 101965632A
Authority
CN
China
Prior art keywords
electrode
resin
welding material
projection
engagement member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2009801082646A
Other languages
English (en)
Other versions
CN101965632B (zh
Inventor
大桥直伦
酒谷茂昭
岸新
山口敦史
宫川秀规
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN101965632A publication Critical patent/CN101965632A/zh
Application granted granted Critical
Publication of CN101965632B publication Critical patent/CN101965632B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13563Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13566Both on and outside the bonding interface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605Shape
    • H01L2224/16057Shape in side view
    • H01L2224/16058Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856Pre-cured adhesive, i.e. B-stage adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10992Using different connection materials, e.g. different solders, for the same connection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

半导体安装结构体中,具备:具有第1电极的半导体、具有第2电极的电路基板、在第1电极上形成的凸块、配置在凸块和第2电极之间且通过凸块将第1电极与第2电极电连接的接合构件、至少按照将凸块与接合构件的接合部分和接合构件覆盖的方式配置在各个接合构件的周围的增强树脂构件;各个增强树脂构件按照相邻的增强树脂构件之间不接触的方式相互分离地配置,同时以不与半导体接触的方式配置。由此,在半导体安装结构体中,能够提高连接部的抗冲击可靠性,同时容易进行半导体安装结构体的修理。

Description

半导体的安装结构体及其制造方法
技术领域
本发明涉及将半导体芯片(半导体元件)、半导体封装体等半导体在电路基板上电连接的半导体的安装结构体及其制造方法。
背景技术
移动电话、PDA(Personal Digital Assistant)等移动设备的小型化、高功能化不断发展,作为能够应对于此的安装技术,大量使用了BGA(Ball Grid Array)、CSP(Chip Scale Package)等安装结构。移动设备容易置于下落冲击等机械负荷。因此,对于如QFP(Quad Flat Package)的引线那样不具有缓和冲击的机构的BGA、CSP等安装结构,重要的是确保焊接连接部的抗冲击可靠性。
因此,目前为止使用了例如将BGA型半导体封装体与电子电路基板焊接连接时,如利用底部填充的密封增强那样,焊接后在BGA型半导体封装体和电子电路基板的间隙填充增强树脂材料,使BGA型半导体封装体和电子电路基板固着,从而缓和热、机械冲击引起的应力,提高接合部的抗冲击可靠性的手法。作为以往使用的底部填充密封剂,主要使用了加热固化型的环氧树脂(参照专利文献1、2、3)。
此外,近年来,由于对世界上环境问题的关注高涨,不含以往使用的Pb(铅)的无Pb焊料的实用化不断发展。现在,该无Pb焊料中,多采用具有润湿性比较好、连接可靠性高等优点的Sn-Ag-Cu系的焊料。此外,除了Sn-Ag-Cu系焊料以外,也已开始使用不具有Sn-Ag-Cu系焊料这样熔点高的优点的Sn-Zn系、Sn-Ag-In系、Sn-Bi系等低熔点无Pb焊料。但是,对于使用了Sn-Zn系、Sn-Ag-In系、Sn-Bi系焊料的BGA连接,其焊接连接部的连接可靠性尚不明确。
专利文献1:特开平10-101906号公报
专利文献2:特开平10-158366号公报
专利文献3:特开平10-204259号公报
但是,对于专利文献1、2所示的采用底部填充密封的增强结构,采用了通过增强树脂材料使BGA型半导体封装体和电路基板完全固着的结构。因此,产生了BGA型半导体封装体内的不良情况、BGA型半导体封装体与电路基板的连接不良时(或者事后发觉时),存在不能容易地将利用增强树脂材料的固着解除而使BGA型半导体封装体和电路基板分离,更换BGA型半导体封装体极其困难的问题。即,作为增强树脂材料,使用了热固化性树脂,因此在BGA型半导体封装体部件的耐热温度内,不能使作为热固化性树脂的增强树脂材料充分熔融,不能容易地剥离增强树脂。
因此,如专利文献3那样,提出了使用赋予了将上述问题加以改善的修理性(即,利用BGA型半导体封装体和电路基板的分离的BGA型半导体封装体的更换性)的粘合剂。专利文献3中,作为具有这样的良好修理性的粘合剂,记载了通过在单组分性或双组分性环氧树脂中添加增塑剂而能够短时间的热固化、并且能够将CSP、BGA等半导体与配线基板连接、耐热休克性优异、并且在发现了不良情况时能够容易取下CSP、BGA的底部填充密封用热固化性树脂组合物。
但是,对于专利文献3中公开的该方法,使用增塑剂是必要条件,存在树脂强度、即耐久性、耐热性、耐热循环性降低,由于增塑剂从固化物中析出而污染环境的问题。
发明内容
因此,本发明的目的在于解决上述问题,提供将半导体芯片、半导体封装体等半导体在电路基板上电连接的半导体的安装结构体中,能够提高连接部的抗冲击可靠性,同时能够容易地进行半导体安装结构体的修理的半导体安装结构体及其制造方法。
为了实现上述目的,本发明如下构成。
根据本发明的第1方案,提供半导体安装结构体,其具备:具有第1电极的半导体、具有第2电极的电路基板、在第1电极上形成的凸块、配置在凸块和第2电极之间并通过凸块将第1电极与第2电极电连接的接合构件、以至少将凸块与接合构件的接合部分和接合构件覆盖的方式配置在各个接合构件的周围的增强树脂构件;各个增强树脂构件以相邻的增强树脂构件之间不接触的方式相互分离地配置,同时以不与半导体接触的方式配置。
根据本发明的第2方案,提供第1方案所述的半导体安装结构体,其中,凸块和接合构件具有含有从Bi、In、Ag、Zn和Cu中选择的1种以上的元素与Sn的组合的合金组成。
根据本发明的第3方案,提供第2方案所述的半导体安装结构体,其中接合构件由熔点比形成凸块的焊接材料的熔点低10℃以上的合金材料形成。
根据本发明的第4方案,提供第3方案所述的半导体安装结构体,其中凸块由合金组成:Sn-Ag-Cu系的焊接材料形成,接合构件由合金组成:Sn-Bi系的焊接材料形成。
根据本发明的第5方案,提供第4方案所述的半导体安装结构体,其中增强树脂构件的高度H相对于第1电极与第2电极之间的距离D的比率(H1/D)为15%以上。
根据本发明的第6方案,提供第1方案~第5方案任一个所述的半导体安装结构体,其中在电路基板上的相邻的第2电极间,形成有防止各个增强树脂构件之间的接触的突起部。
根据本发明的第7方案,提供第1方案~第5方案任一个所述的半导体安装结构体,其中各个接合构件形成为其外周面成为环状的弯曲凹面形状,至少在接合构件的周围配置增强树脂构件以对接合构件的全部弯曲凹面填充增强树脂构件。
根据本发明的第8方案,提供第1方案~第5方案任一个所述的半导体安装结构体,其中在半导体和电路基板之间,按照将各个第1电极、第2电极、凸块和增强树脂构件覆盖的方式配置有另外的树脂材料。
根据本发明的第9方案,提供半导体安装结构体的制造方法,其中在电路基板上的第2电极上涂布含有增强用树脂材料和焊接材料的混合糊剂,借助混合糊剂将在半导体的第1电极上形成的焊接凸块配置于电路基板的第2电极上,
通过加热混合糊剂,使增强用树脂材料和焊接材料分离,借助焊接材料和焊接凸块将第1电极和第2电极电连接,同时至少按照将焊接凸块与焊接材料的接合部分和焊接材料覆盖的方式在各个焊接材料的周围配置增强用树脂材料。
根据本发明的第10方案,提供半导体安装结构体的制造方法,其中在电路基板上的第2电极上涂布糊状的焊接材料,在半导体的第1电极上形成的焊接凸块上,涂布增强用树脂材料,将半导体的焊接凸块上的增强用树脂材料配置在电路基板的焊接材料上,通过加热增强用树脂材料和焊接材料,借助焊接材料和焊接凸块将第1电极和第2电极电连接,同时至少按照将焊接凸块与焊接材料的接合部分和焊接材料覆盖的方式在各个焊接材料的周围配置增强用树脂材料。
根据本发明的第11方案,提供第9方案或第10方案的半导体安装结构体的制造方法,其中焊接材料具有比形成焊接凸块的材料的熔点低10℃以上的熔点,在焊接材料的加热时,不将焊接凸块熔融而将焊接材料熔融。
根据本发明,在半导体安装结构体中,通过按照将凸块与接合构件的接合部分和接合构件覆盖的方式在各个接合构件的周围配置增强树脂构件,能够通过增强树脂构件更确实可靠地增强凸块与接合构件的接合部分以及接合构件。增强树脂构件不与半导体接触,以覆盖凸块与接合构件的接合部分以及接合构件的方式配置,因此与半导体和电路基板之间用树脂材料密封的以往的结构相比,能够容易地进行半导体安装结构体的修理。再有,这样的修理可通过将接合构件再熔融,将凸块与第2电极的连接解除来进行。
此外,各个增强树脂构件按照相邻的增强树脂构件之间不接触的方式相互分离配置,因此即使产生再熔融的接合材料利用毛细管现象通过增强树脂构件中产生的微细的裂纹流出的情况,也能够确实可靠地防止相邻的电极间的短路。
因此,半导体安装结构体中,能够提高连接部的抗冲击可靠性,同时能够提高半导体安装结构体的修理性。
附图说明
本发明的这些方案和特征,由针对附图的优选的实施方式相关联的以下说明可清楚地获知。该附图中,
图1为本发明的第1实施方式涉及的半导体封装体的安装结构体的截面图;
图2为表示本发明的第2实施方式涉及的半导体封装体的安装结构体的制造方法(安装方法1)的图;
图3为表示本发明的第2实施方式中半导体封装体的安装结构体的制造方法(安装方法2)的图;
图4为表示本发明的第2实施方式中半导体封装体的安装结构体的制造方法(安装方法3)的图;
图5为表示本发明的实施例和比较例涉及的半导体封装体的安装结构体的测定结果的表;
图6为本发明的实施例的半导体封装体的安装结构体的接合部分的截面图。
具体实施方式
在继续本发明的说明之前,在附图中对于相同的部件标注相同的附图标记。
以下根据附图对本发明涉及的实施方式进行详细说明。
(第1实施方式)
图1是通过本第1实施方式中的安装方法得到的半导体封装体(半导体的一例,包括为半导体元件单独的情况和作为包含半导体元件的封装体而构成的情况。)1的安装结构体10的概略部分截面图。如图1所示,安装结构体10具有:具有多个电极2的BGA半导体封装体1、在各个电极2上形成的焊接凸块3、具有多个基板电极(第2电极的一例)5的电路基板4、存在于焊接凸块3和电路基板4的基板电极5之间并且将焊接凸块3与基板电极5电连接的接合构件9、和配置在各个接合构件9的周围且增强接合构件9的增强树脂(增强树脂构件)6。
在本第1实施方式的安装结构体10中,焊接凸块3固定于半导体封装体1的电极2上。此外,增强树脂6按照将接合构件9与焊接凸块3的接合部分(接合界面)和接合构件9覆盖的方式配置在各个接合构件9的周围。此外,相邻的增强树脂6之间按照相互不接触的方式彼此分离配置。即,相邻的增强树脂6之间设置有防止相互接触的间隔S。再有,该间隔S可以设定为一定的值,此外,也可对应于各个基板电极5的形成间隔分别设定。此外,增强树脂6以不与半导体封装体1接触的方式配置,配置成没有将各个焊接凸块3整体覆盖而只将一部分覆盖。此外,增强树脂6朝向电路基板4的基板电极5的一侧形成具有裙摆形状的焊脚。
在这样的结构的安装结构体10中,按照覆盖焊接凸块3与接合构件9的接合部分(接合界面)和接合构件9的方式,在各个接合构件9的周围配置有增强树脂6,从而能够通过增强树脂6确实可靠地增强焊接凸块3与接合构件9的接合部分和接合构件9自身。增强树脂6配置成不与BGA半导体封装体1接触而将焊接凸块3与接合构件9的接合部分和接合构件9自身覆盖的,因此与用树脂材料密封BGA半导体封装体1和电路基板4之间的以往的结构相比,能够容易地进行安装结构体10的修理,即BGA半导体封装体1的修理。再有,这样的修理可以通过将接合构件9再熔融,将焊接凸块3与基板电极5的连接解除来进行。
进而,各个增强树脂6按照相邻的增强树脂6之间不接触的方式相互分离地配置,即设置有间隔S,即使产生了在增强树脂6中产生微细的裂纹且再熔融的接合材料(例如焊接材料)利用毛细管现象通过该裂纹流出的情况,也能够确实地防止相邻的基板电极5间等的短路。
进而,增强树脂6在电路基板4侧形成成为裙摆的焊脚,电路基板4的基板电极5和电路基板4的表面的一部分被增强树脂6覆盖,因此受到热冲击、机械冲击时,能够抑制电路基板4的变形,能够使抗冲击性提高。
因此,BGA半导体封装体1的安装结构体10中,能够提高连接部的抗冲击可靠性,同时能够提高BGA半导体封装体1的修理特性。
在这里,对半导体封装体1的安装结构体10的构成和材料方案等,进一步详细说明。
半导体封装体1,以其为由BGA型半导体形成的BGA半导体封装体1的情形为一例进行了说明,但并不限于此。可以是具有焊接凸块的半导体。
作为焊接凸块3,可以使用例如锡系合金单独或这些合金的混合物,例如从Sn-Bi系、Sn-In系、Sn-Bi-In系、Sn-Ag系、Sn-Cu系、Sn-Ag-Cu系、Sn-Ag-Bi系、Sn-Cu-Bi系、Sn-Ag-Cu-Bi系、Sn-Ag-In系、Sn-Cu-In系、Sn-Ag-Cu-In系和Sn-Ag-Cu-Bi-In系选择的合金组成。焊接凸块3更优选具有含有从Bi、In、Ag、Zn和Cu中选择的1种以上的元素与Sn的组合的合金组成。
增强树脂6为热固化性树脂,可以含有环氧树脂、聚氨酯树脂、丙烯酸类树脂、聚酰亚胺树脂、聚酰胺树脂、双马来酰亚胺、酚醛树脂、聚酯树脂、有机硅树脂、氧杂环丁烷树脂等各种树脂。它们可以单独使用,也可以将2种以上组合使用。这些中,特别优选环氧树脂。
在环氧树脂中,还可以使用从双酚型环氧树脂、多官能环氧树脂、可挠性环氧树脂、溴化环氧树脂、缩水甘油酯型环氧树脂、高分子型环氧树脂中选择的环氧树脂。例如,适合使用双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂、联苯型环氧树脂、萘型环氧树脂、苯酚酚醛清漆型环氧树脂、甲酚酚醛清漆型环氧树脂等。也可以使用将这些改性而成的环氧树脂。它们可以单独使用,也可以将2种以上组合使用。
作为与上述的热固化性树脂组合使用的固化剂,可以使用从硫醇系化合物、改性胺系化合物、多官能酚系化合物、咪唑系化合物和酸酐系化合物中选择的化合物。它们可以单独使用,也可以将2种以上组合使用。固化剂可以根据导电性糊剂的使用环境、用途,选择适当的固化剂。
此外,根据需要,作为粘度调节/触变性赋予添加剂,可以使用无机系或有机系的物质,例如,如果是无机系,可以使用二氧化硅、氧化铝等,如果是有机系,可以使用固体的环氧树脂、低分子量的酰胺、聚酯系、蓖麻油的有机衍生物等。它们可以单独使用,也可以将2种以上组合使用。
再有,本第1实施方式中使用的BGA半导体封装体1的大小,例如,为11mm×11mm的大小,焊接凸块3具有0.5mm间距,凸块数为441个,电路基板4为3cm×7cm的大小,厚度为0.8mm,电极材质为铜,基板材质为玻璃环氧材料。
(第2实施方式)
本第2实施方式涉及本发明的1个方案中半导体封装体1的安装方法,即半导体封装体1的安装结构体10的制造方法,使用图2、图3和图4对3个图案的安装方法(制造方法)1、2、3进行说明。再有,对于与图1所示的安装结构体10基本上相同的构成构件,标注相同的附图标记而省略其说明。
(安装方法1)
首先,对安装方法1进行说明。如图2所示,在电路基板4的基板电极5上印刷由下述焊接材料与未固化状态的热固化性树脂混合得到的混合糊剂71(即焊接材料和热固化性树脂的混合糊剂),所述焊接材料是由Sn与选自Bi、In、Ag和Cu中2种或2种以上的元素的组合构成的合金组成的材料。然后,进行在BGA半导体封装体1的电极2上形成的各个焊接凸块3与在电路基板4的基板电极5上印刷的混合糊剂71的对位,按照使焊接凸块3与混合糊剂71接触的方式在电路基板4上安装BGA半导体封装体1。
然后,使用回流装置,加热将焊接材料和热固化性树脂混合得到的混合糊剂71,使焊接材料熔融。通过将混合糊剂71中的焊接材料熔融,成为已熔融的焊接材料与焊接凸块3和基板电极5的表面相润湿的状态(金属扩散状态),由此,在混合糊剂71中,焊接材料与热固化性树脂分离。已分离的热固化性树脂配置于焊接材料的周围。然后,热固化性树脂发生热固化而成为增强树脂6,同时焊接材料凝固,成为接合构件9,将焊接凸块3和基板电极5电连接。此外,增强树脂6覆盖接合构件9与焊接凸块3的接合部分和接合构件9而将其增强。此外,优选调整混合糊剂71的印刷量,以使各个增强树脂6覆盖接合构件9与焊接凸块3的接合部分和接合构件9,并且增强树脂6不与半导体封装体1接触,进而相邻的增强树脂6之间相互分离。
因此,采用安装方法1,能够形成图1所示的第1实施方式的BGA型半导体封装体1的安装结构体10。
(安装方法2)
接着,对安装方法2进行说明。如图3所示,在电路基板4的基板电极5上印刷由Sn与选自Bi、In、Ag和Cu中2种或2种以上的元素的组合构成的合金组成的焊接糊剂7。其次,将未固化状态的热固化性树脂8转印于由Sn与选自Bi、In、Ag、Zn和Cu中2种或2种以上的元素的组合构成的合金组成所形成的BGA半导体封装体1的焊接凸块3上。热固化性树脂的转印通过用刮板将树脂铺展为0.1~1mm左右的均匀的薄度,在其上放置BGA半导体封装体1的焊接凸块3而进行。
关于热固化性树脂8的转印量,可以通过控制用刮板铺薄时的树脂的薄度、或者将BGA半导体封装体1的焊接凸块3压靠于树脂时的压入量等来调整。具体而言,进行热固化性树脂8的转印量的调整,以使安装结束后热固化性树脂(即增强树脂6)、各个增强树脂6,覆盖接合构件9与焊接凸块3的接合部分和接合构件9,并且增强树脂6不与半导体封装体1接触,进而相邻的增强树脂6之间相互分离。
然后,将半导体封装体1安装于电路基板4,使用回流装置,使焊接糊剂7熔融,进行焊接,另外同时热固化性树脂的固化也完成。由此,焊接糊剂7凝固而成为接合构件9,将焊接凸块3与基板电极5电连接,同时热固化性树脂6成为在接合构件9的周围配置的增强树脂6,将接合构件9与焊接凸块3的接合部分和接合构件9覆盖而使其增强。
因此,采用安装方法2,能够形成图1所示的第1实施方式的BGA型半导体封装体1的安装结构体10。
(安装方法3)
接着,对安装方法3进行说明。如图4所示,只在电路基板4的基板电极5的衬垫上印刷焊接糊剂7。然后,用丝网印刷、分配器等将未固化状态的热固化性树脂8供给到电路基板4上。供给场所可以是焊接糊剂7上,也可以是其周边,此外,可以是电路基板4的全部基板电极5上,或者是电路基板4的中央部、四角等一部分的基板电极5的周围。调整热固化性树脂8的供给量,以使安装结束后热固化性树脂8(即增强树脂6)、各个增强树脂6覆盖接合构件9与焊接凸块3的接合部分和接合构件9,并且增强树脂6不与半导体封装体1接触,进而相邻的增强树脂6之间相互分离。除了这样的热固化性树脂8的供给量的调节,如图4所示,可在各个基板电极5之间的电路基板4上设置突起构件4a。通过这样设置突起构件4a,安装结束后,能够使电路基板4与增强树脂6的接合强度提高,同时能够确实可靠地使相邻的增强树脂6之间分离。再有,如果能够在相邻的热固化性树脂7间设置间隔S,可以代替如此设置突起构件4a的情形,而采用其他各种手段。
然后,将BGA半导体封装体1安装于电路基板4,使用回流装置,使焊接糊剂7熔融而进行焊接,另外同时热固化性树脂的固化也完成。由此,焊接糊剂7凝固而成为接合构件9,将焊接凸块3与基板电极5电连接,同时热固化性树脂6成为配置在接合构件9的周围的增强树脂6,将接合构件9与焊接凸块3的接合部分和接合构件9覆盖而使其增强。
因此,采用安装方法3,能够形成图1所示的第1实施方式的BGA型半导体封装体1的安装结构体10。
此外,用于焊接糊剂的焊接材料的熔点,优选为比用于焊接凸块的焊接材料的熔点低10℃以上的温度,更优选为低20℃以上的温度。通过如此设置熔点差,修理半导体安装结构体10时,能够将接合构件9再加热而容易地使其熔融,能够提高修理性。如果考虑这样的熔点差,希望焊接凸块由合金组成为Sn-Ag-Cu系的焊接材料形成,接合构件由合金组成为Sn-Bi系的焊接材料形成。
(实施例)
作为本发明的实施例,对于使用上述安装方法2安装的BGA型半导体封装体1的安装结构体10,使焊接糊剂的种类和回流温度、增强树脂的量改变,考察对抗冲击性、修理性的影响,将其结果示于图5的表中。作为图5的表,示出使用本发明的安装方法2安装的安装结构体10的实施例1~6与成为比较对象的比较例1~4。
焊接糊剂7使用了Sn58Bi焊接糊剂(商品名“L20-BLT-5-T7F”、千住金属工业株式会社制)。
作为BGA型的半导体封装体1,使用搭载了SnAgCu球作为焊接凸块3的Daisy-chain配线半导体封装体,热固化性树脂共同地使用双酚F型环氧树脂(商品名“Epicoat 806”、日本环氧树脂制),固化剂共同地使用咪唑系固化剂(商品名“Curezole 2P4MZ”、四国化成制),粘度调节/触变性赋予添加剂共同地使用蓖麻油系触变剂(商品名“THIXCIN R”、日本Elementis制)。
焊接凸块3(SnAgCu球)的熔点为219℃,焊接糊剂7(Sn58Bi焊接糊剂)的熔点为138℃。
用于焊接糊剂7的回流的加热温度(回流最高到达温度)为焊接糊剂7的熔点以上,并且作为小于焊接凸块3的熔点的温度,实施例和比较例中共同地进行加热到155℃,形成了安装结构体。
此外,对于各个实施例1~6和比较例1~4,改变了增强树脂6的添加量而形成了安装结构体。具体而言,对于增强树脂6的添加量,在安装结束后的状态下,用从基板电极侧润湿上升的增强树脂6的高度相对于包含焊接凸块3的高度和接合部9高度的总高度的比例进行计算,示于图5的表中。在实施例1~6中,将增强树脂6的树脂高度的比设定在15%~80%的范围内,在比较例1~4中,设定为0%(无增强树脂)、5%、10%、100%。
各个BGA型半导体封装体的安装结构体的评价如下所述进行。
作为抗冲击试验,用耐落下寿命进行评价。具体而言,从30cm的高度使安装结构体落下,在半导体封装体中,如果阻抗值上升了20%以上,判断为不良,将直至不良情况发生时的落下次数作为耐落下寿命。作为耐落下寿命,按合格、容许范围内、不合格的三等级评价。
再有,这里使用的BGA半导体封装体的大小为11mm×11mm大小,焊接凸块3为0.5mm间距,凸块数为441个,电路基板4为3cm×7cm的大小,厚度为0.8mm,电极材质为铜,基板材质为玻璃环氧材料。
作为修理性,使用热板使安装结构体的温度上升到250℃,30秒后,用钳子以10N的力将BGA型的半导体封装体1剥离。如果能够由此剥离,则为合格,如果不能则为不合格,其中间为容许范围内,按三等级评价。
(测定结果)
在图5的表所示的测定结果中,将实施例4(增强树脂高度为50%)与比较例3(增强树脂高度为100%)进行对比,在耐落下寿命方面得到了同等程度的结果,但比较例3中修理性显著劣化,实施例4得到了良好的结果。此外,将实施例4(增强树脂高度为50%)与比较例4(增强树脂高度为0%)进行对比,比较例4中,耐落下寿命显著劣化,实施例4得到了良好的结果。
此外,将实施例1(增强树脂高度为15%)与比较例2(增强树脂高度为10%)进行对比,耐落下寿命中,实施例1为40次,比较例2为25次,可知实施例1得到了能够耐实用的结果。进而,将实施例6(增强树脂高度为80%)与比较例3(增强树脂高度为100%)进行对比,在修理性方面,可知实施例6得到了能够耐实用的结果。
因此,实施例1~6中,可知能够同时实现能够耐实用的耐落下寿命的确保和修理性的提高。从这样的观点出发,可以说将增强树脂高度的比例设定为15%以上、更优选15%~80%的范围内是有效的。即,增强树脂6的润湿上升高度H相对于半导体封装体1的电极2与电路基板4的基板电极5之间的距离D的比率(H/D)设定为15%以上、更优选15%~80%的范围内可以说是有效的。
此外,虽在实施例1~6和比较例1~4中没有提及,但在回流最高到达温度245℃下焊接时,脆弱的Bi成分分散在整体中,因此确认没有被增强树脂覆盖的脆弱的组成露出,耐落下冲击性降低。对此,在如实施例1~6那样不使焊接凸块熔融而只使焊接糊剂即SnBi熔融时,Bi没有在整个接合构件9中分散,而作为SnBi存在于电路基板4侧,电路基板4侧被增强树脂6覆盖,因此脆弱的组成没有露出,认为耐落下冲击性增大。
由此,在本发明的半导体封装体1的安装结构体10的结构中,使用脆弱的SnBi等低温焊料,焊接SnAgCu焊接凸块的BGA半导体封装体1时,即使在SnAgCu焊料熔融的温度下焊接,也会得到增强树脂产生的增强效果,但在SnAgCu焊料不熔融的温度下焊接时,得到的增强树脂的增强效果大,所以优选。
以安装方法2为例进行了说明,但其他的安装方法1、3也得到同样的结果。
在这里,将由上述的实施例得到的本发明的半导体封装体1的安装结构体10中接合部分的截面图示于图6。
在图6所示的安装结构体10的实施例中,作为焊接凸块3,使用SnAgCu系例如Sn-3Ag-0.5Cu焊接凸块(熔点219℃),接合构件9由SnBi系例如Sn-58Bi焊料(熔点138℃)形成。此外,作为增强树脂6,使用了环氧树脂。
图6的安装结构体10中,接合构件9的外周面形成为大致环状的弯曲凹面形状,在接合构件9的弯曲凹面的整个外周填充增强树脂6,从而将接合构件9增强。通过采用这样的增强结构,能够更有效地得到增强树脂6产生的增强效果。
再有,通过将上述各种实施方式中的任意的实施方式适当组合,能够产生各自具有的效果。
本发明边参照附图边与优选的实施方式关联而充分记载,对于本领域技术人员而言,可知各种变形、修正。只要这样的变形、修正未脱离所附的权利要求限定的本发明的范围以外,应理解为包含在其中。
2008年10月27日申请的日本专利申请No.2008-275109号的说明书、附图和权利要求的公开内容全部作为参考而引入本说明书中。
产业上的利用可能性
本发明的BGA半导体封装体的安装结构体及其制造方法,在电气/电子电路形成技术的领域中能够用于广泛的用途。例如,能够用于CCD元件、全息元件、芯片部件等电子部件的连接用以及将它们与基板接合的用途,能够用于内置这些元件、部件或基板的制品,例如DVD、移动电话、便携AV设备、数码相机等。

Claims (11)

1.一种半导体安装结构体,其具备:
具有第1电极的半导体、
具有第2电极的电路基板、
在第1电极上形成的凸块、
配置在凸块和第2电极之间并通过凸块将第1电极与第2电极电连接的接合构件、
至少按照将凸块与接合构件的接合部分和接合构件覆盖的方式配置在各个接合构件的周围的增强树脂构件;
各个增强树脂构件按照相邻的增强树脂构件之间不接触的方式相互分离地配置,同时以不与半导体接触的方式配置。
2.如权利要求1所述的半导体安装结构体,其中,
凸块和接合构件具有含有下述组合的合金组成,所述组合是从Bi、In、Ag、Zn和Cu中选择的1种以上的元素与Sn的组合。
3.如权利要求2所述的半导体安装结构体,其中,
接合构件由熔点比形成凸块的焊接材料的熔点低10℃以上的合金材料形成。
4.如权利要求3所述的半导体安装结构体,其中,
凸块由合金组成为Sn-Ag-Cu系的焊接材料形成,接合构件由合金组成为Sn-Bi系的焊接材料形成。
5.如权利要求4所述的半导体安装结构体,其中,
增强树脂构件的高度H相对于第1电极和第2电极之间的距离D的比率H1/D为15%以上。
6.如权利要求1~5任一项所述的半导体安装结构体,其中,
在电路基板上相邻的第2电极间,形成有防止各个增强树脂构件之间的接触的突起部。
7.如权利要求1~5任一项所述的半导体安装结构体,其中,
各个接合构件形成为其外周面成为环状的弯曲凹面形状,至少按照向接合构件的全部弯曲凹面填充增强树脂构件的方式在接合构件的周围配置增强树脂构件。
8.如权利要求1~5任一项所述的半导体安装结构体,其中,
在半导体和电路基板之间,按照将各个第1电极、第2电极、凸块和增强树脂构件覆盖的方式配置有另外的树脂材料。
9.一种半导体安装结构体的制造方法,其中,
在电路基板上的第2电极上涂布含有增强用树脂材料和焊接材料的混合糊剂,
借助混合糊剂将在半导体的第1电极上形成的焊接凸块配置于电路基板的第2电极上,
通过加热混合糊剂,使增强用树脂材料和焊接材料分离,借助焊接材料和焊接凸块将第1电极和第2电极电连接,同时至少按照将焊接凸块与焊接材料的接合部分和焊接材料覆盖的方式在各个焊接材料的周围配置增强用树脂材料。
10.一种半导体安装结构体的制造方法,其中,
在电路基板上的第2电极上涂布糊状的焊接材料,
在半导体的第1电极上形成的焊接凸块上,涂布增强用树脂材料,
将半导体的焊接凸块上的增强用树脂材料配置在电路基板的焊接材料上,
通过加热增强用树脂材料和焊接材料,借助焊接材料和焊接凸块将第1电极和第2电极电连接,同时至少按照将焊接凸块与焊接材料的接合部分和焊接材料覆盖的方式在各个焊接材料的周围配置增强用树脂材料。
11.如权利要求9或10所述的半导体安装结构体的制造方法,其中,
焊接材料具有比形成焊接凸块的材料的熔点低10℃以上的熔点,在焊接材料的加热时,没有将焊接凸块熔融而将焊接材料熔融。
CN2009801082646A 2008-10-27 2009-10-27 半导体的安装结构体及其制造方法 Expired - Fee Related CN101965632B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008275109 2008-10-27
JP2008-275109 2008-10-27
PCT/JP2009/005662 WO2010050185A1 (ja) 2008-10-27 2009-10-27 半導体の実装構造体およびその製造方法

Publications (2)

Publication Number Publication Date
CN101965632A true CN101965632A (zh) 2011-02-02
CN101965632B CN101965632B (zh) 2012-09-26

Family

ID=42128556

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801082646A Expired - Fee Related CN101965632B (zh) 2008-10-27 2009-10-27 半导体的安装结构体及其制造方法

Country Status (4)

Country Link
US (1) US8450859B2 (zh)
JP (2) JP5204241B2 (zh)
CN (1) CN101965632B (zh)
WO (1) WO2010050185A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103460815A (zh) * 2011-04-04 2013-12-18 松下电器产业株式会社 安装结构体及其制造方法
CN104246997A (zh) * 2012-05-10 2014-12-24 松下知识产权经营株式会社 安装结构体及其制造方法
CN105684138A (zh) * 2014-07-29 2016-06-15 松下知识产权经营株式会社 半导体部件和使用其的半导体安装品、半导体安装品的制造方法
CN111292634A (zh) * 2020-03-26 2020-06-16 京东方科技集团股份有限公司 一种显示基板和显示面板
CN116744548A (zh) * 2022-09-20 2023-09-12 荣耀终端有限公司 电路板组件及其加工方法、电子设备
CN117727723A (zh) * 2024-02-15 2024-03-19 江门市和美精艺电子有限公司 一种封装基板中bga防翘曲封装结构及封装工艺

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080308932A1 (en) * 2007-06-12 2008-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
US20100307805A1 (en) * 2007-10-29 2010-12-09 Hitachi Chemical Company, Ltd. Circuit connecting material, connection structure and method for producing the same
JP2012039045A (ja) * 2010-08-11 2012-02-23 Nec Embedded Products Ltd パッケージ、電子機器、パッケージ接続方法及びパッケージ修理方法
JP5463328B2 (ja) * 2010-09-16 2014-04-09 株式会社タムラ製作所 パッケージ部品の接合方法およびその方法に用いる熱硬化性樹脂組成物
JP5587804B2 (ja) * 2011-01-21 2014-09-10 日本特殊陶業株式会社 電子部品実装用配線基板の製造方法、電子部品実装用配線基板、及び電子部品付き配線基板の製造方法
JP5534107B2 (ja) * 2011-07-25 2014-06-25 株式会社村田製作所 ベアチップ実装構造の電子部品およびその製造方法並びにベアチップ実装構造の電子部品を備える複合モジュール並びにその製造方法
JP5869911B2 (ja) * 2012-02-23 2016-02-24 株式会社タムラ製作所 熱硬化性樹脂組成物
JP6179287B2 (ja) * 2013-09-09 2017-08-16 富士通株式会社 半導体装置の製造方法
US9925612B2 (en) * 2014-07-29 2018-03-27 Panasonic Intellectual Property Management Co., Ltd. Semiconductor component, semiconductor-mounted product including the component, and method of producing the product
KR101778498B1 (ko) 2014-10-10 2017-09-13 이시하라 케미칼 가부시키가이샤 합금 범프의 제조방법
JP6447155B2 (ja) * 2015-01-16 2019-01-09 富士通株式会社 電子装置及び電子装置の製造方法
US9472531B2 (en) * 2015-02-06 2016-10-18 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing phthalate
US9824998B2 (en) 2015-02-06 2017-11-21 Semigear, Inc. Device packaging facility and method, and device processing apparatus utilizing DEHT
JP6124032B2 (ja) 2015-08-04 2017-05-10 パナソニックIpマネジメント株式会社 実装構造体と実装構造体の製造方法
JP6659950B2 (ja) * 2016-01-15 2020-03-04 富士通株式会社 電子装置及び電子機器
KR101892468B1 (ko) * 2016-06-10 2018-08-27 엘지이노텍 주식회사 인쇄회로기판 및 그 제조 방법
JPWO2018134860A1 (ja) * 2017-01-17 2019-11-07 パナソニックIpマネジメント株式会社 半導体実装品
JP6990488B2 (ja) * 2017-08-30 2022-02-10 株式会社タムラ製作所 熱硬化性フラックス組成物および電子基板の製造方法
WO2020066488A1 (ja) * 2018-09-28 2020-04-02 株式会社村田製作所 接続電極および接続電極の製造方法
US11483937B2 (en) * 2018-12-28 2022-10-25 X Display Company Technology Limited Methods of making printed structures
JP2021070057A (ja) 2019-11-01 2021-05-06 パナソニックIpマネジメント株式会社 はんだペーストおよび実装構造体
US11600498B2 (en) * 2019-12-31 2023-03-07 Texas Instruments Incorporated Semiconductor package with flip chip solder joint capsules
JP2021178336A (ja) 2020-05-12 2021-11-18 パナソニックIpマネジメント株式会社 樹脂フラックスはんだペーストおよび実装構造体
US11830746B2 (en) * 2021-01-05 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11721642B2 (en) * 2021-06-17 2023-08-08 Nxp Usa, Inc. Semiconductor device package connector structure and method therefor
WO2023248302A1 (ja) * 2022-06-20 2023-12-28 三菱電機株式会社 はんだ接合部材、半導体装置、はんだ接合方法、および、半導体装置の製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10101906A (ja) 1996-10-03 1998-04-21 Shin Etsu Chem Co Ltd 液状エポキシ樹脂組成物の製造方法
JP3351974B2 (ja) 1996-12-05 2002-12-03 住友ベークライト株式会社 液状注入封止アンダーフィル材料
US6316528B1 (en) * 1997-01-17 2001-11-13 Loctite (R&D) Limited Thermosetting resin compositions
JP3613367B2 (ja) 1997-01-17 2005-01-26 ヘンケル コーポレイション 熱硬化性樹脂組成物
JP3067693B2 (ja) 1997-06-02 2000-07-17 日本電気株式会社 はんだバンプ構造体及びはんだバンプ構造体の製造方法
JP2000058709A (ja) * 1998-08-17 2000-02-25 Nec Corp 突起電極構造および突起電極形成方法
CN1228826C (zh) * 1999-03-12 2005-11-23 晶扬科技股份有限公司 高低熔点球栅阵列结构
US6583354B2 (en) * 1999-04-27 2003-06-24 International Business Machines Corporation Method of reforming reformable members of an electronic package and the resultant electronic package
JP4071893B2 (ja) 1999-05-31 2008-04-02 京セラ株式会社 配線基板およびその実装構造
JP2002026070A (ja) 2000-07-04 2002-01-25 Toshiba Corp 半導体装置およびその製造方法
JP4609617B2 (ja) 2000-08-01 2011-01-12 日本電気株式会社 半導体装置の実装方法及び実装構造体
JP2002050717A (ja) 2000-08-03 2002-02-15 Nec Corp 半導体装置およびその製造方法
JP2002299518A (ja) 2001-04-03 2002-10-11 Sumitomo Bakelite Co Ltd 半導体パッケージ、その製造方法、及び、半導体装置
JP3608536B2 (ja) * 2001-08-08 2005-01-12 松下電器産業株式会社 電子部品実装方法
JP4977937B2 (ja) 2001-09-25 2012-07-18 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
JP3708478B2 (ja) * 2001-11-20 2005-10-19 松下電器産業株式会社 電子部品の実装方法
JP3925252B2 (ja) * 2002-03-15 2007-06-06 松下電器産業株式会社 電子部品実装方法
JP2005064303A (ja) * 2003-08-15 2005-03-10 Sony Corp 光電気複合基板装置及びその製造方法
JP4283091B2 (ja) * 2003-11-10 2009-06-24 富士通株式会社 電子部品の実装方法
KR100733208B1 (ko) * 2004-10-11 2007-06-27 삼성전기주식회사 플립칩 실장 기술을 이용한 반도체 패키지
JP4729963B2 (ja) * 2005-04-15 2011-07-20 パナソニック株式会社 電子部品接続用突起電極とそれを用いた電子部品実装体およびそれらの製造方法
JP5022756B2 (ja) 2007-04-03 2012-09-12 オンセミコンダクター・トレーディング・リミテッド 半導体チップの実装方法

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9603295B2 (en) 2011-04-04 2017-03-21 Panasonic Intellectual Property Management Co., Ltd. Mounted structure and manufacturing method of mounted structure
CN103460815A (zh) * 2011-04-04 2013-12-18 松下电器产业株式会社 安装结构体及其制造方法
CN103460815B (zh) * 2011-04-04 2017-06-23 松下知识产权经营株式会社 安装结构体及其制造方法
US9795036B2 (en) 2012-05-10 2017-10-17 Panasonic Intellectual Property Management Co., Ltd. Mounting structure and method for manufacturing same
CN104246997A (zh) * 2012-05-10 2014-12-24 松下知识产权经营株式会社 安装结构体及其制造方法
US10412834B2 (en) 2012-05-10 2019-09-10 Panasonic Intellectual Property Management Co., Ltd. Mounting structure and method for manufacturing same
TWI582915B (zh) * 2012-05-10 2017-05-11 松下知識產權經營股份有限公司 Mounting structure and manufacturing method thereof
CN104246997B (zh) * 2012-05-10 2017-09-08 松下知识产权经营株式会社 安装结构体及其制造方法
CN106537571A (zh) * 2014-07-29 2017-03-22 松下知识产权经营株式会社 半导体安装品及其制造方法
CN105684138B (zh) * 2014-07-29 2019-09-06 松下知识产权经营株式会社 半导体部件和半导体安装品的制造方法
CN105684138A (zh) * 2014-07-29 2016-06-15 松下知识产权经营株式会社 半导体部件和使用其的半导体安装品、半导体安装品的制造方法
CN106537571B (zh) * 2014-07-29 2019-11-01 松下知识产权经营株式会社 半导体安装品及其制造方法
CN111292634A (zh) * 2020-03-26 2020-06-16 京东方科技集团股份有限公司 一种显示基板和显示面板
CN111292634B (zh) * 2020-03-26 2022-08-09 京东方科技集团股份有限公司 一种显示基板和显示面板
CN116744548A (zh) * 2022-09-20 2023-09-12 荣耀终端有限公司 电路板组件及其加工方法、电子设备
CN116744548B (zh) * 2022-09-20 2024-05-10 荣耀终端有限公司 电路板组件及其加工方法、电子设备
CN117727723A (zh) * 2024-02-15 2024-03-19 江门市和美精艺电子有限公司 一种封装基板中bga防翘曲封装结构及封装工艺
CN117727723B (zh) * 2024-02-15 2024-04-26 江门市和美精艺电子有限公司 一种封装基板中bga防翘曲封装结构及封装工艺

Also Published As

Publication number Publication date
JP2013123078A (ja) 2013-06-20
US8450859B2 (en) 2013-05-28
US20110095423A1 (en) 2011-04-28
JP5557936B2 (ja) 2014-07-23
WO2010050185A1 (ja) 2010-05-06
CN101965632B (zh) 2012-09-26
JP5204241B2 (ja) 2013-06-05
JPWO2010050185A1 (ja) 2012-03-29

Similar Documents

Publication Publication Date Title
CN101965632B (zh) 半导体的安装结构体及其制造方法
US6238599B1 (en) High conductivity, high strength, lead-free, low cost, electrically conducting materials and applications
US8188605B2 (en) Components joining method and components joining structure
JP5967489B2 (ja) 実装構造体
CN101728354B (zh) 电子设备及其制造方法
US10440834B2 (en) Resin fluxed solder paste, and mount structure
KR101982034B1 (ko) 이방성 도전성 페이스트 및 그것을 사용한 전자부품의 접속방법
CN104246997B (zh) 安装结构体及其制造方法
JP2002151170A (ja) 導電性材料の使用方法
US20180229333A1 (en) Solder paste and mount structure obtained by using same
CN102088822A (zh) 具有焊点自保护功能的pcb基板及其焊盘制作工艺
JP2017080797A (ja) はんだペースト及びはんだ付け用フラックス及びそれを用いた実装構造体
CN108406165B (zh) 焊膏和由其得到的安装结构体
JP2017022190A (ja) 実装構造体
CN106449444B (zh) 组装结构体及组装结构体的制造方法
CN114502685B (zh) 连接体的制备方法、各向异性导电接合材料及连接体
CN117715726A (zh) 助焊剂用树脂组合物、焊料糊剂和安装结构体
JP5579996B2 (ja) はんだ接合方法
JP2018181939A (ja) 半導体部品の実装構造体
JP2019140359A (ja) 実装構造体とその製造方法
Melton Alternatives of lead bearing solder alloys
JP2018181937A (ja) リペア性に優れる実装構造体
JP2017152652A (ja) 半導体部品の実装構造体

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120926

CF01 Termination of patent right due to non-payment of annual fee