JP2013123078A - 半導体の実装構造体およびその製造方法 - Google Patents
半導体の実装構造体およびその製造方法 Download PDFInfo
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- JP2013123078A JP2013123078A JP2013026869A JP2013026869A JP2013123078A JP 2013123078 A JP2013123078 A JP 2013123078A JP 2013026869 A JP2013026869 A JP 2013026869A JP 2013026869 A JP2013026869 A JP 2013026869A JP 2013123078 A JP2013123078 A JP 2013123078A
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- solder
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Abstract
【解決手段】半導体実装構造体10において、第1電極2を有する半導体1と、複数の第2電極5を有する回路基板4と、第1電極上に形成されたはんだバンプ3と、はんだバンプと第2電極との間に配置され、はんだバンプを通じて第1電極と第2電極とを電気的に接続し、はんだバンプの融点より低い融点を有するはんだ材料により形成された接合部材9と、少なくとも、はんだバンプと接合部材との接合部分および接合部材を覆うように、個々の接合部材の周囲に配置された樹脂部材6とを備え、それぞれの樹脂部材は、隣接する樹脂部材同士が、互いに離間して配置されているとともに、回路基板上における隣接する第2電極間に個々の樹脂部材同士の接触を防止する空間Sが形成されている。
【選択図】図1
Description
以下に、本発明にかかる実施の形態を図面に基づいて詳細に説明する。
図1は、本第1実施形態における実装方法によって得られる半導体パッケージ(半導体の一例であって、半導体素子単体である場合、および半導体素子を含むパッケージとして構成される場合を含む。)1の実装構造体10の概略部分断面図である。図1に示すように、実装構造体10は、複数の電極2を有するBGA半導体パッケージ1と、それぞれの電極2上に形成されたはんだバンプ3と、複数の基板電極(第2電極の一例)5を有する回路基板4と、はんだバンプ3と回路基板4の基板電極5との間に介在して、はんだバンプ3と基板電極5とを電気的に接続する接合部材9と、それぞれの接合部材9の周囲に配置され、接合部材9を補強する補強樹脂(補強樹脂部材)6とを備える。
本第2実施形態は、本発明の1つの形態における半導体パッケージ1の実装方法、すなわち半導体パッケージ1の実装構造体10の製造方法に関するものであり、図2、図3、および図4を用いて3つのパターンの実装方法(製造方法)1、2、3について説明する。なお、図1に示す実装構造体10と実質的に同じ構成部材には、同じ参照番号を付してその説明を省略する。
まず、実装方法1について説明する。図2に示すように、回路基板4の基板電極5上に、Snと、Bi、In、AgおよびCuの群から選ばれる2種もしくはそれ以上の元素との組合せからなる合金組成のはんだ材料と、未硬化状態の熱硬化性樹脂とが混ざった混合ペースト71(すなわち、はんだ材料と熱硬化性樹脂との混合ペースト)を印刷する。その後、BGA半導体パッケージ1の電極2上に形成されたそれぞれのはんだバンプ3と、回路基板4の基板電極5上に印刷された混合ペースト71との位置合わせを行い、はんだバンプ3と混合ペースト71とを接触させるように、回路基板4上にBGA半導体パッケージ1をマウントする。
次に、実装方法2について説明する。図3に示すように、回路基板4の基板電極5上にSnと、Bi、In、AgおよびCuの群から選ばれる2種もしくはそれ以上の元素との組合せからなる合金組成のはんだペースト7を印刷する。次に、未硬化状態の熱硬化性樹脂8を、Snと、Bi、In、Ag、ZnおよびCuの群から選ばれる2種もしくはそれ以上の元素との組合せからなる合金組成からなるBGA半導体パッケージ1のはんだバンプ3上に転写する。熱硬化性樹脂の転写は、樹脂をスキージで0.1〜1mm程度の均一な薄さに広げ、そこにBGA半導体パッケージ1のはんだバンプ3を載せることで行う。
次に、実装方法3について説明する。図4に示すように、回路基板4の基板電極5のパッド上にのみ、はんだペースト7を印刷する。その後、未硬化状態の熱硬化性樹脂8をスクリーン印刷やディスペンサーなどで回路基板4上に供給する。供給場所ははんだペースト7の上でも、その周辺でもよく、また、回路基板4の全ての基板電極5上、あるいは、回路基板4における中央部や四隅など、一部の基板電極5の周囲でもよい。熱硬化性樹脂8の供給量は、実装完了後に熱硬化性樹脂8(すなわち補強樹脂6)が、それぞれの補強樹脂6が接合部材9とはんだバンプ3との接合部分および接合部材9を覆い、かつ補強樹脂6が半導体パッケージ1に接触することなく、さらに隣接する補強樹脂6同士が互いに離間するように、調整する。このような熱硬化性樹脂8の供給量の調整に加えて、図4に示すように、それぞれの基板電極5の間における回路基板4上に突起部材4aを設けても良い。このように突起部材4aを設けることにより、実装完了後に、回路基板4と補強樹脂6との接合強度を向上させながら、隣接する補強樹脂6同士を確実に離間させることができる。なお、隣接する熱硬化性樹脂7間にスペースSを設けることができれば、このように突起部材4aを設けるような場合に代えて、他の様々な手段を採用しても良い。
本発明の実施例として、上述の実装方法2を用いて実装したBGA型半導体パッケージ1の実装構造体10について、はんだペーストの種類とリフロー温度、補強樹脂の量を変化させ、耐衝撃性やリペア性への影響を調べ、図5の表にその結果を示した。図5の表としては、本発明の実装方法2を用いて実装した実装構造体10の実施例1〜6と、比較対象となる比較例1〜4について示している。
図5の表に示す測定結果において、実施例4(補強樹脂高さが50%)と比較例3(補強樹脂高さが100%)を対比すると、耐落下寿命では同程度の結果を得ながら、比較例3ではリペア性が著しく劣り、実施例4が良好な結果を得ている。また、実施例4(補強樹脂高さが50%)と比較例4(補強樹脂高さが0%)を対比すると、比較例4では、耐落下寿命が著しく劣り、実施例4が良好な結果を得ている。
2 電極
3 はんだバンプ
4 回路基板
5 基板電極
6 補強樹脂
9 接合部材
10 実装構造体
Claims (12)
- 第1電極を有する半導体と、
複数の第2電極を有する回路基板と、
第1電極上に形成されたはんだバンプと、
はんだバンプと第2電極との間に配置され、はんだバンプを通じて第1電極と第2電極とを電気的に接続し、はんだバンプの融点より低い融点を有するはんだ材料により形成された接合部材と、
少なくとも、はんだバンプと接合部材との接合部分および接合部材を覆うように、個々の接合部材の周囲に配置された樹脂部材とを備え、
それぞれの樹脂部材は、隣接する樹脂部材同士が、互いに離間して配置されているとともに、半導体と接触せず配置されており、
回路基板上における隣接する第2電極間に、個々の樹脂部材同士の接触を防止する空間が形成されている、半導体実装構造体。 - 樹脂部材は、はんだバンプと接合部材との接合部分のそれぞれを個別に覆い、それぞれが独立して回路基板に配置されている、請求項1に記載の半導体実装構造体。
- 樹脂部材は、熱硬化性樹脂であり、その硬化温度は、はんだ材料の固化温度と同じである、請求項1または2に記載の半導体実装構造体。
- 接合部材は、はんだバンプを形成するはんだ材料の融点よりも20℃以上低い融点の合金材料により形成されている、請求項1から3のいずれか1つに記載の半導体実装構造体。
- 第1電極と第2電極との間の距離Dに対する樹脂部材の高さHの比率(H1/D)が、15%以上である、請求項1から4のいずれか1つに記載の半導体実装構造体。
- 回路基板上における隣接する第2電極間に、個々の樹脂部材同士の接触を防止する突起部が形成されている、請求項1から5のいずれか1つに記載の半導体実装構造体。
- 個々の接合部材は、その外周面が環状の湾曲凹面形状となるように形成され、
少なくとも、接合部材の湾曲凹面全体に樹脂部材が充填されるように、接合部材の周囲に樹脂部材が配置されている、請求項1から6のいずれか1つに記載の半導体実装構造体。 - 半導体と回路基板との間において、それぞれの第1電極、第2電極、はんだバンプおよび樹脂部材を覆うように、別の樹脂材料が配置されている、請求項1から7のいずれか1つに記載の半導体実装構造体。
- 接合部材のはんだ材料は、Snと、Bi、In、AgおよびCuの群から選ばれる2種若しくはそれ以上の元素との組み合わせからなる合金組成のはんだ材料である、請求項1から8のいずれか1つに記載の半導体実装構造体。
- はんだバンプは、Sn−Ag−Cu系のはんだ材料であり、
はんだ材料は、Sn−Bi系のはんだ材料である、請求項1から9のいずれか1つに記載の半導体実装構造体。 - 回路基板上の第2電極上に、樹脂材料とはんだ材料とを含む混合ペーストを塗布し、
半導体の第1電極上に形成され、かつ、はんだ材料の融点より高い融点を有するはんだバンプを、混合ペーストを介して回路基板の第2電極上に配置し、
混合ペーストを加熱することで、樹脂材料とはんだ材料とを分離させ、はんだ材料およびはんだバンプを介して、第1電極と第2電極とを電気的に接続するとともに、少なくとも、はんだバンプとはんだ材料との接合部分およびはんだ材料を覆うように、個々のはんだ材料の周囲に樹脂材料を配置させるとともに、回路基板上における隣接する第2電極間に、個々の樹脂材料同士の接触を防止する空間を形成する、半導体実装構造体の製造方法。 - 回路基板上の第2電極上に、ペースト状のはんだ材料を塗布し、
半導体の第1電極上に形成され、かつ、はんだ材料の融点より高い融点を有するはんだバンプ上に、樹脂材料を塗布し、
半導体のはんだバンプ上の樹脂材料を、回路基板のはんだ材料上に配置し、
樹脂材料およびはんだ材料を加熱することで、はんだ材料およびはんだバンプを介して、第1電極と第2電極とを電気的に接続するとともに、少なくとも、はんだバンプとはんだ材料との接合部分およびはんだ材料を覆うように、個々のはんだ材料の周囲に樹脂材料を配置させるとともに、回路基板上における隣接する第2電極間に、個々の樹脂材料同士の接触を防止する空間を形成する、半導体実装構造体の製造方法。
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WO2010050185A1 (ja) | 2010-05-06 |
JPWO2010050185A1 (ja) | 2012-03-29 |
JP5557936B2 (ja) | 2014-07-23 |
US8450859B2 (en) | 2013-05-28 |
JP5204241B2 (ja) | 2013-06-05 |
US20110095423A1 (en) | 2011-04-28 |
CN101965632B (zh) | 2012-09-26 |
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