CN101582403A - 以夹在金属层之间的倒装管芯为特征的半导体封装 - Google Patents
以夹在金属层之间的倒装管芯为特征的半导体封装 Download PDFInfo
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- CN101582403A CN101582403A CNA2008101761748A CN200810176174A CN101582403A CN 101582403 A CN101582403 A CN 101582403A CN A2008101761748 A CNA2008101761748 A CN A2008101761748A CN 200810176174 A CN200810176174 A CN 200810176174A CN 101582403 A CN101582403 A CN 101582403A
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- 239000002184 metal Substances 0.000 title claims abstract description 154
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 154
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004806 packaging method and process Methods 0.000 claims abstract description 23
- 238000005538 encapsulation Methods 0.000 claims description 99
- 238000000034 method Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 241000272168 Laridae Species 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 241001133184 Colletotrichum agaves Species 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Abstract
根据本发明的实施例涉及用于半导体器件的倒装片封装,其特征在于夹在金属层之间的管芯。一个金属层包括通过焊球接触与管芯第一表面上的各个焊盘(例如,IC焊盘或MOSFET栅极或源极焊盘)电连接且热连接的引线框的一部分。其他金属层被构造为与管芯的相对面至少热连接。根据本发明的封装实施例显示出卓越的散热性能,同时避免了昂贵的引线接合。本发明的实施例特别适合于功率器件的封装。
Description
相关申请的交叉引用
本非临时专利申请要求2008年5月15日提交的美国临时专利申请No.61/053561的优先权,并在此引入其全部内容以作参考。
背景技术
图1示出了包封功率MOSFET管芯的常规封装的简化平面图。图1A示出了图1的该封装沿1A-1A’线的简化截面图。
具体地,常规功率MOSFET封装100包括具有顶表面并以栅极焊盘104和源极焊盘106为特征的功率MOSFET管芯102。栅极焊盘104被构造为通过接合线112与第一引线110电连接,源极焊盘106被构造为通过接合线116与第二引线114电连接。
管芯102的底表面以漏极焊盘108为特征。漏极焊盘通过导电性粘接材料120与下面的管芯焊盘118电连接。这种粘接材料120还是导热性的,以便将操作期间由MOSFET管芯产生的热量通过由管芯焊盘的下表面形成的散热器122传输到封装之外。还可以通过与管芯焊盘集成在一起的引线将热能传导到封装之外。
虽然图1、1A的封装是起作用的,但是仍存在一些缺点。一个缺点是需要进行焊盘或管芯表面和引线之间的引线接合。具体地,由于接合线材料通常由金构成,这是一种非常昂贵的商品,因此这种引线接合步骤是昂贵的。
由于需要将接合线弯曲(应变)然后通过一些力并以高精度在引线的端部处将接合线连接到管芯和小的目标区域上,因此进行引线接合步骤也是困难的。引线在应力下断裂或者引线端部的精确对准失败都会增加缺陷并降低生产量。在此步骤中将引线连接到管芯的力也可能会损伤管芯。
而且,源极和栅极接合线的连接限制了封装散发热能的能力。特别是,小体积的接合线仅提供了用于将热量传输到封装之外的小体积的导热性材料。
最后,由接合线提供的相对较小的截面会妨碍在管芯和引线之间建立低电阻的接触。为了建立电阻较小的接触而做的常规努力通常意味着使用更多的接合线,从而使上述成本问题加剧。而且,为了建立与管芯表面的低电阻接触而使用多针接合线需要多个连接步骤,其再次引起可能损伤管芯的危险。
使用长的和/或多条接合线作为到管芯的电连接可以引起其他缺点。例如接合线会引起较大的电感,其可能削弱MOSFET开关作用。并且,接合线会增加对功率IC的需要在内部集成电路中进行补偿的不受控的外部电感或阻抗。
因此,现有技术需要改进的封装设计以便呈现良好的热传导和低制造成本。
发明概述
根据本发明的实施例涉及用于半导体器件的封装,其以夹在金属层之间的倒装管芯为特征。一个金属层包括引线框的被配置用于通过焊料接触与管芯第一表面上的各个焊盘(例如,IC焊盘或MOSFET的栅极或源极焊盘)电连接且热连接的各部分。其他金属层被配置为至少与管芯的相对侧热连接。根据本发明的封装实施例显示出卓越的散热性能,同时避免了引线接合的费用。
下面将结合本文和附图更详细地描述本发明的这些和其他实施例以及其特征和一些潜在的优点。
附图说明
图1示出了常规功率MOSFET封装的简化平面图。
图1A示出了图1的常规封装沿线1A-1A’的简化截面图。
图2示出了根据本发明实施例的封装的简化平面图。
图2A示出了图2的封装实施例沿线2A-2A’的简化截面图。
图2B示出了根据本发明的封装的可选实施例的简化截面图。
图2C示出了根据本发明的封装的又一可选实施例的简化截面图。
图2D示出了根据本发明的封装的再一可选实施例的简化截面图。
图2DA示出了根据本发明的封装的还一可选实施例的简化截面图。
图2E-EA分别示出了根据本发明实施例的引线框实施例的平面和截面图。
图2FA-FB分别示出了根据本发明实施例的引线框的可选实施例的平面和截面图。
图2GA-GB分别示出了根据本发明实施例的引线框的可选实施例的平面和截面图。
图2H示出了根据本发明的引线框实施例的简化平面图。
图2IA-IB分别示出了根据本发明实施例的引线框的可选实施例的平面和截面图。
图2J示出了根据本发明的引线框实施例的简化平面图。
图2K示出了根据本发明的引线框实施例的简化平面图。
图2LA-LB分别示出了根据本发明实施例的引线框的可选实施例的平面和截面图。
图2M示出了根据本发明的引线框的实施例的简化平面图。
图2N示出了根据本发明的引线框的实施例的简化平面图。
图2O示出了根据本发明的引线框的实施例的简化平面图。
图3A示出了根据本发明的引线框的可选实施例的上金属层的简化平面图,其被配置为支撑多个管芯。
图3B示出了根据本发明的引线框的可选实施例的下金属层的简化平面图,其被配置为支撑多个管芯。
图3C示出了根据本发明的被配置为包封多个管芯的封装实施例的简化截面图。
图4示出了根据本发明实施例的引线框中多个管芯布置的简化平面图。
图5示出了根据本发明以叠置结构的多个管芯为特征的封装实施例的简化截面图。
图6示出了根据本发明的封装的可选实施例的简化截面图。
图7示出了根据本发明的封装的可选实施例的简化截面图。
具体实施方式
图2是根据本发明的封装实施例的简化平面图。图2A是图2的封装沿截面线2A-2A’的简化截面图。
封装200包括MOSFET管芯202,其具有以栅极焊盘204和源极焊盘206为特征的顶表面。MOSFET管芯202的底表面以漏极接触208为特征。
漏极接触208通过导电且导热的粘接材料220与下面的第一金属层224电连接。这种导电且导热材料的一个例子是焊料。在某一实施例中,第一金属层可以利用焊球提供预凸起或预先形成有可焊接接触的表面。
第一金属层224的成一体的突出延伸到塑料封装体的外部以提供用于与MOSFET漏极电接触的引线。露出封装体的第一金属层的下侧部分可以用作散热器。
封装200包括覆盖在管芯上面的第二金属层226。第二金属层的第一部分228通过焊料连接230与栅极焊盘204电连接。第二金属层的第二部分232通过多个焊料连接234与源极焊盘206电连接。上金属层226的部分228和232依次布置(route)为延伸到塑料封装体的外部,以用作连接栅极和源极的引线。该布置可以包括改变金属部分228和232的垂直高度以匹配第一金属层的高度。在特定实施例中,可以通过弯曲形成第二金属层的形状。在其他实施例中,可以以预先形成的形状提供第二金属层。
图2-2A的封装设计可以提供超出常规封装设计的许多优点。一个优点是在制造期间避免了引线接合。相反地,通过焊料接触提供管芯和第二金属层之间的接触,而不需要金属接合线的弯曲和精确对准。使用这种焊料接触取代引线接合减小了缺陷的发生率并降低了制造封装的总体成本。
本发明的实施例还提供了有利的电性能。例如,相对于接合线降低了金属层的电感从而提供了较小的电感,并且可以允许更快的开关速度。使用金属层取代窄的接合线还可以有利地对被封装包封的管芯提供电阻降低的接触。
图2-2A所示的封装实施例提供的另一可能优点是增强了散热能力。具体地,下金属层与管芯的漏极接触热连接,由此能够将热量通过引线传导到封装之外。并且,在某些实施例中,下金属层的一部分露出封装之外,由此用作到周围环境的散热器。
并且,上金属层也实质上通过焊料连接与管芯的较大面积热接触,特别是与管芯上表面上存在的源极焊盘。这种大面积接触进一步增强了热量通过引线从管芯向封装外到周围环境的流动。并且,在某些实施例中,上金属层的一部分露出封装之外,由此用作到周围环境的散热器。
虽然图2-2A的具体实施例示出了使用焊球从而仅与管芯的一侧建立电连接,但这并不是本发明必须的。根据可选实施例,可以采用焊球与管芯两侧上的触点建立电连接。
并且虽然图2-2A的具体实施例示出了通过焊料连接使下金属层与漏极接触且上金属层与栅极/源极的接触,但这并不是本发明必须的。本发明的可选实施例可以以下金属层接触管芯的源极和栅极、上金属层接触漏极为特征。这样的实施例在图2B的简化截面图中示出。此外,两个金属层都提供所期望的高热传导率和可靠性、低制造成本的特性。
并且,图2C示出了根据本发明的封装的另一实施例的简化截面图。在该特定实施例中,下金属层向上弯曲以接触上金属层的一部分,上金属层自身向下弯曲以延伸到封装体之外。图2C的实施例提供的优点在于确保第一金属层向上突出的部分保持可靠地埋置在封装的塑料体中。此外,图2C的设计提出了正方形或矩形轮廓的散热器,以便使在封装底部上暴露的下金属层的集成部分不会一直延伸到封装的侧面。
在将管芯封装到塑料封装体内之后,可以通过冲压穿过露出的引线将图2C的封装从周围的材料分离(singulated),以使引线的一部分延伸到封装体之外并可用于测试。根据可选实施例,可以通过切割工艺将封装从周围材料分离,使露出的引线与封装的表面齐平。
图2D示出了根据本发明封装的又一实施例的简化截面图。在本特定实施例中,第一和第二金属层被配置为从封装厚度的中间点凸出。由于可以使突出的引线在任一方向(向上或向下)上弯曲,并且可以根据封装最终放置的环境的需要形成各种形状(J形、鸥翼形、倒鸥翼形),因此这种构造为封装提供了充分的使用灵活性。
图2DA示出了根据本发明封装的又一实施例的简化截面图。本实施例示出了鸥翼形引线,其朝着设置在封装顶部的散热器向上突出。
图2E-2EA分别示出了根据本发明封装的又一实施例的简化平面图和截面图。图2E-2EA的封装包括仅设置在封装一个侧面上的突出引线。第一突出引线由位于封装中间厚度并通过焊料接触与管芯上的源极焊盘接触的部分下金属层形成。第二突出引线也由通过焊料接触与管芯上的栅极焊盘接触的部分下金属层形成。第三突出引线由部分上金属层形成,所述部分上金属层与管芯的漏极焊盘接触并在中间厚度的高度处在最终退出封装体之前向下弯曲。如图2E所示,上金属层可以包括允许穿通封装体塑料封装的小孔,由此有助于封装内上金属层的机械互锁。
到目前为止描述的实施例涉及包封具有三个端子(栅极、源极、漏极)的MOSFET器件的封装。但是,本发明不限于包封这种类型的管芯。根据本发明封装的可选实施例可以被配置为包封具有更少或更多端子的管芯。
例如,图2FA-B示出了根据本发明实施例的用于平面两端子器件(例如二极管)的引线框的平面图和沿线2F-2F’的截面图。引线框包括仅与管芯背面热连接的下金属层。上金属层的两个部分与管芯上侧面上的各触点电连接。
类似地,图2GA-B示出了根据本发明实施例的用于垂直两端子器件(例如二极管)的引线框的平面图和沿线2G-2G’的截面图。引线框包括与管芯背面上的触点电连接的下金属层和与管芯正面上的触点电连接的上金属层。
图2H示出了用于双器件封装的引线框的平面图,但是该双器件具有三个端子,其中两个连接到器件的相同部分。具体来说,下金属层与背面触点电连接,且上金属层限定了两个部分,每一个与正面触点电连接。图2H示出的特定封装是TO-220/247/251型封装,其特征在于标记孔(tag hole),该标记孔被配置为容纳螺钉以将封装紧固到支撑结构。其他实施例包括TO263/252型封装,其具有到塑料体的外部引线,其被弯曲或预先形成以接触(meet)漏极散热器的相同平面。
虽然刚刚描述的封装和引线框的实施例是为单个管芯设计的,但是本发明并非必须如此。根据本发明的可选实施例可以被配置为包封多个管芯。
例如,图2IA-B示出了根据本发明的引线框的实施例的简化平面图和沿线2I-2I’的截面图,其被配置为包封两个双管芯。在本特定实施例中,两个管芯共用用于公共背面触点的相同端子,并具有其正面上的分离的端子和触点。
图2J示出了根据本发明的引线框的实施例的简化平面图,其被配置为包封两个MOSFET管芯。在本特定实施例中,两个MOSFET管芯共用用于公共背面触点(漏极)的相同端子,并在管芯的正面上具有用于源极和栅极触点的分离的端子和接触。
虽然图2J的实施例示出了用于源极、漏极和栅极触点的每一个的具有单个端子的结构,但本发明并非必须如此。图2K示出了具有用于源极(S)和漏极(D)的多个端子的MOSFET管芯的引线框的简化平面图。
类似地,图2LA-B示出了具有用于两个MOSFET管芯中每一个的多个源极端子的引线框的简化平面图和截面图,该MOSFET管芯具有彼此隔离的漏极。与这些漏极接触的部分引线框通过连接条结构固定在一起,该连接条结构在铸模步骤之后被切断(例如通过冲压)。图2M示出了支撑两个管芯的引线框的简化平面图,其中该两个管芯具有与两个端子(D1、D2)接触的公共漏极和用于每个管芯的多个源极端子。
类似地,图2N示出了引线框另一实施例的平面图,该引线框的特征在于多个源极端子和各自具有夹子连接的多个漏极端子,并且还包括连接条连接,该连接条连接在分离期间和铸模之后从周围的金属基体切断。图2O示出了包封多个MOSFET管芯的引线框的另一实施例的简化平面图,该MOSFET管芯每一个具有成组的漏极端子对并且还包括连接条。
虽然目前为止所述的实施例涉及被配置为包封相同类型管芯的引线框和封装,但这也不是本发明所必须的。可选实施例可以被配置为包封不同管芯类型,例如MOSFET和集成电路(IC)。
例如,图3A-B示出了根据本发明可选实施例的引线框300的平面图。图3A示出了上金属层302和三个被封装管芯304、306和308的平面图,而图3B示出了下金属层310和被封装管芯304、306和308的平面图。图3C示出了简化截面图。
引线框的上金属层302限定了与被包封管芯上表面上的各个焊盘接触的引线。例如,管芯304代表在其上表面上具有许多触点的IC管芯。因此,引线框的上金属层302包括在这些焊盘上方延伸的多个引线(no.5-17)。并且插入的焊料接触312提供了与管芯的必要的电连接和热连接。
此外,引线框的上金属层302的引线不限于接触特定尺寸的IC管芯。因此,如图3A所示,这些引线包括两组焊料触点以便提供占据更大覆盖区的IC管芯。
相反,管芯306和308是在其每个顶表面上仅具有栅极焊盘和更大的源极焊盘的MOSFET。因此,上金属层仅包括用于每个MOSFET管芯的两个分离的部分,其在相应的栅极/源极焊盘上方延伸并通过插入的焊料触点312与每个管芯热连接和电连接。具体地,上金属部分330接触MOSFET管芯306的栅极焊盘(引线no.4),且更大的上金属部分332接触管芯306的源极焊盘(引线no.33-36)。
虽然不是必须的,但是在本特定实施例中,更大的上金属部分332包括限定小孔333的图案的栅格状结构。这些小孔降低了更大的金属部分中的热应力,该热应力是由响应于封装内部热环境改变的收缩和膨胀而引起的。
虽然图3A实施例的小孔是方形的,但这并不是本发明所必须的。可选实施例可以根据特定应用以限定其他形状小孔的金属层为特征,包括但不限于圆形或多边形。
类似地,上金属层的较大部分340允许与MOSFET管芯308的源极焊盘热接触且电接触(引线no.21-27)。在图3A-B的特定实施例中,上金属层的相同(较宽的)部分(相应于引线no.17)提供了与IC和MOSFET管芯308的栅极焊盘的公共接触。
上金属层302特征在于单独引线(no.18-20和32)和成组引线(no.1-3和28-31)。如下面具体描述的,引线1-3、28-31和32通过下金属层与MOSFET管芯下侧上的漏极焊盘电连接。
如图3C的截面图所示,在从封装体露出之前,从引线框300的上金属层延伸的引线向下弯曲,以便使其最终从封装的厚度的底部突出。但是,这并不是本发明所必须的。在其他实施例中,上金属层可以在封装侧面的上部露出,以便如结合图2D所描述的在各个方向上弯曲。
图3B所示的下金属层348的结构比上金属层简单。在某些实施例中,IC管芯304下面的下金属层的部分350完全不与IC管芯电连接。因此,部分350不与任何引线接触,但在封装的底部露出以提供散热器。在需要IC接地并连接到引脚的某些实施例中,通过连接来提供电连接,在本例中,通过连接350到图3A中的引脚5来提供电连接。
在两个或多个管芯之间需要连接的特定实施例中,通过在适当地构图且连续的引脚上具有两个(多个)球接触位置来提供连接。图3A中的引脚17就是这样的例子,其连接MOSFET的栅极和IC。
下金属层的部分352与MOSFET管芯306下侧上的漏极焊盘电连接且热连接。区域352a向上微凸(jog)以便接触上金属层的成组的引脚1-3和单独引脚32,由此提供与MOSFET管芯306的漏极的接触。下金属层中的这些向上微凸还用于提供塑料封装体的封装中的层的机械互锁。下金属部分352的下侧还露出封装的下侧以提供散热器。
下金属层的部分354与MOSFET管芯308下侧上的漏极焊盘电连接且热连接。部分354a向上微凸以便接触上金属层的成组引脚28-31和引脚18,由此提供与MOSFET管芯308的漏极的接触。下金属层中的这些向上微凸还用于提供塑料封装体的封装中的层的机械互锁。下金属部分354的下侧还露出封装的下侧以提供散热器。
在图3A-B的封装的特定实施例中,引脚no.18用于提供与MOSFET 308漏极的散热器的安装和电连接。在本实施例中引脚no.19和20是非连接引脚,但在其他实施例中可以用作用于热连接和电连接的备用位置。
刚刚描述的引线框实施例提供了一些优点。一个优点是包封不同结构和尺寸的管芯的易于获得的适应性。例如,虽然示出MOSFET管芯占据了栅格状下金属部分上大部分的可用面积,但这并不是必须的。图3A-B所示的引线框的实施例可以被配置为包封占据较小覆盖面积或包封在上金属部分内适用的不同覆盖面积的MOSFET管芯。在一些这样的实施例中,特定接触(例如栅极)的位置可以是固定的,而其他接触(例如源极)的位置可以根据管芯的尺寸和形状在空间上变化。
根据本发明实施例的从封装体突出用作引脚的引线框金属层的部分可以在封装内部发挥作用,以便根据应用需要在安装在相同水平面上的两个或多个独立管芯之间提供信号传送功能。例如,图4示出了实施例的简化示意图,其中IC管芯401和MOSFET管芯402通过具有焊球连接的连续引脚而被连接。此外,图4示出了根据一些实施例的该连续引脚连接可以延伸成为部分400并进而延伸到部分404,其在IC管芯402和MOSFET管芯406上的各接触之间提供连续的信号路径。在一些实施例中,部分404延伸作为突出的引脚部分408。
虽然目前为止所示的实施例描述了封装和引线框被配置为在相同水平面中包封设置有信号路径的多个管芯,但这并不是本发明所必须的。根据本发明的封装和引线框的可选实施例可以以垂直叠层定向或其他定向的多个管芯为特征。
例如,图5示出了被配置为包封两个倒装片管芯的封装的实施例的简化截面图。在引线框上金属层502的下侧上支撑第一倒装片管芯500。在引线框下金属层506上支撑第二倒装片管芯504。管芯500和504表面上的触点通过焊球508彼此电连接。第一管芯500表面上的其他触点与中间金属层510电接触。
除叠层的管芯结构之外,图5的实施例的几个方面值得注意。首先,图5的封装在其两侧上露出散热器。一个这种散热器可以与下面的PC板热连接,而另一个散热器与周围环境热连接。应当理解的是,这种多个散热器的使用还可以用于前述一个或多个实施例。
第二,根据本发明的实施例不限于使用两个或任意数目的多个金属层,或不限于仅集成两个管芯。而是,本发明的实施例可以使用夹有任意期望数目的管芯的多个金属层。
如根据图3A-C所述,根据本发明实施例的引线框通过允许在各种金属层上支撑多种尺寸的管芯而为封装设计者提供了灵活性。根据本发明的实施例,还可以通过在夹层结构中组合多个模块来实现封装设计的更进一步的灵活性。
例如,图6示出了封装600,如图所示,图6的封装包括夹在第一和第二金属层604和606之间的第一倒装片管芯602。多芯片模块(MCM)的制造通过集成模块609来完成,模块609包括本身夹在金属层612和614之间的第二倒装片管芯610。允许以类似于拼接(puzzle)互锁片的方式由多个被夹着的管芯组件来组装该封装,这对于特定需要的封装设计提供了充分的额外灵活性。
图7示出了根据本发明封装再一实施例的简化截面图,其由多个较小元件形成。具体来说,封装包括这样的管芯,该管芯具有在同一平面中通过焊球与夹层结构的金属层之一接触的互连和信号路径(例如,通过阴影的焊球和FC DIE 3和FC DIE 4之间的下金属层)。封装还包括这样的管芯,该管芯具有利用焊球接触(例如通过阴影焊球,位于FC DIE 1和FC DIE 2之间)的彼此之间的信号路径垂直互连。在该封装中,夹层结构的下金属层可以保持在下平面中以便建立与支撑垂直连接的管芯之一的下金属层的接触,或者可以向上弯曲,以便建立与上金属层的接触,所述上金属层接触垂直连接的管芯的上部。图7的封装包括两侧上的散热器,其中上侧具有多个散热器。
根据本发明的实施例不限于包封特定类型的管芯。但是,诸如功率器件的某些类型的管芯特别适合于根据本发明的封装。就本申请而言,术语“功率器件”应当理解为是指在功率电子电路中用作开关或整流器的半导体器件。其包括但不限于分立器件,例如二极管、功率MOSFET、隔离栅双极晶体管(IGBT)和用在分立器件的模拟或数字控制中的功率集成电路。
在组合中,功率器件通常被用于提供功率管理功能,例如电源、电池充电控制系统。具有平面或垂直结构的功率分立器件可以处理从几毫瓦到几十千瓦的功率。对于上述封装而言,典型的功率器件可以在约500W和5mW之间操作。在关断状态中,在从约几伏特至高达约2000伏特的电压处会发生反向击穿。功率器件的操作电流可以在几毫安到几百安的范围内。
虽然上面已经全面描述了具体实施例,但可以使用各种改变、可选结构和等效结构。因此,上面的描述和说明不应限制由所附权利要求限定的本发明的范围。
Claims (33)
1、一种用于半导体器件的封装,该封装包括:
第一金属层,其被配置为与功率器件管芯热连接;以及
第二金属层,其被设置在功率器件管芯的与所述第一金属层相反的一侧上,所述第二金属层被配置为通过焊球接触与功率器件管芯表面上的焊盘热连接和电连接,第一金属层或第二金属层包括从封装功率器件管芯、焊球接触以及第一和第二金属层的至少一部分的塑料封装体突出的集成引线。
2、根据权利要求1的封装,其中第一金属层还被配置为与功率器件管芯电连接。
3、根据权利要求2的封装,其中第一金属层被配置为通过第二焊球接触与功率器件管芯电连接。
4、根据权利要求1的封装,其中第一金属层的一部分露出塑料封装体以形成散热器。
5、根据权利要求1的封装,其中第二金属层的一部分露出塑料封装体以形成散热器。
6、根据权利要求1的封装,还包括第二功率器件管芯,其被配置为与第二金属层的一部分电连接。
7、根据权利要求6的封装,其中第二金属层的同一部分被配置为与第一功率器件管芯和第二功率器件管芯电连接。
8、根据权利要求7的封装,其中第二金属层的所述同一部分与第一金属层垂直电连接。
9、根据权利要求7的封装,其中第一功率器件管芯是MOSFET且第二金属层的所述同一部分被配置为与第一功率器件管芯的栅极电连接。
10、根据权利要求6的封装,其中第二金属层被配置为在固定位置处容纳焊球接触,并根据第一功率器件管芯的大小或形状在不同位置处容纳到第一功率器件管芯的其他焊球接触。
11、根据权利要求6的封装,还包括第三功率器件管芯,其设置在第二管芯之上或之下并具有通过焊球与第二功率器件管芯的焊盘电连接的焊盘。
12、根据权利要求1的封装,其中功率器件管芯包括MOSFET管芯,以及第二金属层包括被配置为与MOSFET管芯表面上的栅极焊盘电连接的第一部分和被配置为与MOSFET管芯表面上的源极焊盘电连接的第二部分。
13、根据权利要求12的封装,其中第一金属层被配置为与MOSFET管芯的第二表面上的漏极热连接且电连接。
14、根据权利要求12的封装,其中引线与第二金属层集成在一起。
15、根据权利要求1的封装,其中功率器件管芯包括集成电路(IC)管芯,以及第二金属层包括被配置为与所述IC管芯表面上的相应焊盘电连接的多个部分。
16、根据权利要求15的封装,其中第一金属层被配置为与所述IC管芯的第二表面电连接。
17、根据权利要求1的封装,其中第二金属层的一部分限定了小孔。
18、一种用于半导体器件的封装,该封装包括:
第一金属层,其被配置为与第一功率器件管芯的第一侧至少热连接;
第二功率器件管芯,其位于第一功率器件管芯之上或之下,并通过焊球接触与第一功率器件管芯的第二侧电接触;以及
第二金属层,其设置在第二功率器件管芯的与第一功率器件管芯相反的一侧上,所述第二金属层被配置为与第二功率管芯至少热连接,第一金属层或第二金属层包括集成引线,该集成引线从封装功率器件管芯、焊球接触以及第一和第二金属层的至少一部分的塑料封装体突出,其中第一功率器件管芯或第二功率器件管芯与第一金属层或第二金属层电连接。
19、根据权利要求18的封装,其中第一功率器件管芯通过第二焊球接触与第一金属层电连接。
20、根据权利要求18的封装,其中第一功率器件管芯通过第二焊球接触与位于第一和第二金属层之间的第三金属层电连接。
21、根据权利要求18的封装,其中第一金属层的一部分露出塑料封装体以形成散热器。
22、根据权利要求18的封装,其中第二金属层的一部分露出塑料封装体以形成第二散热器。
23、一种封装半导体器件的方法,该方法包括:
提供第一金属层,其被配置为与功率器件管芯的第一表面至少热连接;
提供第二金属层,其被配置为通过焊球接触与功率器件管芯的与所述第一侧相反的第二表面热连接且电连接;以及
在塑料封装内封装该管芯、焊球和第一与第二金属层的至少一部分以形成封装体。
24、根据权利要求23的方法,其中提供第一金属层从而还与功率器件管芯电连接。
25、根据权利要求23的方法,其中封装功率器件管芯露出了第一金属层的一部分作为散热器。
26、根据权利要求23的方法,其中封装功率器件管芯露出了第二金属层的一部分作为第二散热器。
27、根据权利要求23的方法,还包括向第二金属层的平面外弯曲第二金属层的一部分以形成露出封装体的引线。
28、根据权利要求23的方法,其中第二金属层具有向第二金属层的平面外弯曲的部分,从而形成露出封装体的引线。
29、根据权利要求23的方法,其中第一金属层具有被配置为与第二功率器件管芯的第一表面至少热连接的部分;以及
第二金属层包括被配置为通过焊球接触与第二功率器件管芯的与第一表面相对的第二表面上的焊盘电连接且热连接的部分。
30、根据权利要求29的方法,其中所述部分还与第一功率器件管芯的第二表面上的焊盘电连接。
31、根据权利要求29的方法,其中第一功率器件管芯包括MOSFET管芯,且所述部分与MOSFET管芯的栅极电连接。
32、根据权利要求29的方法,还包括提供第三功率器件管芯,其设置在第二功率器件管芯之上或之下并通过第二焊球接触与第二功率器件管芯电连接。
33、一种形成用于半导体器件的封装的方法,该方法包括:
提供第一金属层,其被配置为与第一功率器件管芯的第一侧至少热连接;
提供第二功率器件管芯,其位于第一功率器件管芯之上或之下并通过焊球接触与第一功率器件管芯的第二侧电接触;以及
提供第二金属层,其设置在第二功率器件管芯的与第一功率器件管芯相反的一侧上,所述第二金属层被配置为与第二功率器件管芯至少热连接,第一金属层或第二金属层包括集成引线,其从封装功率器件管芯、焊球接触和第一与第二金属层的至少一部分的塑料封装体突出,其中第一功率器件管芯或第二功率器件管芯与第一金属层或第二金属层电连接。
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102171825A (zh) * | 2011-04-29 | 2011-08-31 | 华为技术有限公司 | 电源模块及其封装集成方法 |
CN102194785A (zh) * | 2009-12-18 | 2011-09-21 | Nxp股份有限公司 | 引线框电路及其方法 |
CN102201449A (zh) * | 2011-05-27 | 2011-09-28 | 电子科技大学 | 一种功率mos器件低热阻封装结构 |
CN102456655A (zh) * | 2010-10-15 | 2012-05-16 | 三垦电气株式会社 | 半导体模块 |
CN103594448A (zh) * | 2013-11-15 | 2014-02-19 | 杰群电子科技(东莞)有限公司 | 一种引线框架 |
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CN108133915A (zh) * | 2017-12-21 | 2018-06-08 | 乐健科技(珠海)有限公司 | 功率器件内置且双面散热的功率模组及其制备方法 |
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US11569193B2 (en) | 2020-10-26 | 2023-01-31 | Samsung Electronics Co., Ltd. | Semiconductor package including semiconductor chips |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2010004609A1 (ja) * | 2008-07-07 | 2011-12-22 | 三菱電機株式会社 | 電力用半導体装置 |
US8168490B2 (en) | 2008-12-23 | 2012-05-01 | Intersil Americas, Inc. | Co-packaging approach for power converters based on planar devices, structure and method |
US8673687B1 (en) * | 2009-05-06 | 2014-03-18 | Marvell International Ltd. | Etched hybrid die package |
US8178954B2 (en) * | 2009-07-31 | 2012-05-15 | Alpha & Omega Semiconductor, Inc. | Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors |
TWI453831B (zh) | 2010-09-09 | 2014-09-21 | 台灣捷康綜合有限公司 | 半導體封裝結構及其製造方法 |
JP5921072B2 (ja) * | 2011-03-05 | 2016-05-24 | 新電元工業株式会社 | 樹脂封止型半導体装置 |
US8310098B2 (en) | 2011-05-16 | 2012-11-13 | Unigen Corporation | Switchable capacitor arrays for preventing power interruptions and extending backup power life |
ITMI20111213A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo elettronico a semi-ponte con dissipatore di calore ausiliario comune |
US8723311B2 (en) * | 2011-06-30 | 2014-05-13 | Stmicroelectronics S.R.L. | Half-bridge electronic device with common heat sink on mounting surface |
ITMI20111214A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo di potenza a spessore ridotto |
ITMI20111218A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo di potenza ad elevata velocita? di commutazione |
ITMI20111208A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Sistema con dissipatore di calore stabilizzato |
ITMI20111216A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo elettronico di potenza ad elevata dissipazione di calore e stabilita? |
ITMI20111217A1 (it) * | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Sistema contenitore/dissipatore per componente elettronico |
ITMI20111219A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Sistema con dissipatore di calore condiviso |
US9041183B2 (en) * | 2011-07-19 | 2015-05-26 | Ut-Battelle, Llc | Power module packaging with double sided planar interconnection and heat exchangers |
US9601417B2 (en) * | 2011-07-20 | 2017-03-21 | Unigen Corporation | “L” shaped lead integrated circuit package |
US20160277017A1 (en) * | 2011-09-13 | 2016-09-22 | Fsp Technology Inc. | Snubber circuit |
JP5857755B2 (ja) * | 2012-01-24 | 2016-02-10 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
US9698143B2 (en) | 2012-09-07 | 2017-07-04 | Fairchild Semiconductor Corporation | Wireless module with active devices |
CN103681557B (zh) * | 2012-09-11 | 2017-12-22 | 恩智浦美国有限公司 | 半导体器件及其组装方法 |
KR101367065B1 (ko) | 2012-10-30 | 2014-02-24 | 삼성전기주식회사 | 전력 모듈 패키지 |
US9589929B2 (en) | 2013-03-14 | 2017-03-07 | Vishay-Siliconix | Method for fabricating stack die package |
US9966330B2 (en) * | 2013-03-14 | 2018-05-08 | Vishay-Siliconix | Stack die package |
US9070657B2 (en) | 2013-10-08 | 2015-06-30 | Freescale Semiconductor, Inc. | Heat conductive substrate for integrated circuit package |
US9559064B2 (en) * | 2013-12-04 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in package-on-package structures |
FR3023059B1 (fr) * | 2014-06-25 | 2018-01-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Circuit integre comportant un dissipateur de chaleur |
US9431319B2 (en) | 2014-08-01 | 2016-08-30 | Linear Technology Corporation | Exposed, solderable heat spreader for integrated circuit packages |
US9425304B2 (en) | 2014-08-21 | 2016-08-23 | Vishay-Siliconix | Transistor structure with improved unclamped inductive switching immunity |
US10319674B2 (en) * | 2014-10-29 | 2019-06-11 | Infineon Technologies Americas Corp. | Packaged assembly for high density power applications |
US10685904B2 (en) | 2014-11-21 | 2020-06-16 | Delta Electronics, Inc. | Packaging device and manufacturing method thereof |
US10535587B2 (en) * | 2015-02-04 | 2020-01-14 | Stmicroelectronics S.R.L. | Integrated electronic device having a dissipative package, in particular dual side cooling package |
WO2017054855A1 (en) * | 2015-09-30 | 2017-04-06 | Agile Power Switch 3D - Integration Apsi3D | A semiconductor power device comprising additional tracks and method of manufacturing the semiconductor power device |
WO2017091152A1 (en) * | 2015-11-23 | 2017-06-01 | Agency For Science, Technology And Research | Wafer level integration of high power switching devices on cmos driver integrated circuit |
US10586757B2 (en) | 2016-05-27 | 2020-03-10 | Linear Technology Corporation | Exposed solderable heat spreader for flipchip packages |
KR101652423B1 (ko) * | 2016-07-07 | 2016-08-30 | 제엠제코(주) | 핑거 클립 본딩 반도체 패키지 |
JP6661565B2 (ja) * | 2017-03-21 | 2020-03-11 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2021068717A (ja) * | 2018-02-13 | 2021-04-30 | 日立Astemo株式会社 | 電子制御装置 |
JP7137955B2 (ja) * | 2018-04-05 | 2022-09-15 | ローム株式会社 | 半導体装置 |
US10872848B2 (en) * | 2018-10-25 | 2020-12-22 | Infineon Technologies Ag | Semiconductor package with leadframe interconnection structure |
US11476232B2 (en) | 2019-03-25 | 2022-10-18 | Analog Devices International Unlimited Company | Three-dimensional packaging techniques for power FET density improvement |
JP2022144247A (ja) * | 2021-03-18 | 2022-10-03 | 株式会社デンソー | 半導体モジュール、および、これを用いた電子装置 |
JP7470086B2 (ja) * | 2021-09-13 | 2024-04-17 | 株式会社東芝 | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6191478B1 (en) * | 1999-06-07 | 2001-02-20 | Agilent Technologies Inc. | Demountable heat spreader and high reliability flip chip package assembly |
US6731000B1 (en) * | 2002-11-12 | 2004-05-04 | Koninklijke Philips Electronics N.V. | Folded-flex bondwire-less multichip power package |
JP2005159238A (ja) * | 2003-11-28 | 2005-06-16 | Renesas Technology Corp | 半導体装置 |
JP2005302951A (ja) * | 2004-04-09 | 2005-10-27 | Toshiba Corp | 電力用半導体装置パッケージ |
CN100390974C (zh) * | 2004-08-20 | 2008-05-28 | 清华大学 | 一种大功率半导体器件用的大面积散热结构 |
US7705476B2 (en) * | 2007-11-06 | 2010-04-27 | National Semiconductor Corporation | Integrated circuit package |
US7619303B2 (en) * | 2007-12-20 | 2009-11-17 | National Semiconductor Corporation | Integrated circuit package |
-
2008
- 2008-08-05 US US12/186,342 patent/US8358017B2/en active Active
- 2008-11-14 CN CN2008101761748A patent/CN101582403B/zh active Active
-
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- 2009-05-13 JP JP2009116937A patent/JP2009278103A/ja active Pending
-
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- 2012-12-17 US US13/716,419 patent/US20130105974A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
US20090283919A1 (en) | 2009-11-19 |
JP2009278103A (ja) | 2009-11-26 |
US20130105974A1 (en) | 2013-05-02 |
CN101582403B (zh) | 2012-04-04 |
US8358017B2 (en) | 2013-01-22 |
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