CN101467249B - 阵列型封装及其制造方法 - Google Patents
阵列型封装及其制造方法 Download PDFInfo
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- CN101467249B CN101467249B CN2007800212959A CN200780021295A CN101467249B CN 101467249 B CN101467249 B CN 101467249B CN 2007800212959 A CN2007800212959 A CN 2007800212959A CN 200780021295 A CN200780021295 A CN 200780021295A CN 101467249 B CN101467249 B CN 101467249B
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Abstract
一种包装一个或多个半导体器件的阵列型封装及其制造方法。该封装包括绝缘衬底,绝缘衬底具有对置的第一侧面和第二侧面以及从第一侧面延伸到第二侧面的居中设置的孔,第一和第二侧面具有多个导电过孔。散热块具有贯穿该孔的中间部分、与衬底的第一侧面相邻的第一部分、和与衬底的第二侧面相邻的对置的第二部分,第一部分的横截面面积大于孔的横截面面积。一个或多个半导体器件接合到散热块的第一部分上且与导电过孔相互电连接。具有第一侧面和对置的第二侧面的散热器与半导体器件隔开且与散热块大致平行,由此半导体器件设置在散热器和散热块之间。模制树脂封装半导体器件和至少衬底的第一侧面、散热块的第一部分和散热器的第一侧面。
Description
技术领域
本发明涉及用于包装一个或多个半导体器件的封装,且更特别地涉及具有衬底基座和散热块的模制塑料球栅阵列封装。
背景技术
增强包装半导体器件的基于衬底的封装的热性能仍是一个挑战。典型的基于衬底的封装例如平面栅格阵列(1and grid array)封装和球栅阵列封装通常通过金属过孔散出热量。但是,该过孔的小表面积限制了散热的量。已知如授予Medeiros等人的美国专利No.5,111,277所公开的通过将散热片铜焊到贯穿封装基座的孔上来提高表面安装封装的散热。包括散热片的封装衬底也在授予Mahulikar等人的美国专利No.5,629,835中公开。
在授予Mahulikar的美国专利No.5,559,306中公开了一种通过降低自感和互感系数而提高模制塑料封装的电特性的方法。平行金属板设置在封装主体内,半导体器件设置在这些平行金属板之间。
但是,仍然存在对可低成本大量制造的具有改进散热的基于衬底的封装的需要。
发明内容
根据本发明的第一实施例,提供一种包装一个或多个半导体器件的阵列型封装。该封装包括绝缘衬底,该绝缘衬底具有对置的第一和第二侧面、多个导电过孔和从该第一侧面延伸到第二侧面的居中设置的孔。散热块具有贯穿该孔的中间部分、与该衬底的第一侧面相邻的第一部分和与该衬底的第二侧面相邻的对置的第二部分,第一部分的横截面面积大于孔的横截面面积。一个或多个半导体器件接合到该散热块的第一部分上且与该导电过孔相互电连接。具有第一侧面和对置的第二侧面的散热器与该半导体器件隔开且与该散热块大致平行,由此该半导体器件设置在该散热器和散热块之间。模制树脂封装该半导体器件以及至少该衬底的第一侧面、该散热块的第一部分和该散热器的第一侧面。
根据本发明的第二实施例,提供一种散热块阵列,该散热块阵列包括绝缘衬底和多个相互连接的散热块,该绝缘衬底具有对置的第一和第二侧面以及设置成阵列的多个孔。每个散热块具有由中间部分分离的第一部分和第二部分,其中该中间部分贯穿所述孔之一且该第一部分具有比该孔的周长大的周长。
根据本发明的第三实施例,提供一种用于制造用于包装一个或多个半导体器件的阵列型封装的方法。该方法包括以下步骤:(a)提供包含绝缘衬底和多个相互连接的散热块的散热块阵列,该绝缘衬底具有多个孔,该多个相互连接的散热块具有由中间部分分开的对置的第一部分和第二部分,该中间部分贯穿该多个孔中的一个,其中该第一部分具有比该孔的周长更大的周长,且多个连接杆(tie bar)从该第一部分的周长伸出,且其中从一个散热块伸出的连接杆与从相邻散热块伸出的至少一个其他连接杆在相互交叉点处交叉;(b)将半导体器件接合到第一部分上且将半导体器件与该绝缘衬底的第一侧面上的导电过孔相互电连接,该导电过孔通过所述绝缘衬底延伸到该绝缘衬底的对置第二侧面;(c)提供具有多个连接杆的散热器阵列,该多个连接杆从其周长延伸,其中从一个散热器上延伸的连接杆与从相邻散热器延伸的至少一个其他连接杆在相互交叉点交叉;(d)将该散热块的连接杆接合到该散热器的连接杆上,使得该半导体器件设置在该散热块中的一个和该散热器中的一个之间;和(e)将该半导体器件以及该散热器和该散热块的至少一部分封装在模制树脂中。
附图说明
将在附图和描述中说明本发明一个或多个实施例的细节。本发明的其他特征、目标和优点将由于该说明、附图和权利要求而变得清楚。
图1是本发明的球栅阵列封装的局部剖视俯视平面图。
图2是图1的球栅阵列封装的剖视图。
图3是用于制造本发明封装所使用的连接有散热块的衬底阵列的俯视平面图。
图4是图3的阵列的剖视图。
图5是用于制造本发明封装所使用的散热器阵列的俯视平面图。
图6是图5的阵列的剖视图。
图7示出了根据本发明制造的封装阵列的剖视图。
图8示出了使散热块连接杆的一部分部分变薄,以便于切割(singulation)。
图9-11示出了用于将散热器连接杆锁定到散热块连接杆上的机构。
图12示出了与根据本发明一个实施例的封装一起使用的引线框。
图13是图12的引线框的顶视透视图。
图14是图12的引线框的仰视透视图。
图15a和15b示出了与根据本发明另一个实施例的封装一起使用的引线框。
图16示出了与根据本发明又一个实施例的封装一起使用的引线框。
在各个附图中的相同标号和标记表示相同的元件。
具体实施方式
对于本专利申请,“散热块(heat slug)”或“散热片”定义为一种金属构件,该金属构件具有比聚合物模制树脂的导热系数更大的导热系数和比封装在模制树脂中的半导体器件的厚度更大的最大厚度。“散热器(heat spreader)”定义为一种金属构件,该金属构件具有比聚合物模制树脂的导热系数更大的导热系数和等于或小于封装在模制树脂中的半导体器件的厚度的最大厚度。
图1示出了根据本发明的阵列型封装10的俯视平面图。部分剖开该封装以示出该封装的构件。图2以剖面表示示出该阵列型封装。这里所公开的全部阵列型封装可封装一个或多个集成电路器件(例如硅基集成电路器件)和一个或多个无源设备(例如电阻器、电感器和电容器)。多个器件可以成相邻或层叠关系。
参考图1和2,绝缘衬底12具有对置的第一侧面14和第二侧面16。多个导电过孔18贯穿该绝缘衬底。居中设置的孔20也贯穿该绝缘衬底12。该孔可以是任何形状,例如正方形、矩形或圆形,且具有第一周长。
散热块22由绝缘衬底12的第一侧面14支撑。该散热块22具有由中间部分28分离的第一部分24和对置的第二部分26。该中间部分28的尺寸适合通过该居中设置的孔20装配,并且优选地具有有限的间隙。该第一部分24的周长大于居中设置的孔20的周长,并形成覆盖在该第一表面14上的凸缘。
使用合适的芯片连接粘合材料,例如铅基或金基焊料或金属填充环氧树脂,将一个或多个半导体器件30或例如混合电路中的半导体器件和无源设备的组合粘合到该第一部分24上。该一个或多个半导体器件30通过如用于带式自动接合的小直径接合线32或薄金属箔条与导电过孔18相互电连接。
具有第一侧面36和对置的第二侧面38的散热器34与一个或多个半导体器件30间隔开,其中第一侧面36大致平行于散热块22的第一侧面24。如图2所示,第一侧面36和第一侧面24形成两个平行导电板的相邻侧面,其中在平行板之间设置有一个或多个半导体器件30。
模制树脂40封装一个或多个半导体器件30、散热块22的第一部分24和散热器34的第一侧面36。与该绝缘衬底12的第二侧面16相邻的导电过孔18与形成在外部电路例如印刷电路板上的电路迹线相互电连接。可以通过包括使用焊球42的合适装置实现相互电连接。该焊球全部具有基本相同直径,使得每个焊球的与第二侧面16相对的点和与该第二侧面16相对的所有其他点大致共面。该焊球典型地由例如重量63%的锡/37%的铅的低熔化温度铅基焊料形成。优选地,该散热块22的第二部分26也与该焊球的相对点共面。然后该第二部分可以焊接到封装10外部的散热片或接地。
图3-6示出了对于该阵列型包装的制造有用的构件。图3以俯视平面图示出了散热块阵列44,且图4以剖视图示出散热块阵列44。该散热块阵列44包括多个散热块22,每个散热块22具有由中间部分28分开的第一部分24和第二部分26。该散热块阵列44也包括绝缘衬底12,该绝缘衬底具有对置的第一侧面14和第二侧面16以及贯穿该绝缘衬底的居中设置的孔20。该散热块22的中间部分28贯穿每个孔20。第一部分16具有比该孔20的周长更大的周长。散热块连接杆46从该第一部分24的周边伸出,且从一个散热块伸出的连接杆与从相邻散热块伸出的至少一个连接杆在相互交叉点48处交叉。如图8最优示出的,为便于切割该连接杆46的厚度可在相互交叉点48处减小。
再参考图4,该散热块22通常通过环氧树脂或粘合带粘合到绝缘衬底12上。该散热块优选地由例如铜合金的导热金属形成,且可以被预先镀有例如镍上的金或钯层的导线可粘合材料。参考图5和6,散热器阵列50具有从其周边延出的多个散热器连接杆52。来自相邻散热器的连接杆在连接杆相互交叉点54处连接在一起,在该相互交叉点54处具有减小的厚度,以便于切割。
该连接杆一般包括镦制部分(upset portion)56,使得第二侧面38凸出足够的量以在利用模制树脂封装后暴露,并为用于引线接合的导线提供隔离间隙(standoff clearance)。该暴露的第二侧面38可以是包括圆形或正方形的任何形状。该散热器由具有高导热系数的任何金属例如铜、铝和它们的合金形成。该金属可涂覆有另一种材料以增强标记对比。对于铝合金散热器,黑阳极处理是最优选的。可部分蚀刻该散热器34的外周部58以形成阶梯结构,从而改善到该模制树脂的机械锁定。
图7以剖面表示示出了根据本发明的阵列型封装的阵列60。例如通过粘合结合剂62将散热器连接杆52粘合到散热块连接杆46上而将散热器阵列50粘合到散热块阵列44上。这样该阵列可在利用模制树脂封装之前或之后进行切割。
参考图9-11,散热器连接杆190可具有凸出部192以增加距用于引线结合的导线的支座间隙。该凸出部192也用于将该散热器对准并锁定在散热块连接杆194上的适当位置。孔196可以形成在该散热块连接杆194中以进一步增强对准和锁定。这些凸出部典型地在化学蚀刻工艺中形成或在镦制工艺中通过压花/冲压形成。虽然该装配工艺描述了该散热块阵列和散热器阵列一起模制并随后被切割,但是在用熔化的树脂封装以及将单个散热块和单个散热器放置在用于引线接合和封装的单个模腔中的拾取和放置工艺之前进行散热器和散热块的切割也在本发明的范围内。
图12以剖视表示示出了本发明的可替换实施例,其中该封装200包括散热块202,该散热块起引线框的功能。该引线框202以顶视透视图在图13中示出并以仰视透视图在图14中示出。该引线框包括面向表面伸出部204和面向芯片伸出部206。另外,该引线框包括多个连接杆208,该连接杆典型地从引线框的角部向外伸出然后向下伸出。再参考图12,该引线框202包括外切面向表面伸出部204的至少一部分的厚度减小部210。面向表面伸出部204形成该封装200的顶表面212的一部分以促进散热。因为该引线框202由导电材料形成,暴露的面向表面伸出部204也可用于向和从一个或多个集成电路器件214传导电信号,该集成电路器件安装在绝缘衬底218的中心部分上。模制树脂216封装该一个或多个集成电路器件214且在厚度减小部210上延伸,以有效地将该引线框202锁定在适当位置。
对于引线框202的要求与这里上述的对散热器的要求相似。该引线框202由例如铜、铜合金、铝、铝合金或者有时用于引线框的铁/镍基合金(例如合金42(42%镍-平衡铁)或科瓦铁镍钴合金(铁-镍-钴合金))的导电金属形成。因为该面向表面伸出部204暴露于环境,该面向表面伸出部的至少暴露部分涂覆抗腐蚀材料。优选地,该引线框202由铜基合金形成,且该面向表面伸出部204的暴露部分以黑色氧化物涂覆。
引线框22的与这里上述的散热器相同的其他特征是为了阵列需要可以以网状形式提供该引线框。根据需要,该面向表面伸出部204可以是圆形或正方形或任何其他所需形状。特征可以蚀刻到该引线框和连接杆中以增强该连接杆的模制锁定和对准。优选地镦制该连接杆以使起该面向表面伸出部升高并避免接触引线接合封装的导线。该连接杆的部分可以细化以易于切割,且可以具有用于提供与引线接合的隔离间隙的凸出部。
该引线框可由铜合金、铝合金或其他具有高导热系数的金属形成。当由铝基合金形成时,它可以被黑阳极处理或具有另一种涂层,以改善标记对比。引线框可以以矩阵形式提供,或被切割来用于拾取和放置过程。模制可以作为单独封装或条的形式。
该封装200的衬底218由绝缘材料形成且可包括上述的向下伸出的散热块。多个导电过孔220贯穿该衬底的外周部,从而将导线或突出接合部220与焊球224相互连接。如所示的,该导电过孔中的一些提供用于与绕该IC器件214的外周226形成的输入/输出(I/O)垫进行电通讯的路径。其他的导电过孔220’形成焊球和连接杆208之间的电路径。面向芯片伸出部206可与该IC器件214的中心部分228电接触。这样,该引线框202提供用于导热的路径和用于导电的路径中的至少一个或者两个。导热脂或其他热/电增强材料可以设置在面向芯片伸出部206和中心部228之间。
虽然图12示出了引线接合的集成电路器件214,但该集成电路器件214的电气有源面可以面向下且通过倒装芯片焊接方式与该衬底218电连接。
图15a以剖视表示方式示出了结合引线框202和衬底218以有效地用于球栅阵列封装和平面栅格封装的可替换封装230。该引线框202贯穿在衬底上的居中设置的孔232。引线框202通过该引线框202和衬底218之间的传导或不传导粘合材料保持在适当位置。一个或多个集成电路器件214安装到该引线框202的向上伸出部235的表面234上。该集成电路器件214通过导线或突出接合部222与导电过孔220相互电连接。然后,该集成电路器件封装在模制树脂216中。
某些导电过孔220’将该集成电路器件214的电气有源面上的输入/输出垫和该引线框202的外部部分236或连接杆相互电连接。图15b示出了用于该封装的可替换实施例230’的改进的引线框202’。
图16以剖视表示示出了又一个可替换封装240。引线框202具有贯穿居中设置的孔232的向下伸出部241。可选择地与无源器件242结合的一个或多个集成电路器件214安装在该引线框202的居中设置部分244上以降低该封装240的整体高度。导线或突出接合部222将集成电路器件214或无源器件242上的I/O垫与例如印刷电路板上的外部电路相互电连接。所选择的导电过孔220”’将该引线框202的外部部分236与外部电路相互电连接。与前述实施例一样,集成电路器件214和可选的无源器件242然后用模制树脂216封装。
该引线框202的向下伸出部241的表面246提供用于散热的大表面积。虽然如以下示例所示,与传统的BGA和LGA封装相比这里公开的所有封装均具有改善的散热特性,但图16的封装240大幅度地提高了散热。为了更好的散热特性,该表面246可以与外部散热片或散热器热连接或暴露于冷却液。表面246也可起到止挡的功能,以在焊球熔化以连接到外部电路之后控制接合到导电过孔220”’的焊球的尺寸。
本发明的优点将从以下示例变得更加明显。
示例
示例1
图12的封装通过具有表1的尺寸和规格的169个球8×8BGA(FBGA)封装的计算机仿真而模拟热性能。ΘJA是从半导体器件的运行部分到围绕该设备的静止空气环境的热阻。如表2中所示,该仿真的ΘJA改善了大约2℃/W。这种改善意味着功率消耗的7.9%的改善。
表1
封装类型 : FBGA
封装尺寸 : 8×8×0.7mm
管芯尺寸 : 4.98×4.8×0.25mm
球形矩阵 : 13×13
球的数量 : 169个球
球间距 : 0.5mm
腔体方向 : 向上
衬底 : 2层(0.2mm厚)
PCB中热过孔数量 : 81
表2
静止空气 | 无引线框 | 有引线框 |
ΘJA(℃/W) | 27.04 | 25.05 |
ΘJA 善 | N.A. | 1.99 |
功率改善(W/W) | N.A. | 0.0794 |
示例2:
图15和16的封装通过具有表3的尺寸和规格的FBGA封装的计算机仿真而模拟热性能。这些仿真封装的计算热性能在表4中示出。
表3
封装类型 : FBGA
封装尺寸 : 8×8×0.7mm
管芯尺寸 : 4.98×4.8×0.25mm
球形矩阵 : 13×13
球的数量 : 169个球
球间距 : 0.5mm
腔体方向 : 向上
衬底 : 2层(0.2mm厚)
PCB中热过孔数量 : 81
表4
静止空气 | 无引线框 | 衬底上有引线框(图16) | 衬底下有引线框(图15) |
ΘJA(℃/W) | 27.04 | 24.05 | 24.69 |
ΘJA改善 | N.A. | 2.99 | 2.35 |
功率改善(W/W) | N.A. | 0.1243 | 0.0952 |
表4示出了图15的封装具有大约2.4℃/W的ΘJA改善而图16的封装具有几乎3℃/W的ΘJA改善。与图15的封装相比,由于更小的居中设置的孔,该封装能保持更多的信号I/O。再参考图2,该中间部分28可以被制造得更小且该居中设置的孔更小,使得该封装能在衬底12上保持更多的信号I/O。此外,该引线框能用作接地平面和热路径。
已经描述本发明的一个或多个实施例。然而,可以理解在不背离本发明的精神和范围的前提下可以作出各种修改。
Claims (34)
1.一种用于包装一个或多个半导体器件(30)的阵列型封装(10),其特征在于:
绝缘衬底(12),该绝缘衬底具有对置的第一侧面(14)和第二侧面(16),所述绝缘衬底(12)还具有多个导电过孔(18)和从所述第一侧面(14)延伸到所述第二侧面(16)的居中设置的孔(20);
散热块(22),该散热块具有贯穿所述孔(20)的中间部分(28)、与所述第一侧面(12)相邻的第一部分(24)、和与所述第二侧面(16)相邻的对置的第二部分(26),所述第一部分(24)具有比所述孔(20)的横截面面积更大的横截面面积;
一个或多个半导体器件(30),所述一个或多个半导体器件接合到所述散热块(22)的所述第一部分(24)且与所述绝缘衬底(12)的所述第一侧面(14)上的所述导电过孔(18)相互电连接(32);
散热器(34),该散热器具有第一侧面(36)和对置的第二侧面(38),且与所述一个或多个半导体器件(30)间隔开对引线接合中所使用的导线足够的隔离间隙并与所述散热块(22)大致平行,由此所述一个或多个半导体器件(30)设置在所述散热器(34)和所述散热块(22)之间;和
模制树脂(40),该模制树脂封装所述一个或多个半导体器件(30),并至少封装所述衬底(12)的所述第一侧面(14)、所述散热块(34)的所述第一部分(36)和所述散热器(34)的所述第一侧面(36)。
2.如权利要求1所述的阵列型封装(10),其特征在于焊球(42)接合在所述衬底(12)的所述第二侧面(16)上的所述导电过孔(18)上,与所述接合相对的所述焊球的点是大致共面的。
3.如权利要求2所述的阵列型封装(10),其特征在于所述散热块(22)的所述第二部分(26)与所述焊球(42)的所述点大致共面。
4.如权利要求2所述的阵列型封装(10),其特征在于所述散热块(22)由从铜、铝及其合金组成的组中选择的金属形成。
5.如权利要求4所述的阵列型封装(10),其特征在于所述散热块(22)涂覆有另一种材料,以增强标记能力。
6.如权利要求5所述的阵列型封装(10),其特征在于所述散热块(22)是涂覆有黑阳极处理层的铝合金。
7.一种散热块阵列(44,194),其特征在于:
绝缘衬底(12),该绝缘衬底具有对置的第一侧面(14)和第二侧面(16)以及设置成阵列的多个孔(20);
多个相互连接的散热块(22),每个所述散热块(22)具有由中间部分(28)分离的第一部分(24)和第二部分(26),其中所述中间部分(28)贯穿所述多个孔(20)中的一个孔,且所述第一部分(24)具有比所述多个孔(20)中的所述一个孔的周长更大的周长。
8.如权利要求7所述的散热块阵列(44,194),其特征在于多个连接杆(46)从每个散热块(22)的每个第一部分(24)的周边伸出,且从一个所述散热块(22)伸出的连接杆(46)与从相邻散热块(22)伸出的至少一个其他连接杆(46)在相互交叉点(48)处交叉。
9.如权利要求8所述的散热块阵列(44,194),其特征在于在所述相互交叉点(48)处减小所述多个连接杆(46)的厚度,以便于切割。
10.如权利要求8所述的散热块阵列(194),其特征在于所述连接杆(194)包括用于与散热器阵列(50)的连接杆(190)接合的特征(192,196)。
11.如权利要求10所述的散热块阵列(194),其特征在于所述特征(192,196)从由凸出部(192)、孔(196)及其组合组成的组中选择。
12.一种用于制造包装一个或多个半导体器件(30)的阵列型封装(10)的方法,其特征在于以下步骤:
a)提供包含具有多个孔(20)的绝缘衬底(12)和多个相互连接的散热块(22)的散热块阵列(44),所述散热块具有由贯穿所述多个孔(20)中的一个孔的中间部分(28)分开的对置的第一部分(24)和第二部分(26),其中所述第一部分(24)具有比所述多个孔(20)中的所述一个孔的周长更大的周长,多个连接杆(46)从所述周长伸出,其中从一个所述散热块(22)伸出的连接杆(46)与从相邻散热块(22)伸出的至少一个其他连接杆(46)在相互交叉点(48)处交叉;
b)将所述一个或多个半导体器件(30)接合到所述第一部分(24)上并将所述一个或多个半导体器件(30)与所述绝缘衬底(12)的第一侧面(14)上的导电过孔(18)相互电连接(32),所述导电过孔(18)通过所述绝缘衬底(12)延伸到该绝缘衬底的对置第二侧面(16);
c)提供散热器阵列(50),该散热器阵列具有多个从其周长延伸的连接杆(52),其中从一个所述散热器(34)延伸的连接杆(52)与从相邻散热器(34)延伸的至少一个其他连接杆(52)在相互交叉点(54)处交叉;
d)将所述散热块(22)的连接杆(46)接合(62)到所述散热器(34)的连接杆(52)上,使得所述一个或多个半导体器件(30)设置在所述散热块(22)中的一个和所述散热器(34)中的一个之间;和
e)将所述一个或多个半导体器件(30)以及所述散热器(34)和散热块(22)的至少一部分封装在模制树脂(40)中。
13.如权利要求12所述的方法,包括将所述阵列切割成单个构件(10)的步骤。
14.如权利要求13所述的方法,其特征在于所述切割步骤在(a)提供散热器阵列(44)的步骤和(b)接合所述一个或多个半导体器件(30)的步骤之间。
15.如权利要求13所述的方法,其特征在于所述切割步骤在(f)封装步骤之后。
16.如权利要求13所述的方法,其特征在于所述散热块(22)的所述连接杆(46,194)和所述散热器(34)的所述连接杆(52,190)具有便于对齐和接合的特征(192,196)。
17.如权利要求16所述的方法,其特征在于所述散热块(22)和所述散热器(34)中的一个设置有凸出部(192),所述散热块(22)和所述散热器(34)中的另一个设置有配合孔(196)。
18.如权利要求13所述的方法,包括将焊球(42)连接在所述第二侧面(16)上的所述导电过孔(18)上的步骤。
19.如权利要求18所述的方法,其特征在于选择所述焊球(42)的直径,以有效地使所述焊球(42)上与所述第二侧面(16)相对的点与所述散热块(22)的所述第二部分(26)共面。
20.如权利要求19所述的方法,包括将所述焊球(42)和所述第二部分(26)焊接到外部电路上的步骤。
21.一种用于包装一个或多个半导体器件(214)的阵列型封装(200),其特征在于:
绝缘衬底(218),该绝缘衬底具有对置的第一侧面和第二侧面、中央半导体器件安装部和外周部,多个导电过孔(220)贯穿该外周部;
所述一个或多个半导体器件(214)中的至少一个具有对置的第一和第二侧面,所述第一侧面固定到所述半导体安装部上,所述至少一个半导体器件(214)与相应的所述导电过孔(220)相互电连接(222);
引线框(202),所述引线框具有面向表面侧面(204)和对置的面向芯片侧面(206),该面向表面侧面具有凸出部,所述面向芯片侧面与所述半导体器件(214)的所述第二侧面相邻,所述引线框(202)还具有多个连接杆(208),所述多个连接杆从引线框边缘向外延伸且与其他所述电连接过孔(220’)相互电连接;和
模制树脂(216),该模制树脂封装所述衬底(218)的至少所述第一侧面、至少一个集成电路器件(214)和所述引线框(202)的至少一部分,其中所述引线框(202)的所述凸出部(204)形成所述阵列型封装(200)的暴露表面。
22.如权利要求21的阵列型封装(200),其特征在于所述引线框(202)的所述面向芯片侧面(206)与所述至少一个半导体器件(214)热连接。
23.如权利要求22的阵列型封装(200),其特征在于所述引线框(202)的所述面向芯片侧面(206)与所述至少一个半导体器件(214)电连接。
24.如权利要求21的阵列型封装(200),其特征在于所述引线框(202)由铜基合金形成且涂覆黑色氧化物。
25.如权利要求21的阵列型封装(200),其特征在于所述引线框(202)由铝基合金形成且用黑色阳极处理进行涂覆。
26.一种用于包装一个或多个半导体器件(214)的阵列型封装(230),其特征在于:
绝缘衬底(218),该绝缘衬底具有对置的第一侧面和第二侧面、居中设置的孔(232)和外周部,多个导电过孔(220)贯穿该外周部;
引线框(202),该引线框具有向上伸出部(235)和外周凸缘(236),所述向上伸出部(235)贯穿所述居中设置的孔(232),并且所述凸缘部(236)抵靠所述绝缘衬底(218)的所述第二侧面;
所述一个或多个半导体器件(214)中的至少一个具有对置的第一和第二侧面,所述第一侧面固定到所述向上伸出部(235)上,所述至少一个半导体器件(214)与相应的所述导电过孔(220)相互电连接(222);
模制树脂(216),该模制树脂至少封装所述衬底(218)的所述第一侧面、所述至少一个集成电路器件(214)和所述引线框(202)的所述向上伸出部(235)。
27.如权利要求26所述的阵列型封装(230),其特征在于所述外周凸缘(236)与所述导电过孔中所选的多个过孔(220”)相互电连接。
28.如权利要求27所述的阵列型封装(230),其特征在于所述至少一个半导体器件(214)上的I/O垫与所述外周凸缘(236)共同地和至少导电过孔(220”)相互电连接(222)。
29.一种用于包装一个或多个半导体器件(214)的阵列型封装(240),其特征在于:
绝缘衬底(218),该绝缘衬底具有对置的第一侧面和第二侧面、居中设置的孔(232)和外周部,多个导电过孔(220)贯穿该外周部;
引线框(202),该引线框具有向下伸出部(241)和外周凸缘(236),所述向下伸出部(241)贯穿所述居中设置的孔(232),并且所述凸缘部(236)抵靠所述绝缘衬底(218)的所述第一侧面;
所述一个或多个半导体器件(214)中的至少一个具有对置的第一和第二侧面,所述第一侧面固定到所述向下伸出部(241),所述至少一个半导体器件(214)与相应的所述导电过孔(220)相互电连接;
模制树脂(216),该模制树脂至少封装所述衬底(218)的所述第一侧面、所述至少一个集成电路器件(214)和所述引线框(202)的所述外周凸缘(236)。
30.如权利要求29所述的阵列型封装(240),其特征在于所述外周凸缘(236)与所述导电过孔(220”’)中所选的多个过孔电连接。
31.如权利要求30所述的阵列型封装(240),其特征在于所述至少一个半导体器件(214)的至少一个I/O垫与所述外周凸缘(220”’)电连接(222)。
32.如权利要求29所述的阵列型封装(240),其特征在于所述向下伸出部(241)与外部结构热连接。
33.如权利要求29所述的阵列型封装(240),其特征在于焊球固定到所述衬底(218)的所述第二侧面上的所述导电过孔(220,220”’)。
34.如权利要求33所述的阵列型封装(240),其特征在于所述向下伸出部(241)在连接到外部电路之后有效地控制所述焊球的尺寸。
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US11/807,650 US7741158B2 (en) | 2006-06-08 | 2007-05-30 | Method of making thermally enhanced substrate-base package |
US11/807,650 | 2007-05-30 | ||
PCT/US2007/013206 WO2007145925A2 (en) | 2006-06-08 | 2007-06-05 | Method of making thermally enhanced substrate-based array package |
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Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9018667B2 (en) * | 2008-03-25 | 2015-04-28 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and dual adhesives |
US8329510B2 (en) * | 2008-03-25 | 2012-12-11 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a post/base heat spreader with an ESD protection layer |
US8148747B2 (en) * | 2008-03-25 | 2012-04-03 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base/cap heat spreader |
US8232576B1 (en) | 2008-03-25 | 2012-07-31 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and ceramic block in post |
US20100072511A1 (en) * | 2008-03-25 | 2010-03-25 | Lin Charles W C | Semiconductor chip assembly with copper/aluminum post/base heat spreader |
US20110163348A1 (en) * | 2008-03-25 | 2011-07-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump |
US8324723B2 (en) * | 2008-03-25 | 2012-12-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bump/base heat spreader and dual-angle cavity in bump |
US8269336B2 (en) * | 2008-03-25 | 2012-09-18 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and signal post |
US8203167B2 (en) * | 2008-03-25 | 2012-06-19 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and adhesive between base and terminal |
US8531024B2 (en) * | 2008-03-25 | 2013-09-10 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and multilevel conductive trace |
US20100181594A1 (en) * | 2008-03-25 | 2010-07-22 | Lin Charles W C | Semiconductor chip assembly with post/base heat spreader and cavity over post |
US8314438B2 (en) * | 2008-03-25 | 2012-11-20 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bump/base heat spreader and cavity in bump |
US8354688B2 (en) | 2008-03-25 | 2013-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump |
US8207553B2 (en) * | 2008-03-25 | 2012-06-26 | Bridge Semiconductor Corporation | Semiconductor chip assembly with base heat spreader and cavity in base |
US8310043B2 (en) * | 2008-03-25 | 2012-11-13 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader with ESD protection layer |
US7948076B2 (en) * | 2008-03-25 | 2011-05-24 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and vertical signal routing |
US8525214B2 (en) | 2008-03-25 | 2013-09-03 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader with thermal via |
US8067784B2 (en) * | 2008-03-25 | 2011-11-29 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and substrate |
US20110156090A1 (en) * | 2008-03-25 | 2011-06-30 | Lin Charles W C | Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts |
US20110278638A1 (en) | 2008-03-25 | 2011-11-17 | Lin Charles W C | Semiconductor chip assembly with post/dielectric/post heat spreader |
US8193556B2 (en) * | 2008-03-25 | 2012-06-05 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and cavity in post |
US8378372B2 (en) * | 2008-03-25 | 2013-02-19 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and horizontal signal routing |
US8415703B2 (en) * | 2008-03-25 | 2013-04-09 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base/flange heat spreader and cavity in flange |
US20100052005A1 (en) * | 2008-03-25 | 2010-03-04 | Lin Charles W C | Semiconductor chip assembly with post/base heat spreader and conductive trace |
US8288792B2 (en) * | 2008-03-25 | 2012-10-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base/post heat spreader |
US8129742B2 (en) | 2008-03-25 | 2012-03-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and plated through-hole |
US8212279B2 (en) * | 2008-03-25 | 2012-07-03 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader, signal post and cavity |
US20090284932A1 (en) * | 2008-03-25 | 2009-11-19 | Bridge Semiconductor Corporation | Thermally Enhanced Package with Embedded Metal Slug and Patterned Circuitry |
JP5155890B2 (ja) * | 2008-06-12 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8022516B2 (en) * | 2008-08-13 | 2011-09-20 | Atmel Corporation | Metal leadframe package with secure feature |
US8810015B2 (en) * | 2009-06-14 | 2014-08-19 | STAT ChipPAC Ltd. | Integrated circuit packaging system with high lead count and method of manufacture thereof |
US20100327421A1 (en) * | 2009-06-30 | 2010-12-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Ic package design with stress relief feature |
US8324653B1 (en) | 2009-08-06 | 2012-12-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with ceramic/metal substrate |
US8362598B2 (en) * | 2009-08-26 | 2013-01-29 | Amkor Technology Inc | Semiconductor device with electromagnetic interference shielding |
US8547709B2 (en) * | 2010-02-12 | 2013-10-01 | Cyntec Co. Ltd. | Electronic system with a composite substrate |
TWI544592B (zh) * | 2010-05-27 | 2016-08-01 | 精材科技股份有限公司 | 封裝結構及其製法 |
TWI485823B (zh) * | 2010-07-08 | 2015-05-21 | Subtron Technology Co Ltd | 半導體封裝結構及半導體封裝結構的製作方法 |
CN102376677B (zh) * | 2010-08-20 | 2013-07-10 | 旭德科技股份有限公司 | 半导体封装结构及半导体封装结构的制作方法 |
JP2012142371A (ja) * | 2010-12-28 | 2012-07-26 | Mitsubishi Electric Corp | 半導体パッケージ |
TWI421995B (zh) * | 2011-04-27 | 2014-01-01 | Unimicron Technology Corp | 半導體封裝結構及其製法 |
TWI453872B (zh) * | 2011-06-23 | 2014-09-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US20130082407A1 (en) * | 2011-10-04 | 2013-04-04 | Texas Instruments Incorporated | Integrated Circuit Package And Method |
US8556159B2 (en) | 2012-02-24 | 2013-10-15 | Freescale Semiconductor, Inc. | Embedded electronic component |
US8921994B2 (en) | 2012-09-14 | 2014-12-30 | Freescale Semiconductor, Inc. | Thermally enhanced package with lid heat spreader |
US9159643B2 (en) | 2012-09-14 | 2015-10-13 | Freescale Semiconductor, Inc. | Matrix lid heatspreader for flip chip package |
DE102013211613B4 (de) * | 2013-06-20 | 2023-01-12 | Robert Bosch Gmbh | Bauteil in Form eines Waferlevel-Packages und Verfahren zu dessen Herstellung |
CN104576565A (zh) * | 2013-10-18 | 2015-04-29 | 飞思卡尔半导体公司 | 具有散热体的半导体器件及其组装方法 |
US20150136357A1 (en) * | 2013-11-21 | 2015-05-21 | Honeywell Federal Manufacturing & Technologies, Llc | Heat dissipation assembly |
US9693445B2 (en) * | 2015-01-30 | 2017-06-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Printed circuit board with thermal via |
US9860987B2 (en) * | 2015-02-13 | 2018-01-02 | Deere & Company | Electronic assembly with one or more heat sinks |
US9947612B2 (en) | 2015-12-03 | 2018-04-17 | Stmicroelectronics, Inc. | Semiconductor device with frame having arms and related methods |
JP6283379B2 (ja) * | 2016-01-29 | 2018-02-21 | 本田技研工業株式会社 | コンデンサの配置構造 |
WO2017145331A1 (ja) * | 2016-02-25 | 2017-08-31 | 三菱電機株式会社 | 半導体パッケージ、及びモジュール |
US10269678B1 (en) * | 2017-12-05 | 2019-04-23 | Nxp Usa, Inc. | Microelectronic components having integrated heat dissipation posts, systems including the same, and methods for the fabrication thereof |
US11183487B2 (en) * | 2018-12-26 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
TWI692846B (zh) * | 2019-03-21 | 2020-05-01 | 旭德科技股份有限公司 | 散熱基板及其製作方法 |
CN113923848B (zh) * | 2020-07-10 | 2023-07-21 | 庆鼎精密电子(淮安)有限公司 | 电路板及其制造方法 |
JP7506564B2 (ja) * | 2020-09-10 | 2024-06-26 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5111277A (en) | 1991-03-29 | 1992-05-05 | Aegis, Inc. | Surface mount device with high thermal conductivity |
US6262477B1 (en) | 1993-03-19 | 2001-07-17 | Advanced Interconnect Technologies | Ball grid array electronic package |
AU2371795A (en) | 1994-05-17 | 1995-12-05 | Olin Corporation | Electronic packages with improved electrical performance |
US5969414A (en) | 1994-05-25 | 1999-10-19 | Advanced Technology Interconnect Incorporated | Semiconductor package with molded plastic body |
US5629835A (en) | 1994-07-19 | 1997-05-13 | Olin Corporation | Metal ball grid array package with improved thermal conductivity |
US5442230A (en) | 1994-09-16 | 1995-08-15 | National Semiconductor Corporation | High density integrated circuit assembly combining leadframe leads with conductive traces |
US5569955A (en) | 1994-09-16 | 1996-10-29 | National Semiconductor Corporation | High density integrated circuit assembly combining leadframe leads with conductive traces |
US5977626A (en) * | 1998-08-12 | 1999-11-02 | Industrial Technology Research Institute | Thermally and electrically enhanced PBGA package |
US7161239B2 (en) | 2000-12-22 | 2007-01-09 | Broadcom Corporation | Ball grid array package enhanced with a thermal and electrical connector |
US6963142B2 (en) | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
US6700206B2 (en) | 2002-08-02 | 2004-03-02 | Micron Technology, Inc. | Stacked semiconductor package and method producing same |
JP2006501677A (ja) * | 2002-09-30 | 2006-01-12 | アドバンスド インターコネクト テクノロジーズ リミテッド | ブロック成形集成体用の耐熱強化パッケージ |
US7432586B2 (en) * | 2004-06-21 | 2008-10-07 | Broadcom Corporation | Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages |
TWI235465B (en) | 2004-10-28 | 2005-07-01 | Advanced Semiconductor Eng | Multi-row substrate strip and method for manufacturing the same |
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- 2007-06-05 WO PCT/US2007/013206 patent/WO2007145925A2/en active Search and Examination
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CN101467249A (zh) | 2009-06-24 |
KR20090036085A (ko) | 2009-04-13 |
WO2007145925A3 (en) | 2008-04-10 |
WO2007145925B1 (en) | 2008-06-12 |
JP2009540572A (ja) | 2009-11-19 |
WO2007145925A2 (en) | 2007-12-21 |
TWI351744B (en) | 2011-11-01 |
US20070284733A1 (en) | 2007-12-13 |
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