JP6661565B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 120
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000011347 resin Substances 0.000 claims description 58
- 229920005989 resin Polymers 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 16
- 238000004891 communication Methods 0.000 description 12
- 238000000465 moulding Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000008054 signal transmission Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
図1は、アウターリード2−1−1、2−2−1を有するリード2−1、2−2と、アウターリードを有さないインナーリード3−1−2、3−2−2との関係を示す半導体装置Dの部分断面図である。図2は、チップ間通信のためのインナーリード12−1−2、12−2−2とインナーリード13−1−2、13−2−2との関係を示す半導体装置Dの部分断面図である。
以下、実施形態に係る半導体装置の半導体製造装置による半導体製造方法について説明する。
この際、リード12−1、12−2、13−1、13−2のタイバー12−1−1、12−2−1、13−1−1、13−2−1の切断は、リード3−1、3−2のタイバー3−1−1、3−2−1の切断とともに行なわれる。
3 効果
実施形態によれば、チップ間通信に使用されるリードについては、不要なアウターリードを削減した分だけパッケージのサイズを小さくすることができる。
Claims (8)
- 第1ダイパッドと、
モールド成形された樹脂の内部に配置された第1インナーリードと、
第2ダイパッドと、
前記樹脂の内部に配置された第2インナーリードと、
前記樹脂の外部に配置されたアウターリードと、前記樹脂の内部に配置されるインナーリードとを有する複数のリードと、
前記樹脂の内部に配置される第3インナーリードとを具備し、
前記第1インナーリードの一部及び前記第2インナーリードの一部は、互いに貼り合わされて電気的に接続され、
前記第1ダイパッドに搭載された第1半導体チップは、前記第1インナーリード及び前記第2インナーリードを介して、前記第2ダイパッドに搭載された第2半導体チップに電気的に接続され、
前記貼り合わされた前記第1インナーリード及び前記第2インナーリードの一端の端面は、前記樹脂の側面に露出しており、
前記リードの前記インナーリードの一部及び前記第3インナーリードの一部は、互いに貼り合わされて電気的に接続され、
前記第1半導体チップは、前記リード及び前記第3インナーリードを介して、前記第2半導体チップに電気的に接続され、
前記第3インナーリードの一端の端面は、前記モールド成形された樹脂の側面に露出している、
半導体装置。 - 前記第1インナーリード及び前記第2インナーリードは、前記複数のリードの前記インナーリードの間に配置される、請求項1記載の半導体装置。
- 前記第2ダイパッドの前記第2半導体チップが搭載された面とは異なる面は、前記樹脂の表面に露出している、請求項1記載の半導体装置。
- 前記第2ダイパッドの前記第2半導体チップが搭載された面とは異なる面は、前記第2半導体チップで発生した熱を放熱するための部材に接触している、請求項3記載の半導体装置。
- 第1ダイパッドと、第1インナーリードと、前記第1インナーリードから伸びる第1タイバーとを有する第1リードの前記第1ダイパッドに第1半導体チップを搭載し、
第2ダイパッドと、第2インナーリードと、前記第2インナーリードから伸びる第2タイバーとを有する第2リードの前記第2ダイパッドに第2半導体チップを搭載し、
前記第1インナーリードと、前記第2インナーリードとを、前記第1半導体チップと前記第2半導体チップとが所定間隔で互いに対向するように貼り合わせ、
前記第1ダイパッド、前記第2ダイパッド、前記第1インナーリード、前記第2インナーリード、前記第1半導体チップ、及び前記第2半導体チップを樹脂で覆い、
前記樹脂で覆われた前記第1インナーリードから前記第1タイバーを切断し、前記樹脂で覆われた前記第2インナーリードから前記第2タイバーを切断する、
半導体装置の製造方法。 - 前記第1リードを有する第1フレームはさらに、前記第1半導体チップに電気的に接続された第3インナーリードと前記第3インナーリードから伸びるアウターリードとを有し、
前記第2リードを有する第2フレームはさらに、前記第2半導体チップに電気的に接続された第4インナーリードと前記第4インナーリードから伸びる第3タイバーとを有し、
前記第1タイバー及び前記第2タイバーを切断することは、前記第3タイバーを切断することとともに行なわれる、請求項5記載の半導体装置の製造方法。 - 前記第1インナーリードと前記第2インナーリードとを貼り合わせることは、前記第1インナーリード及び前記第2インナーリードに形成された位置合わせ用の凹部又は凸部を使用して行なわれる、請求項5記載の半導体装置の製造方法。
- 前記第1インナーリードと前記第2インナーリードとを貼り合わせることは、前記第3インナーリード及び前記第4インナーリードに形成された位置合わせ用の凹部又は凸部を使用して行なわれる、請求項6記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017054915A JP6661565B2 (ja) | 2017-03-21 | 2017-03-21 | 半導体装置及びその製造方法 |
TW106126539A TWI682507B (zh) | 2017-03-21 | 2017-08-07 | 半導體裝置及其製造方法 |
US15/698,926 US10796982B2 (en) | 2017-03-21 | 2017-09-08 | Semiconductor device and method of manufacturing the same |
US16/567,287 US10720381B2 (en) | 2017-03-21 | 2019-09-11 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2017054915A JP6661565B2 (ja) | 2017-03-21 | 2017-03-21 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2018157162A JP2018157162A (ja) | 2018-10-04 |
JP6661565B2 true JP6661565B2 (ja) | 2020-03-11 |
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JP2017054915A Expired - Fee Related JP6661565B2 (ja) | 2017-03-21 | 2017-03-21 | 半導体装置及びその製造方法 |
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US (2) | US10796982B2 (ja) |
JP (1) | JP6661565B2 (ja) |
TW (1) | TWI682507B (ja) |
Family Cites Families (19)
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JPS6137540A (ja) | 1984-07-30 | 1986-02-22 | Kubota Ltd | 走行用伝動装置 |
JPH0778596B2 (ja) | 1988-08-19 | 1995-08-23 | 富士写真フイルム株式会社 | ハロゲン化銀写真乳剤の製造方法 |
JPH0312954A (ja) | 1989-06-12 | 1991-01-21 | Nec Corp | 樹脂封止型半導体装置 |
JPH0329354A (ja) | 1989-06-26 | 1991-02-07 | Mitsubishi Electric Corp | 半導体装置 |
JP2960283B2 (ja) | 1993-06-14 | 1999-10-06 | 株式会社東芝 | 樹脂封止型半導体装置の製造方法と、この製造方法に用いられる複数の半導体素子を載置するためのリードフレームと、この製造方法によって製造される樹脂封止型半導体装置 |
JPH088389A (ja) | 1994-04-20 | 1996-01-12 | Fujitsu Ltd | 半導体装置及び半導体装置ユニット |
JPH09129819A (ja) | 1995-11-01 | 1997-05-16 | Hitachi Ltd | 半導体装置およびその製造方法 |
KR100285664B1 (ko) * | 1998-05-15 | 2001-06-01 | 박종섭 | 스택패키지및그제조방법 |
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TW558810B (en) * | 2002-07-05 | 2003-10-21 | Siliconware Precision Industries Co Ltd | Semiconductor package with lead frame as chip carrier and fabrication method thereof |
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KR101146973B1 (ko) * | 2005-06-27 | 2012-05-22 | 페어차일드코리아반도체 주식회사 | 패키지 프레임 및 그를 이용한 반도체 패키지 |
TWI287876B (en) * | 2005-10-21 | 2007-10-01 | Siliconware Precision Industries Co Ltd | Semiconductor package |
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US7564123B1 (en) * | 2008-05-19 | 2009-07-21 | Powertech Technology Inc. | Semiconductor package with fastened leads |
TWI490960B (zh) * | 2012-01-17 | 2015-07-01 | Chipmos Technologies Inc | 半導體封裝結構及其製作方法 |
JP5512784B2 (ja) * | 2012-11-26 | 2014-06-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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-
2017
- 2017-03-21 JP JP2017054915A patent/JP6661565B2/ja not_active Expired - Fee Related
- 2017-08-07 TW TW106126539A patent/TWI682507B/zh not_active IP Right Cessation
- 2017-09-08 US US15/698,926 patent/US10796982B2/en active Active
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2019
- 2019-09-11 US US16/567,287 patent/US10720381B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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TW201843779A (zh) | 2018-12-16 |
TWI682507B (zh) | 2020-01-11 |
US20180277466A1 (en) | 2018-09-27 |
US10720381B2 (en) | 2020-07-21 |
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