CN101443979B - 用于电池功率控制的多芯片模块及其制造方法 - Google Patents
用于电池功率控制的多芯片模块及其制造方法 Download PDFInfo
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- CN101443979B CN101443979B CN2007800051730A CN200780005173A CN101443979B CN 101443979 B CN101443979 B CN 101443979B CN 2007800051730 A CN2007800051730 A CN 2007800051730A CN 200780005173 A CN200780005173 A CN 200780005173A CN 101443979 B CN101443979 B CN 101443979B
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Abstract
一种适用于电池保护电路的多芯片模块。该多芯片模块包括:集成单路芯片;第一功率晶体管;第二功率晶体管;第一连接结构,它将集成电路芯片电耦合到第一功率晶体管;第二连接结构,它将集成电路芯片电耦合到第二功率晶体管;以及引线框结构,它包括第一引线、第二引线、第三引线和第四引线,其中集成电路芯片、第一功率晶体管和第二功率晶体管被安装到引线框结构上。模塑材料覆盖集成电路芯片、第一功率晶体管、第二功率晶体管、第一连接结构和第二连接结构的至少一部分。
Description
相关申请的交叉引用
本专利申请是2006年2月13日提交的美国临时专利申请No.60/773,034的非临时申请并要求其优先权,该申请出于所有目的通过引用整体结合于此。
背景
存在用于锂离子电池的各种保护机制。如果锂离子电池过度充电,则较强的放热反应是可能的,并且导致火灾的可能性增大。
为了防止锂离子电池过度充电,使用电池保护电路。电池保护电路——图1中所示的示例——常常连同其它组件一起包含两个FET(场效应晶体管)开关122、124和控制IC(集成电路)120。一个FET防止电流流入电池,而另一个防止电流从电池流出,除非控制IC允许它流出。
存在包含控制IC和MOSFET的多芯片模块。然而,可作出许多改进。例如,某些常规多芯片模块在封装的所有四侧都包含引线。这导致模块较大,这不是期望的,因为此类模块被用在诸如蜂窝电话的小型电子设备中。多芯片模块的大小可被减小,但是这减小了可用在此类封装中的芯片的载流能力。
因此,需要改进的多芯片模块。
本发明的实施例单独或共同地解决上述问题和其它问题。
简要概述
本发明的实施例涉及多芯片模块,用于制作多芯片模块的方法,以及结合该多芯片模块的系统和组装件。
本发明的一个实施例涉及多芯片模块,它包括至少一个集成电路(IC)芯片、至少一个功率器件芯片以及包括引线的金属引线框结构。金属引线 框结构包括彼此电隔离的至少两个独立管芯安装焊盘。该至少两个独立管芯安装焊盘包括用于安装至少一个IC芯片的第一焊盘和用于安装至少一个功率器件芯片的第二焊盘。多芯片模块还可包括将至少一个IC芯片和至少一个功率器件芯片连接到引线的具有一个以上的直径的接合导线。
本发明的另一实施例涉及电池保护模块,该模块包括集成单路芯片以及容纳在单个外壳中用于调节电池的充电和放电的至少一个功率器件芯片。外壳可由模塑材料形成。集成电路芯片和至少一个功率器件芯片形成电路的至少一部分。到电路的必要外部连接被限于四个引线。
本发明的另一实施例涉及多芯片模块,该模块包括:集成单路芯片;第一功率晶体管;第二功率晶体管;第一连接结构,它将集成电路芯片电耦合到第一功率晶体管;第二连接结构,它将集成电路芯片电耦合到第二功率晶体管;以及引线框结构。该引线框结构包括第一引线、第二引线、第三引线和第四引线,其中集成电路芯片、第一功率晶体管和第二功率晶体管被安装到引线框结构上。模塑材料覆盖集成电路芯片、第一功率晶体管、第二功率晶体管、第一连接结构和第二连接结构的至少一部分。第一引线提供到第一功率晶体管的电连接,而第二引线提供到第二功率晶体管的电连接。第一和第二引线在多芯片模块的第一端处,而第三和第四引线在多芯片模块的第二端处。管芯安装焊盘的至少一个沿着焊盘的两个相对侧皆没有外部引线、安装焊盘或其它管芯安装焊盘。
本发明的其它实施例涉及用于形成上述多芯片模块的方法以及使用此类模块的组装件和系统。
本发明的其它实施例的可参照附图和以下详细描述来描述。
附图简述
图1示出常规电池保护电路图。
图2示出根据本发明的实施例的多芯片模块的立体图。也示出该多芯片模块中的内部组件。
图3示出图2中所示模块的侧视图。
图4(a)-4(e)示出多芯片模块中的组件的立体图。图4(a)-4(e)例示用于制 作图2中所示的多芯片模块的工艺流程。
图5示出结合图2中所示的多芯片模块的电池保护电路图。
图6示出图2中所示的多芯片模块的电路图。
图7示出多芯片模块的仰视图。
图8示出包括电路衬底和安装在该电路衬底上的图2中所示的多芯片模块的电组装件。
图9示出包括耦合到图8中所示的电组装件的锂离子电池的系统。
图10(a)示出了另一模块实施例的底部平面图。
图10(b)示出用在图10(a)的模块中的引线框结构和管芯的顶部立体图。
图10(c)示出图10(b)中所示引线框结构的顶部立体图。
详细描述
公开了用于调节诸如蜂窝电话电池之类的电池的充电的功率半导体开关和控制IC的集成。在本发明的实施例中,公开了较小形状因数的多芯片模块,并且它可被安装到微型电路板上。微型电路板可被连接到电池组的端子末端。多芯片模块可形成部分电池保护电路。
如以上所述,图1示出常规电池保护电路图。某些人已用分立组件来创建图1中所示的电路。当许多分立组件被用于形成图1中所示的电路时,所形成的保护电路可导致占用相对较大的空间量。例如,仅对于分立IC和功率MOSFET,在电路板上就可能需要最少八个焊接焊盘。
本发明的实施例集中在使包封在多芯片模块的紧致(例如,2毫米×5毫米)外壳的内部中的芯片面积最大化。在外壳的内部,多芯片模块中的外部引脚的数目和内部信号路由特征被最小化。
许多不同特征可引向这种类型的紧致、多芯片模块。首先,功率MOSFET的引线框结构的管芯安装焊盘可从多芯片模块的一个边缘完全延伸到另一个边缘。这允许管芯安装焊盘上的功率芯片的大小被最大化,由此使功率MOSFET的额定电流最大。第二,不存在从或者功率芯片或者IC芯片到引线框结构的“向下接合(down bond)”。第三,IC与功率MOSFET之间的连接通过芯片到芯片的互连(例如,导线互连)来实现。第四,与 MOSFET管芯安装焊盘毗邻的外部引线和信号路由元件的数目被最小化。通过使外部引线最小化并消去“向下接合”,封装内部的面积被最大化,从而允许较大的功率MOSFET。功率MOSFET增加的大小减小了导通电阻,这使得功率损失最小化并降低发热。这最终增大了电池的有效能量。
根据本发明的实施例的多芯片模块也可具有专用诊断测试模式。为了防止电流过冲(overshoot),MOSFET开关时间通过驱动IC来减小。在本发明的实施例中,正常工作模式验证测试将需要1200毫秒的测试时间。多芯片模块未用于正常操作的一条引线连接到IC上的焊盘,这使得IC能够使开关时间缩短至原来的十分之一,由此允许验证测试时间被减至120毫秒。经缩减的测试时间增大了验证测试操作的吞吐量,并降低产品的制造成本。在本发明的实施例中,多芯片模块中IC安装焊盘旁边的任选的第五引线可独占地用于将IC设置到专用诊断测试模式。
图2示出根据本发明的实施例的多芯片模块200。如图2中所示,多芯片模块200包括细长形状并包括第一纵向端200(a)和第二相对纵向端200(b)。在本发明的实施例中,多芯片模块200可具有大于1的纵横比。如以下进一步详细说明的,当此特定形状因数被用在与可充电电池一起使用的电组装件中时,该形状因数使得空间最小化。
多芯片模块200包括引线框结构210。在此示例中,引线框结构210包括彼此由间隙214隔开的第一安装焊盘210(a)-1和第二安装焊盘210(a)-2。间隙214使第一和第二安装焊盘210(a)-1、210(a)-2电隔离,因此在这些焊盘上的任何芯片并非通过引线框结构210直接电连接到一起。
在其它实施例中,间隙214无需存在。例如,具有单个安装焊盘是可能的,并且随后在安装于该单个安装焊盘上的任何芯片中的一个或两个之下具有介电层。介电层随后将使芯片的底面彼此电隔离。
引线框结构210还包括系杆224。(附图标记224指向系杆的示例;在此特定示例中,在封装的一侧有6个系杆,并且在封装中总共有12个系杆。)系杆224远离第一和第二管芯安装焊盘210(a)-1、210(a)-2在横向上延伸。这些系杆224在加工期间可用于将引线框结构的阵列中的多个引线框结构连接在一起。
如图2中所示,引线框结构210还包括在引线框结构210的一个纵向端处以及在模块200的一个纵向端处的两个引线210(b)-1、210(b)-2(例如,第一和第二引线)。引线框210还包括在引线框结构210和模块200的另一纵向端处的两个引线210(b)-3、210(b)-4(例如,第三和第四引线)。任选测试引线210(c)相对于第二安装焊盘210(a)-2横向地设置。如图2中所示,在模块200中仅有四个必需的引线210(b)-1、210(b)-2、210(b)-3、210(b)-4。
在此示例中,引线210(b)-1、210(b)-2、210(b)-3、210(b)-4与第一和第二管芯安装焊盘210(a)-1、210(a)-2分开,但是如果模块200被用在不同类型的电路中,则它们可连接到这些焊盘(例如,与焊盘集成)。
引线框结构210可包括任何合适的材料,包括铜及其合金。在某些实施例中,引线框结构210可用NiPdAu预先电镀或用可焊接材料(例如,Sn)电镀。
半导体芯片204包括功率晶体管并被安装在第一安装焊盘210(a)-1上。控制IC芯片215被安装在第二管芯安装焊盘210(a)-2上。
在此实施例中,包括功率晶体管的半导体芯片204包括第一MOSFET204(m)-1,该第一MOSFET 204(m)-1包括在芯片204的第一表面上的第一源极区204(s)-1和第一栅极区204(g)-1以及在芯片204的第二表面上的漏极区204(d)。在此示例中,第一MOSFET可以是垂直MOSFET,因为源极区204(s)-1和漏极区204(d)在芯片204的相对的侧。在此示例中,芯片204的第一表面将在引线框结构210的远端,而芯片204的第二表面将在引线框结构210的近端。
虽然详细描述了功率MOSFET,但是任何适当的垂直功率晶体管可用在本发明的实施例中。垂直功率晶体管包括VDMOS晶体管和垂直双极晶体管。VDMOS晶体管是具有两个或更多个通过扩散形成的半导体区的MOSFET。它具有源极区、漏极区和栅极。设备是垂直的,因为源极区和漏极区在半导体管芯的相对的表面上。栅极可以是沟槽栅极结构或平面栅极结构,并且在与源极区相同的表面处形成。沟槽栅极结构是较佳的,因为沟槽栅极结构较窄且占用比平面栅极结构少的空间。在操作期间,VDMOS器件中从源极区流入漏极区的电流基本上与管芯表面垂直。
半导体芯片204也包括第二MOSFET 204(m)-2,该第二MOSFET204(m)-2包括在芯片204的第一表面上的第二源极区204(s)-2和第二栅极区204(g)-2。第二MOSFET 204(m)-2也包括在芯片204的第二表面上的漏极区204(d)。在此示例中,第一和第二MOSFET 204(m)-1、204(m)-2共享作为公共漏极的公共衬底。(在图2中,在芯片204中限定诸如源极区之类区域的扩散区未被示出。)第一和第二MOSFET 204(m)-1、204(m)-2的漏极区204(d)可电耦合到安装焊盘210(a)-1。
在图2中所示的特定示例中,在单个芯片中存在两个MOSFET。然而,在其它实施例中,在该芯片204中仅有一个MOSFET,或者两个单独的芯片可被安装到第一管芯安装焊盘210(a)上。另外,尽管示出两个MOSFET,但是如果最终应用与图1中所示的电池保护电路不同,则在其它实施例中仅使用一个MOSFET是可能的。
多个连接结构可用于将芯片电耦合在一起,和/或将芯片电耦合到引线。连接结构的示例包括导线或导电夹。此类连接结构可包括任何合适的材料,包括诸如金的贵金属,或者诸如铜或其合金的金属。在图2中所示的多芯片模块200中,连接结构是导线形式的。
参看图2,第一直径的多条导线206(a)-1、206(a)-2将MOSFET的源极区204(s)-1、204(s)-2电耦合到引线210(b)-1、210(b)-2。第二直径的导线220、222可将IC芯片215电耦合到引线210(b)-3、210(b)-4。连接到源极区204(s)-1、204(s)-2的导线206(a)-1、206(a)-2具有比连接到IC芯片215的导线220、222大的直径,因为前者比后者承载更多电流。
多芯片模块200中存在的其它导线包括将IC芯片215连接到栅极区204(g)-1、204(g)-2的导线218(g)-1、218(g)-2。另一导线208(s)-1将IC芯片215电耦合到芯片204中的MOSFET之一的源极区204(s)-1。又一导线212将测试引线210(c)电耦合到IC芯片215。
模塑材料202覆盖引线框结构210、功率晶体管芯片204和IC芯片215的至少一部分。模塑材料202可包括环氧材料或任何其它合适的材料。如图2中所示,引线210(b)-1、210(b)-2、210(b)-3、210(b)-4的端子末端不延伸超过模塑材料202的侧面。图2中所示的多芯片模块200可被表征为MLP (微引线封装)类型封装。
在图2中的多芯片模块中,不存在“向下接合”或者导线向下接合到安装焊盘210(a)-1。例如,导线208(s)-1用于将IC芯片215经由芯片204、215的顶面连接到芯片204中第一MOSFET 204(m)-1的源极区204(s)-1。由于在多芯片模块200中不存在“向下接合”,因此否则将用于向下接合的空间可被芯片204占用,由此使得芯片204的大小在多芯片模块200的边界内最大化。
多芯片模块200也可包括任选的专用测试引线210(c)。封装可用测试引线210(c)更快速地测试。使用测试引线210(c),IC芯片215可被重新编程以使得测试可更快速地执行。如以上所说明的,使用此特征,测试可以比不用专用测试引线210(c)时快达10倍地进行。
图3示出图2中所示模块的侧视图。参照图2描述图3中的组件,并且类似附图标记指示类似元件。图3另外示出引线框结构210的部分蚀刻区210(d)(例如,半蚀刻区)。模塑材料202填充由半蚀刻区210(d)形成的空间,并且模塑材料202可固定引线框结构210。湿法蚀刻工艺可用于形成部分蚀刻区210(a),如本领域中常见的那样。
图3还示出,引线框结构210的底表面、外表面可基本上与模塑材料202的外表面共面。多芯片模块200可直接安装到电路板等,并且引线框结构210的曝露面可用于将热量自功率芯片204转移到电路板上的底层焊盘(未示出)。
可参照图4(a)-4(e)描述用于形成模块200的方法。
图4(a)示出包括第一管芯安装焊盘210(a)-1和第二管芯安装焊盘210(a)-2的引线框结构210。此引线框结构210可以包括蚀刻、冲压等任何合适的方式来获得。
如图4(b)中所示,诸如含银环氧树脂(silver loaded epoxy)或焊接材料(铅焊料或无铅焊料)的导电材料230(a)-1、230(a)-2随后被分别涂到第一和第二管芯安装焊盘210(a)-1、210(a)-2。导电粘合剂230(a)-1、230(a)-2可通过涂覆工艺或分散工艺来涂到第一和第二管芯安装焊盘210(a)-1、210(a)-2。在其它实施例中,粘合剂还可以是不导电的。
如图4(c)中所示,芯片204、215随后被附连到第一和第二管芯安装焊盘210(a)-1、210(a)-2。包括拾取和放置工艺在内的任何合适的工艺可用于将芯片204、215安装到安装焊盘210(a)-1、210(a)-2上。
如图4(d)中所示,前述导线(例如,包括导线206(a)-1、206(a)-2)被接合到芯片204、215以及如前所述的引线框结构210中的引线。合适的导线接合工艺(例如,超声波接合)为本领域技术人员所公知。
如图4(e)中所示,随后使用常规模塑工艺在引线框结构210、芯片204、215和各条导线(例如,206(a)-1、206(a)-2)的至少一部分的周围形成模塑材料202。
图5示出了结合前述多芯片模块200的电路图。参看图2和5两者,B-对应于引线210(b)-1,P-对应于引线210(b)-2,Vdd对应于引线210(b)-3,而VM对应于引线210(b)-4。图5中的多芯片模块200有益地结合图1附图中的许多电子组件。多芯片模块200使得形成电池保护电路更容易,因为电路的许多组件存在于单个较小形状因数的模块中。
图6示出模块200的组件的内部电路图。在图6中,有IC芯片215和由该IC芯片215控制的两个MOSFET 204(m)-1、204(m)-2。参看图2和6,IC芯片端子Vss可连接到导线208(s)-1,端子DO可连接到导线218(g)-1,端子VM可连接到导线222,而端子CO可连接到218(g)-2。将模块200安装到电路板也比将许多分立组件安装到电路板更容易。
图7示出模块200的仰视图。在此附图中,前述测试引线未被示出。如图7中所示,模块200的底表面包括管芯安装焊盘210(a)-1、210(a)-2的曝露面以及引线210(b)-1、210(b)-2、210(b)-3、210(b)-4的曝露面。如所示,模塑材料202的外表面基本上与引线210(b)-1、210(b)-2、210(b)-3、210(b)-4和管芯安装焊盘210(a)-1、210(a)-2的曝露外表面共面。如所示,一个维度可以是约2.0毫米,而另一纵向维度可以是长约5.0毫米。此示例中的模块具有大于2的纵横比。
图8示出包括以模块200安装到其上的电路板302的电组装件300。其它电气组件304也可被安装到电路板302上。
图9示出包括连接到锂离子电池400的前述电组装件300的系统。如 图8和9中所示,模块200的特定形状因数允许与锂离子电池400一起使用的电池保护电路更为紧致。
图10(a)示出另一模块实施例的底部平面图。图10(b)示出用在图10(a)的模块中的引线框结构和管芯的顶部立体图。图10(c)示出图10(b)中所示引线框结构的顶部立体图。在图10(a)-10(c)中,许多附图标记已在上文进行了描述。
图10(a)中的实施例可类似于以上参照图2-4描述的实施例。然而,在此实施例中,模块具有在该模块的末端而非在该模块的侧面(例如,如图2中所示)处的测试引线210(c)。在此示例中,测试引线210(c)在引线210(b)-3与210(b)-4之间。而且,如图10(b)和10(c)中所示,引线框结构210可具有比以上参照图2-4描述的引线框结构210更少的系杆224(例如,每侧3个系杆,取代每侧6个系杆)。这些变化会有助于在切割期间减小机械应力(如与参照图2-4所描述的实施例相比较)。而且,通过在模块的末端提供测试引线210(c),第二安装焊盘210(a)-2可以是较宽的,并可容纳较大的IC芯片。
另外,与图2-4中的引线框结构210相比,图10(b)-10(c)中的引线框结构210中,引线210(b)-1、210(b)-2、210(b)-3、210(b)-4略长。通过使用较长的引线,模块与电路板之间的焊接点的大小可增大。
根据本发明的实施例的多芯片模块可用在无线电话系统、膝上型计算机、服务器计算机、电源等的各种系统中。
“一”、“一个”或“该”的任何列举旨在表示“一个或多个”,除非特别指示其相反方面。
以上描述是示例性的而非限制性的。鉴于以上公开,本发明的许多变化将变得为本领域技术人员所显见。因此,本发明的范围不应当根据以上描述来确定,而是相反,应当待批权利要求连同它们的全部范围或等效方案一起来确定。
Claims (6)
1.一种多芯片模块,包括:
至少一个集成电路(IC)芯片;
至少一个功率器件芯片;
金属引线框结构,它包括引线、彼此电隔离的至少两个独立管芯安装焊盘,所述至少两个独立管芯安装焊盘包括用于安装至少一个IC芯片的第一焊盘和用于安装至少一个功率器件芯片的第二焊盘;
接合导线,用于将所述至少一个IC芯片和所述至少一个功率器件芯片连接到所述引线,所述接合导线中的多个第一接合导线具有第一直径,所述接合导线中的多个第二接合导线具有第二直径,所述第一直径大于所述第二直径;以及
所述管芯安装焊盘中的至少一个沿着所述焊盘的两个相对侧皆没有外部引线、安装焊盘或其它管芯安装焊盘。
2.如权利要求1所述的模块,其特征在于,包括从一个芯片到另一个芯片的接合导线。
3.如权利要求1所述的模块,其特征在于,所述安装焊盘在所述模块的背面上曝露出,并且其中所述模块包括环氧模塑材料。
4.如权利要求1所述的模块,其特征在于,所述引线框结构包括专用测试引线。
5.一种制造多芯片模块的方法,包括:
获得包括引线、彼此电隔离的至少两个独立管芯安装焊盘的金属引线框结构,所述至少两个独立管芯安装焊盘包括用于安装至少一个IC芯片的第一焊盘和用于安装至少一个功率器件芯片的第二焊盘,其中,所述管芯安装焊盘中的至少一个沿着所述焊盘的两个相对侧皆没有外部引线、安装焊盘或其它管芯安装焊盘;
将所述至少一个IC芯片安装到所述第一焊盘;
将所述至少一个功率器件芯片安装到所述第二焊盘;以及
将接合导线附连到所述至少一个IC芯片并将所述至少一个功率器件芯片附连到所述引线,所述接合导线中的多个第一接合导线具有第一直径,所述接合导线中的多个第二接合导线具有第二直径,所述第一直径大于所述第二直径。
6.如权利要求5所述的方法,其特征在于,还包括在所述金属引线框结构、所述至少一个IC芯片、所述至少一个功率器件芯片和所述接合导线的至少一部分的周围使模塑材料模塑成形。
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Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5291864B2 (ja) * | 2006-02-21 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | Dc/dcコンバータ用半導体装置の製造方法およびdc/dcコンバータ用半導体装置 |
US7872350B2 (en) * | 2007-04-10 | 2011-01-18 | Qimonda Ag | Multi-chip module |
US8097945B2 (en) * | 2007-11-21 | 2012-01-17 | Lynda Harnden, legal representative | Bi-directional, reverse blocking battery switch |
US20100252918A1 (en) * | 2009-04-06 | 2010-10-07 | Jiang Hunt H | Multi-die package with improved heat dissipation |
US9257467B2 (en) * | 2009-12-16 | 2016-02-09 | Samsung Electronics Co., Ltd. | Image sensor modules, methods of manufacturing the same, and image processing systems including the image sensor modules |
CN102130098B (zh) * | 2010-01-20 | 2015-11-25 | 飞思卡尔半导体公司 | 双管芯半导体封装 |
US9418919B2 (en) * | 2010-07-29 | 2016-08-16 | Nxp B.V. | Leadless chip carrier having improved mountability |
US8614503B2 (en) * | 2011-05-19 | 2013-12-24 | International Rectifier Corporation | Common drain exposed conductive clip for high power semiconductor packages |
CN102956509A (zh) * | 2011-08-31 | 2013-03-06 | 飞思卡尔半导体公司 | 功率器件和封装该功率器件的方法 |
JP5412559B2 (ja) * | 2012-06-15 | 2014-02-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8723300B2 (en) | 2012-08-13 | 2014-05-13 | Fairchild Semiconductor Corporation | Multi-chip module power clip |
KR102071078B1 (ko) * | 2012-12-06 | 2020-01-30 | 매그나칩 반도체 유한회사 | 멀티 칩 패키지 |
DE102013203280A1 (de) * | 2013-02-27 | 2014-08-28 | Bayerische Motoren Werke Aktiengesellschaft | Hochvolt-Energiespeichermodul und Verfahren zur Herstellung des Hochvolt-Energiespeichermoduls |
CN204030643U (zh) | 2013-06-01 | 2014-12-17 | 快捷半导体(苏州)有限公司 | 用于电池管理和保护的系统及设备 |
EP2822063B1 (en) * | 2013-07-01 | 2017-05-31 | Samsung SDI Co., Ltd. | Protection apparatus for a battery pack and method of manufacturing the protection apparatus |
US9142432B2 (en) | 2013-09-13 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package structures with recesses in molding compound |
CN105098132A (zh) * | 2014-05-15 | 2015-11-25 | (株)Itm半导体 | 电池保护电路组件 |
DE102014212247A1 (de) * | 2014-06-26 | 2015-12-31 | Robert Bosch Gmbh | Elektrischer Verbinder für ein Batteriemodul |
JP6379778B2 (ja) * | 2014-07-15 | 2018-08-29 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN104332465B (zh) * | 2014-09-03 | 2017-05-17 | 江阴芯智联电子科技有限公司 | 一种3d封装结构及其工艺方法 |
US10845407B2 (en) * | 2018-06-25 | 2020-11-24 | Intel Corporation | Scalable infield scan coverage for multi-chip module for functional safety mission application |
CN111834350B (zh) * | 2019-04-18 | 2023-04-25 | 无锡华润安盛科技有限公司 | Ipm的封装方法以及ipm封装中的键合方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313095A (en) * | 1992-04-17 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Multiple-chip semiconductor device and a method of manufacturing the same |
US6943434B2 (en) * | 2002-10-03 | 2005-09-13 | Fairchild Semiconductor Corporation | Method for maintaining solder thickness in flipchip attach packaging processes |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3956821A (en) * | 1975-04-28 | 1976-05-18 | Fairchild Camera And Instrument Corporation | Method of attaching semiconductor die to package substrates |
US4058899A (en) * | 1976-08-23 | 1977-11-22 | Fairchild Camera And Instrument Corporation | Device for forming reference axes on an image sensor array package |
US4382221A (en) * | 1979-12-14 | 1983-05-03 | Reynolds William R | Battery charger for a backup power circuit |
US4680613A (en) * | 1983-12-01 | 1987-07-14 | Fairchild Semiconductor Corporation | Low impedance package for integrated circuit die |
US4751199A (en) * | 1983-12-06 | 1988-06-14 | Fairchild Semiconductor Corporation | Process of forming a compliant lead frame for array-type semiconductor packages |
US4772935A (en) * | 1984-12-19 | 1988-09-20 | Fairchild Semiconductor Corporation | Die bonding process |
US4890153A (en) * | 1986-04-04 | 1989-12-26 | Fairchild Semiconductor Corporation | Single bonding shelf, multi-row wire-bond finger layout for integrated circuit package |
US4720396A (en) * | 1986-06-25 | 1988-01-19 | Fairchild Semiconductor Corporation | Solder finishing integrated circuit package leads |
US4791473A (en) * | 1986-12-17 | 1988-12-13 | Fairchild Semiconductor Corporation | Plastic package for high frequency semiconductor devices |
US4839717A (en) * | 1986-12-19 | 1989-06-13 | Fairchild Semiconductor Corporation | Ceramic package for high frequency semiconductor devices |
US4731701A (en) * | 1987-05-12 | 1988-03-15 | Fairchild Semiconductor Corporation | Integrated circuit package with thermal path layers incorporating staggered thermal vias |
US4796080A (en) * | 1987-07-23 | 1989-01-03 | Fairchild Camera And Instrument Corporation | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate |
US5327325A (en) * | 1993-02-08 | 1994-07-05 | Fairchild Space And Defense Corporation | Three-dimensional integrated circuit package |
US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
JP3429921B2 (ja) * | 1995-10-26 | 2003-07-28 | 三菱電機株式会社 | 半導体装置 |
US6049126A (en) * | 1995-12-14 | 2000-04-11 | Nec Corporation | Semiconductor package and amplifier employing the same |
US5646446A (en) * | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
JP2885213B2 (ja) * | 1997-01-23 | 1999-04-19 | 日本電気株式会社 | 半導体集積回路 |
US5703463A (en) * | 1997-02-18 | 1997-12-30 | National Semiconductor Corporation | Methods and apparatus for protecting battery cells from overcharge |
US6184585B1 (en) * | 1997-11-13 | 2001-02-06 | International Rectifier Corp. | Co-packaged MOS-gated device and control integrated circuit |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6424035B1 (en) * | 1998-11-05 | 2002-07-23 | Fairchild Semiconductor Corporation | Semiconductor bilateral switch |
KR100335480B1 (ko) * | 1999-08-24 | 2002-05-04 | 김덕중 | 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지 |
KR100335481B1 (ko) * | 1999-09-13 | 2002-05-04 | 김덕중 | 멀티 칩 패키지 구조의 전력소자 |
JP4617524B2 (ja) * | 1999-10-29 | 2011-01-26 | ミツミ電機株式会社 | 電池保護装置 |
US6720642B1 (en) * | 1999-12-16 | 2004-04-13 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package and method of manufacture thereof |
US6989588B2 (en) * | 2000-04-13 | 2006-01-24 | Fairchild Semiconductor Corporation | Semiconductor device including molded wireless exposed drain packaging |
JP2001320009A (ja) * | 2000-05-10 | 2001-11-16 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US6556750B2 (en) * | 2000-05-26 | 2003-04-29 | Fairchild Semiconductor Corporation | Bi-directional optical coupler |
KR100370231B1 (ko) * | 2000-06-13 | 2003-01-29 | 페어차일드코리아반도체 주식회사 | 리드프레임의 배면에 직접 부착되는 절연방열판을구비하는 전력 모듈 패키지 |
KR100403608B1 (ko) * | 2000-11-10 | 2003-11-01 | 페어차일드코리아반도체 주식회사 | 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법 |
TW511257B (en) * | 2000-12-11 | 2002-11-21 | Chino Excel Technology Corp | Flip-chip mounting method for decreasing conducting resistance in power transistor of charging battery protection circuit |
KR100374629B1 (ko) * | 2000-12-19 | 2003-03-04 | 페어차일드코리아반도체 주식회사 | 얇고 작은 크기의 전력용 반도체 패키지 |
US6469384B2 (en) * | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US6891257B2 (en) * | 2001-03-30 | 2005-05-10 | Fairchild Semiconductor Corporation | Packaging system for die-up connection of a die-down oriented integrated circuit |
US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
US7061080B2 (en) * | 2001-06-11 | 2006-06-13 | Fairchild Korea Semiconductor Ltd. | Power module package having improved heat dissipating capability |
US6683375B2 (en) * | 2001-06-15 | 2004-01-27 | Fairchild Semiconductor Corporation | Semiconductor die including conductive columns |
US6449174B1 (en) * | 2001-08-06 | 2002-09-10 | Fairchild Semiconductor Corporation | Current sharing in a multi-phase power supply by phase temperature control |
US6774465B2 (en) * | 2001-10-05 | 2004-08-10 | Fairchild Korea Semiconductor, Ltd. | Semiconductor power package module |
US6891256B2 (en) * | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
US6642738B2 (en) * | 2001-10-23 | 2003-11-04 | Fairchild Semiconductor Corporation | Method and apparatus for field-effect transistor current sensing using the voltage drop across drain to source resistance that eliminates dependencies on temperature of the field-effect transistor and/or statistical distribution of the initial value of drain to source resistance |
US6747445B2 (en) * | 2001-10-31 | 2004-06-08 | Agere Systems Inc. | Stress migration test structure and method therefor |
US6674157B2 (en) * | 2001-11-02 | 2004-01-06 | Fairchild Semiconductor Corporation | Semiconductor package comprising vertical power transistor |
US6566749B1 (en) * | 2002-01-15 | 2003-05-20 | Fairchild Semiconductor Corporation | Semiconductor die package with improved thermal and electrical performance |
US6830959B2 (en) * | 2002-01-22 | 2004-12-14 | Fairchild Semiconductor Corporation | Semiconductor die package with semiconductor die having side electrical connection |
US6867489B1 (en) * | 2002-01-22 | 2005-03-15 | Fairchild Semiconductor Corporation | Semiconductor die package processable at the wafer level |
DE10392377T5 (de) * | 2002-03-12 | 2005-05-12 | FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) | Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer |
US7183616B2 (en) * | 2002-03-31 | 2007-02-27 | Alpha & Omega Semiconductor, Ltd. | High speed switching MOSFETS using multi-parallel die packages with/without special leadframes |
US7122884B2 (en) * | 2002-04-16 | 2006-10-17 | Fairchild Semiconductor Corporation | Robust leaded molded packages and methods for forming the same |
US6836023B2 (en) * | 2002-04-17 | 2004-12-28 | Fairchild Semiconductor Corporation | Structure of integrated trace of chip package |
US6841852B2 (en) * | 2002-07-02 | 2005-01-11 | Leeshawn Luo | Integrated circuit package for semiconductor devices with improved electric resistance and inductance |
US7061077B2 (en) * | 2002-08-30 | 2006-06-13 | Fairchild Semiconductor Corporation | Substrate based unmolded package including lead frame structure and semiconductor die |
US6777800B2 (en) * | 2002-09-30 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor die package including drain clip |
US6806580B2 (en) * | 2002-12-26 | 2004-10-19 | Fairchild Semiconductor Corporation | Multichip module including substrate with an array of interconnect structures |
US6909298B2 (en) * | 2003-04-07 | 2005-06-21 | Silicon Laboratories, Inc. | Test socket with integral inductor and method of manufacturing using such a test socket |
US6867481B2 (en) * | 2003-04-11 | 2005-03-15 | Fairchild Semiconductor Corporation | Lead frame structure with aperture or groove for flip chip in a leaded molded package |
US7329968B2 (en) * | 2003-05-08 | 2008-02-12 | The Trustees Of Columbia University In The City Of New York | Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits |
JP4248953B2 (ja) * | 2003-06-30 | 2009-04-02 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US7034385B2 (en) * | 2003-08-05 | 2006-04-25 | International Rectifier Corporation | Topless semiconductor package |
JP2005217072A (ja) * | 2004-01-28 | 2005-08-11 | Renesas Technology Corp | 半導体装置 |
JP4489485B2 (ja) | 2004-03-31 | 2010-06-23 | 株式会社ルネサステクノロジ | 半導体装置 |
US20070132075A1 (en) * | 2005-12-12 | 2007-06-14 | Mutsumi Masumoto | Structure and method for thin single or multichip semiconductor QFN packages |
KR200412109Y1 (ko) | 2006-01-13 | 2006-03-22 | 주식회사 아이티엠반도체 | 배터리 보호기능을 구비한 패키징 아이씨 |
-
2007
- 2007-02-08 US US11/672,728 patent/US7868432B2/en active Active
- 2007-02-09 KR KR1020087022266A patent/KR101399481B1/ko active IP Right Grant
- 2007-02-09 MY MYPI20083036 patent/MY144406A/en unknown
- 2007-02-09 DE DE200711000352 patent/DE112007000352T5/de not_active Withdrawn
- 2007-02-09 JP JP2008554522A patent/JP2009527109A/ja active Pending
- 2007-02-09 WO PCT/US2007/061931 patent/WO2007095468A2/en active Application Filing
- 2007-02-09 CN CN2011103178322A patent/CN102354690A/zh active Pending
- 2007-02-09 CN CN2007800051730A patent/CN101443979B/zh not_active Expired - Fee Related
- 2007-02-12 TW TW96105092A patent/TWI435507B/zh active
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2010
- 2010-12-09 US US12/964,691 patent/US8003447B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313095A (en) * | 1992-04-17 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Multiple-chip semiconductor device and a method of manufacturing the same |
US6943434B2 (en) * | 2002-10-03 | 2005-09-13 | Fairchild Semiconductor Corporation | Method for maintaining solder thickness in flipchip attach packaging processes |
Also Published As
Publication number | Publication date |
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US20110078899A1 (en) | 2011-04-07 |
CN101443979A (zh) | 2009-05-27 |
KR20080105077A (ko) | 2008-12-03 |
US20070187807A1 (en) | 2007-08-16 |
US8003447B2 (en) | 2011-08-23 |
MY144406A (en) | 2011-09-15 |
CN102354690A (zh) | 2012-02-15 |
WO2007095468A3 (en) | 2008-05-15 |
KR101399481B1 (ko) | 2014-05-27 |
TW200737640A (en) | 2007-10-01 |
DE112007000352T5 (de) | 2009-04-02 |
JP2009527109A (ja) | 2009-07-23 |
TWI435507B (zh) | 2014-04-21 |
US7868432B2 (en) | 2011-01-11 |
WO2007095468A2 (en) | 2007-08-23 |
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