CN101499450A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN101499450A
CN101499450A CNA2009100052556A CN200910005255A CN101499450A CN 101499450 A CN101499450 A CN 101499450A CN A2009100052556 A CNA2009100052556 A CN A2009100052556A CN 200910005255 A CN200910005255 A CN 200910005255A CN 101499450 A CN101499450 A CN 101499450A
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Prior art keywords
lead
die pad
pad portion
wire
semiconductor device
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CNA2009100052556A
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CN101499450B (zh
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谷藤雄一
中条卓也
冈浩伟
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NEC Electronics Corp
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Renesas Technology Corp
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Abstract

本发明使得介在于半导体芯片和芯片垫部之间的导电性接着剂的接合可靠性提高。硅芯片3A搭载在与漏极引线Ld一体形成的芯片垫部4D上，且在硅芯片3A的主面上形成有源极垫7。硅芯片3A的背面构成一功率MOSFET的漏极，且经由Ag膏5而接合于芯片垫部4D上。源极引线Ls与源极垫7是通过Al带10而电性连接。在硅芯片3A的背面上形成有Ag纳米粒子涂膜9A，在芯片垫部4D与引线(漏极引线Ld、源极引线Ls)的表面上形成有Ag纳米粒子涂膜9B。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造技术，特别涉及一种应用于具有封装的功率半导体装置中而有效的技术，所述封装是指经由导电性接着剂等而将半导体芯片(semiconductor chip)接合于引线框的芯片垫(die pad)部上。
背景技术
便携式信息设备的电力控制开关或者充放电保护电路开关等所使用的功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)，是被密封在SOP(Small OutLine Package，小外型封装)8等的小型表面安装封装中。
此种功率半导体装置用表面安装封装例如具有如下构造。即，形成有功率MOSFET的半导体芯片以其主面朝上的状态而搭载在与漏极引线一体形成的芯片垫部之上，且经由Ag膏的等导电性接着剂而黏接到芯片垫部上。在半导体芯片的背面上，形成有连接于功率MOSFET的漏极的漏极电极。另一方面，在半导体芯片的主面上，形成有源极垫与栅极垫。为了降低功率MOSFET的导通电阻，源极垫是以相比栅极垫较大的面积所构成。源极垫与栅极垫分别经由Au线而与引线电性连接。而且，这些构件(芯片垫部、半导体芯片、Au线、引线)利用模铸树脂而密封。
在技术论文11th Symposium on“Microjoining and Assembly Technology inElectronics”，pp233-238，(2005.2)(非专利文献1)中，报告了如下内容：作为功率半导体装置用的导电性接着剂，对在现有的Ag膏中混合有Ag纳米粒子而形成的纳米复合Ag膏材料的使用进行了研究。
而且，日本专利特开2005-277168号公报(专利文献1)中揭示有一种功率半导体装置用封装，其利用由铜或铜合金所构成的板状的夹具将半导体芯片的源极垫与引线加以电性连接而形成。此专利文献中所揭示的封装是利用导电性接着剂将源极垫与夹具、以及引线与夹具分别黏接在一起。此导电性接着剂的特征在于：在黏合树脂中含有由具有塑性的铝或铟等组成的导电性粒子，因黏接而导致的塑性变形前的所述导电性接着剂的至少一部分的粒径，具有被黏接的源极垫与夹具的间隙距离、及引线与夹具的间隙距离的最大值以上的尺寸。
专利文献1：日本专利特开2005-277168号公报
非专利文献1：11th Symposium on“Microjoining and Assembly Technology inElectronics”，pp233-238，(2005.2)
发明内容
近年来，随着功率半导体装置的高性能化，要求进一步降低功率MOSFET的导通电阻。因此，以前，对于以具有可挠性的金属带(metal ribbon)将经由Au线而电性连接的源极垫与引线加以连接的情况进行了研究。此金属带例如是由厚度为数百微米(μm)左右的Al箔或Cu箔等所构成，其宽度随着源极垫的宽度而有所不同，但一般为1mm左右。因此，通过金属带将源极垫与引线加以连接，从而与通过Au线将源极垫与引线加以连接的情况相比，可大幅降低源电阻(source resistance)。
为了将金属带连接到源极垫和引线上，使用了利用有超声波振动的楔焊(wedgebonding)法。然而，金属带焊接时施加到源极垫表面的超声波振动能量，远大于Au线焊接时施加到源极垫表面的超声波振动能量(一般为5W～10W左右)。因此，当利用金属带来连接源极垫与引线时，介在于半导体芯片和芯片垫部之间的Ag膏等的导电性接着剂会因超声波振动能量而受到损伤。其结果产生如下不良情况：导电性接着剂的接着强度会降低；或者在金属带焊接时硅芯片会从芯片垫部剥离；或者导电性接着剂的导电率会降低等。
本发明的目的在于提供一种使得介在于半导体芯片和芯片垫部之间的导电性接着剂的接合可靠性提高的技术。
本发明的其它目的在于提供一种推进功率半导体装置大容量化的技术。
本发明的所述以及其它目的和新颖特征可根据本说明书的记述及附图而明确了解。
本申请案所揭示的发明中，对代表性内容的概要的简单说明如下所述。
本发明的半导体装置包含：引线框，其具有芯片垫部和配置在所述芯片垫部附近的第一引线；半导体芯片，其以面朝上(face up)方式搭载在所述芯片垫部上，且在主面上具有第一垫；导电体，其将所述第一引线与所述第一垫加以电性连接；及树脂封装，其将所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以密封；且在所述引线框的表面上，形成有将Ag的纳米粒子烧结所成的第一多孔质金属层；所述芯片垫部与所述半导体芯片的背面经由Ag膏而黏接在一起。
本发明的半导体装置的制造方法包含以下步骤：(a)准备具有芯片垫部和配置在所述芯片垫部附近的第一引线的引线框，并在所述引线框的表面上，形成将Ag的纳米粒子烧结所成的第一多孔质金属层；(b)准备在主面上具有第一垫的半导体芯片；(c)在将Ag膏供给于所述芯片垫部上之后，以面朝上方式将所述半导体芯片搭载在所述芯片垫部上；(d)在所述(c)步骤之后，使所述Ag膏固化，以此将所述芯片垫部与所述半导体芯片的背面经由所述Ag膏而黏接在一起；(e)在所述(d)步骤之后，通过导电体将所述第一引线与所述第一垫加以电性连接；及(f)在所述(e)步骤之后，对所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以树脂密封。
[发明的效果]
本申请案所揭示的发明中，对于代表性内容所获得的效果的简单说明如下所述。
使得介在于半导体芯片和芯片垫部之间的导电性接着剂的接合可靠性提高。
附图说明
图1是表示作为本发明实施形态1的半导体装置的外观的俯视图。
图2是表示作为本发明实施形态1的半导体装置的外观的侧视图。
图3是表示作为本发明实施形态1的半导体装置的内部构造的俯视图。
图4是沿着图3的A-A线的剖面图。
图5是沿着图3的B-B线的剖面图。
图6是将硅芯片与芯片垫部的接合部放大表示的剖面图。
图7是表示硅芯片上所形成的功率MOSFET的主要部分剖面图。
图8是表示包含形成在硅芯片上的源极垫、栅极垫和栅极配线在内的最上层的导电膜与下层的栅极电极的俯视图。
图9是表示实施形态1中所使用的引线框的制造步骤的流程图。
图10(a)是表示作为实施形态1中所使用的引线框的原料的铜条的侧视图，图10(b)是此铜条的部分俯视图。
图11是表示引线框的完成状态的俯视图。
图12是表示实施形态1中所使用的硅芯片的制造步骤的流程图。
图13(a)、(b)、(c)是以步骤顺序来表示在半导体晶片的背面上形成Ag纳米粒子涂膜的方法的说明图。
图14是表示实施形态1的半导体装置的制造步骤的流程图。
图15是实施形态1的半导体装置的制造步骤中所使用的分配器的侧视图。
图16是表示实施形态1的半导体装置的制造方法的引线框的主要部分俯视图。
图17是表示实施形态1的半导体装置的制造方法的引线框的主要部分俯视图。
图18是实施形态1的半导体装置的制造步骤中所使用的楔形工具的主要部分侧视图。
图19是表示实施形态1的Al带的焊接步骤的主要部分剖面图。
图20是表示实施形态1的Al带的焊接步骤的主要部分剖面图。
图21是表示实施形态1的Al带的焊接步骤的主要部分剖面图。
图22是表示实施形态1的Al带的焊接步骤的主要部分剖面图。
图23是表示实施形态1的半导体装置的制造方法的引线框的主要部分俯视图。
图24是表示实施形态1的半导体装置的制造方法的引线框的主要部分俯视图。
图25是表示作为本发明实施形态2的半导体装置的内部构造的俯视图。
图26是沿着图25的C-C线的剖面图。
图27是表示实施形态2的半导体装置的制造步骤的流程图。
图28是表示实施形态2的半导体芯片的焊接方法的概略剖面图。
图29是表示作为本发明实施形态3的半导体装置的剖面图。
图30是表示作为本发明实施形态4的半导体装置的表面侧外观的俯视图。
图31是表示作为本发明实施形态4的半导体装置的背面侧外观的俯视图。
图32是表示作为本发明实施形态4的半导体装置的内部构造的俯视图。
图33是表示实施形态4中所使用的Ag膏的制造步骤的流程图。
图34是表示实施形态4的半导体装置的制造步骤的流程图。
图35是对实施形态4中所使用的Ag膏的效果加以说明的示图。
图36是表示Ag膏厚度与Ag膏断裂超声波输出间的关系的图表。
图37是表示Ag膏厚度与金属带焊接时施加到Ag膏上的最大应力间的关系的图表。
[符号的说明]
1A、1B、1C  半导体装置(SOP8)
2           模铸树脂
3A、3B      硅芯片
4D          芯片垫部
5           Ag膏
5A          Ag填料
5B          环氧树脂
6            漏极电极
7            源极垫(源极电极)
8            栅极垫
9A、9B       Ag纳米粒子涂膜(多孔质金属层)
10           Al带
11           Au线
12           硅晶片
14           Ag膏
15           衬垫树脂
20           n+型单晶硅基板
21           n-型单晶硅层
22           p型井
23           氧化硅膜
24           槽
25           氧化硅膜(栅极氧化膜)
26A          多晶硅膜(栅极电极)
26B          栅极引出电极
27           p-型半导体区域
28           p型半导体区域
29           n+型半导体区域(源极)
30、31       氧化硅膜
32、33       连接孔
34           栅极配线
35           p+型半导体区域
36、37、38   Al配线
40           铜条
41           分配器
42           注射器
44           楔形工具
45           带导向件
46           切刀
48         芯片焊接平台
49         焊接夹头
L          引线
Ld         漏极引线
LF         引线框
Lg         栅极引线
Ls         源极引线
具体实施方式
以下，根据附图来详细说明本发明的实施形态。另外，在用以说明实施形态的所有图中，对于相同的构件，原则上标注相同的符号，并省略其重复的说明。而且，在以下的实施形态中，除了特别必要时以外，原则上不重复进行同一或者同样的部分的说明。
(实施形态1)
图1～图5是表示本实施形态的半导体装置的示图，图1是表示外观的俯视图，图2是表示外观的侧视图，图3是表示内部构造的俯视图，图4是沿着图3的A-A线的剖面图，图5是沿着图3的B-B线的剖面图。
本实施形态的半导体装置1A是作为小型表面安装封装的一种的SOP8所应用的装置。在由环氧系树脂所构成的模铸树脂2的外部，露出有构成SOP8的外部连接端子的八条引线L的外部引线部。在图1所示的引线L中，从第一条引线到第三条引线是源极引线Ls，第四条引线是栅极引线Lg，从第五条引线至第八条引线是漏极引线Ld。
在模铸树脂2的内部，密封有例如具有长边×短边＝3.9mm×2.2mm的平面尺寸的硅芯片3A。在此硅芯片3A的主面上，形成有功率MOSFET，此功率MOSFET使用于例如便携式信息设备的电力控制开关或充放电保护电路开关等。关于此功率MOSFET的构成，将于以下叙述。
硅芯片3A是以其主面朝上的状态而搭载在与四条漏极引线Ld(第五条引线～第八条引线)一体形成的芯片垫部4D上。在硅芯片3A的背面上，形成有连接于功率MOSFET的漏极的漏极电极6，在此漏极电极6的表面上，形成有Ag纳米粒子涂膜(第二多孔质金属层)9A。另一方面，芯片垫部4D和八条引线L(第一条引线～第八条引线)是由铜所构成，在它们的全体表面或者一部分表面上，形成有Ag纳米粒子涂膜(第一多孔质金属层)9B。而且，在两层Ag纳米粒子涂膜9A、9B之间，形成有Ag膏5。即，硅芯片3A的漏极电极6与芯片垫部4D是通过两层Ag纳米粒子涂膜9A、9B和介在于它们之间的Ag膏5而彼此接合。
在硅芯片3A的主面上，形成有源极垫(源极电极)7和栅极垫8。源极垫7和栅极垫8是由形成在硅芯片3A最上层的Al合金膜所构成。为了降低功率MOSFET的导通电阻，源极垫7是以相比栅极垫8较大的面积所构成。基于同样的理由，硅芯片3A的背面的整个面构成功率MOSFET的漏极电极6。
本实施形态的半导体装置1A中，三条源极引线Ls(第一条引线～第三条引线)在模铸树脂2的内部连结，此连结的部分与源极垫7是通过Al带10而电性连接。Al带10的厚度为0.1mm左右，宽度为1mm左右。为了降低功率MOSFET的导通电阻，较理想的是使Al带10的宽度接近源极垫7的宽度从而增大Al带10与源极垫7的接触面积。另一方面，一条栅极引线Lg(第四条引线)与栅极垫8是通过一条Au线11而电性连接。
图6是将硅芯片3A与芯片垫部4D的接合部放大表示的剖面图。硅芯片3A的背面上形成有漏极电极6，此漏极电极6的表面上形成有Ag纳米粒子涂膜9A。同样，芯片垫部4D的表面上形成有Ag纳米粒子涂膜9B。漏极电极6例如是由从靠近硅芯片3A处起依次积层有Ti膜、Ni膜、Au膜而成的金属膜所构成，最表面的Au膜例如是以100nm～5μm的膜厚所形成。而且，Ag纳米粒子涂膜9A、9B各自的膜厚例如为100nm～10μm。
另一方面，介在于Ag纳米粒子涂膜9A、9B之间的Ag膏5是由将Ag填料5A混入到环氧树脂5B中而成的导电性树脂所构成，其膜厚例如为10μm～20μm。而且，Ag膏5中的Ag填料5A的含量为65wt％～98wt％。如果Ag填料5A的含量小于65wt％，则电性导通特性不充分，如果所述含量大于98wt％，则接着特性会下降。
此处，Ag膏5中所含的Ag填料5A的平均粒径例如为0.5μm～50μm，与此相对，构成Ag纳米粒子涂膜9A、9B的Ag粒子的平均粒径例如为1nm～50nm，从而其具有与Ag填料5A相比非常微细的特征。而且，Ag纳米粒子涂膜9A、9B成为微细的Ag粒子彼此熔合、凝集而粗大化的多孔质构造，且成为膜表面的凹凸也显着而富有起伏的膜。因此，与Ag纳米粒子涂膜9A、9B各自的界面相接触的区域的Ag膏5，是在环氧树脂5B侵入到Ag纳米粒子涂膜9A、9B的孔内的状态下固化。由此，在环氧树脂5B的锚定效果(anchor effect)的作用下，硅芯片3A的漏极电极6与Ag膏5、以及芯片垫部4D与Ag膏5分别被牢固地接合在一起，从而硅芯片3A与芯片垫部4D的界面剥离得到抑制。
而且，本实施形态的SOP8不仅在搭载有硅芯片3A的芯片垫部4D的上表面、而且在芯片垫部4D的背面及八条引线L各自的整个表面上，均形成有Ag纳米粒子涂膜9B。因此，与Ag纳米粒子涂膜9B的界面相接触的区域的模铸树脂2是在侵入到Ag纳米粒子涂膜9B的孔内的状态下固化。由此，利用模铸树脂2的锚定效果，芯片垫部4D的背面与模铸树脂2、以及封装内部的引线L与模铸树脂2分别被牢固地接合在一起，从而芯片垫部4D的背面与模铸树脂2的界面剥离、以及引线L与模铸树脂2的界面剥离也得到抑制。
接着，对形成在所述硅芯片3A上的功率MOSFET进行简单说明。图7是表示作为功率MOSFET的一例的n通道型的沟槽栅极型功率MOSFET的硅芯片3A的主要部分剖面图。
在n+型单晶硅基板20的主面上，利用外延生长法而形成有n-型单晶硅层21。n+型单晶硅基板20和n-型单晶硅层21构成一功率MOSFET的漏极。
在n-型单晶硅层21的一部分上，形成有p型井22。而且，在n-型单晶硅层21的表面的一部分上，形成有氧化硅膜23，在另一部分上形成有多个槽24。在n-型单晶硅层21的表面中的被氧化硅膜23所覆盖的区域构成元件分离区域，形成有槽24的区域构成元件形成区域(主动区域)。槽24的平面形状是四角形、六角形、八角形等的多角形或者朝一方向延伸的条纹状(未图示)。
在槽24的底部和侧壁上，形成有构成功率MOSFET的栅极氧化膜的氧化硅膜25。而且，在槽24的内部，埋入有构成功率MOSFET的栅极电极的多晶硅膜26A。另一方面，在氧化硅膜23的上部，形成有由多晶硅膜所构成的栅极引出电极26B，所述多晶硅膜是以与构成所述栅极电极的多晶硅膜26A相同的步骤堆积而成。栅极电极(多晶硅膜26A)与栅极引出电极26B在未图示的区域中电性连接。
在元件形成区域的n-型单晶硅层21上，形成有相比槽24较浅的p-型半导体区域27。此p-型半导体区域27构成一功率MOSFET的通道层。在p-型半导体区域27的上部，形成有相比p-型半导体区域27的杂质浓度较高的p型半导体区域28，且在p型半导体区域28的上部，形成有n+型半导体区域29。p型半导体区域28构成一功率MOSFET的穿通阻止层(punchthrough stopper layer)，n+型半导体区域29构成源极。
在形成有所述功率MOSFET的元件形成区域的上部、及形成有栅极引出电极26B的元件分离区域的上部，形成有两层氧化硅膜30、31。在元件形成区域上，形成有贯穿氧化硅膜31、30、p型半导体区域28和n+型半导体区域29而到达p-型半导体区域27的连接孔32。而且，在元件分离区域上，形成有贯穿氧化硅膜31、30而到达栅极引出电极26B的连接孔33。
在包含连接孔32、33内部的氧化硅膜31的上部，形成有由薄的TiW(钛钨)膜和厚的Al膜的积层膜所构成的源极垫7及栅极配线34。形成在元件形成区域上的源极垫7是穿过连接孔32而电性连接于功率MOSFET的源极(n+型半导体区域29)。在此连接孔32的底部，形成有用以使源极垫7与p-型半导体区域27欧姆接触的p+型半导体区域35。而且，形成在元件分离区域上的栅极配线34是经由连接孔33下部的栅极引出电极26B而连接于功率MOSFET的栅极电极(多晶硅膜26A)。
在源极垫7上，经楔焊法而电性连接有Al带10的一端。为了缓和焊接Al带10时功率MOSFET所受到的冲击，较理想的是将源极垫7在氧化硅膜32、33上部的厚度设为3μm以上。
图8是表示包含形成在硅芯片3A上的源极垫7、栅极垫8和栅极配线34在内的最上层的导电膜与下层的栅极电极(多晶硅膜26A)的俯视图。栅极配线34电性连接于栅极垫8，源极垫7电性连接于Al配线36。而且，在硅芯片3A的外周部，形成有Al配线37、38。栅极垫8和Al配线36、37、38是由与源极垫7和栅极配线34相同层的导电膜(TiW膜与Al膜的积层膜)所构成。在实际的硅芯片3A中，栅极配线34和Al配线36、37、38是由未图示的表面保护膜所覆盖，因此在硅芯片3A的表面上仅露出有所述最上层的导电膜中的源极垫7与栅极垫8。另外，在图7所示的例中，由于是将形成有栅极电极(多晶硅膜26A)的槽24的平面形状设为四角形，所以栅极电极(多晶硅膜26A)的平面形状也成为四角形。
接着，对以所述方式构成的SOP8(半导体装置1A)的制造方法进行说明。图9表示构成芯片垫部4D与引线L的引线框的制造流程。为了制造引线框，首先，准备如图10所示的引线框用的铜条40。图10(a)是卷绕成螺旋状的铜条40的整体图，图10(b)是表示其一部分的俯视图。铜条40例如是由厚度为100μm～150μm左右的铜板或铜合金板所构成。
然后，在此铜条40的整个面上形成膜厚为100nm～10μm左右的Ag纳米粒子涂膜9B。具体而言，调制出使Ag纳米粒子分散于挥发性有机溶剂或纯水等中的分散液，并利用浸渍法或喷涂法等将所述分散液粘附到铜条40的整个面上。此时，也可以向分散液中添加有机树脂等而调节粘度。
接下来，在250℃～400℃的大气中对所述铜条40进行加热、煅烧。由此，分散液中的溶剂及树脂成分消失，Ag纳米粒子彼此开始熔合，同时与铜条40的表面开始熔合。在此加热、煅烧步骤中，并非进行积极的加压处理，因此即便随着煅烧处理温度的上升或者时间的经过而使Ag纳米粒子彼此的熔合不断推进，Ag纳米粒子涂膜9B也不会致密化。因此，煅烧后的Ag纳米粒子涂膜9B成为在表面或内部形成有许多微细孔的多孔膜。而且，与铜条40接触的界面成为局部金属接合的状态。
其次，在氢气体环境中对铜条40进行还原处理，以此将所述加热、煅烧步骤中所生成的铜条40表面的氧化层去除，再对铜条40进行压制成形，形成如图11所示的引线框LF。这样，根据在铜条40的表面直接形成Ag纳米粒子涂膜9B的方法，还具有以下优点，即，可省略在通常的引线框的制造步骤中对铜条40表面进行镀敷处理的步骤。
另一方面，与所述引线框LF的制造并行，根据图12所示的制造流程，在硅芯片3A的背面形成Ag纳米粒子涂膜9A。具体而言，首先，准备如图13(a)所示的在背面形成有漏极电极6的硅晶片12。在此硅晶片12的主面上，按照晶片处理过程(waferprocess)而形成如图7所示的功率MOSFET，且在背面上，依次蒸镀Ti膜、Ni膜、Au膜而形成漏极电极6。
接着，如图13(b)所示，利用旋涂法等在硅晶片12的整个背面形成膜厚为100nm～10μm左右的Ag纳米粒子涂膜9A。Ag纳米粒子涂膜9A的原料可使用与所述Ag纳米粒子涂膜9B的原料(分散液)相同的原料。
接着，在250℃～400℃的大气中对所述硅晶片12进行加热、煅烧。由此，分散液中的溶剂及树脂成分消失，Ag纳米粒子彼此开始熔合，同时与漏极电极6的表面开始熔合。在此加热、煅烧步骤中，并非进行积极的加压处理，因此即便随着煅烧处理温度的上升或时间的经过而使Ag纳米粒子彼此的熔合不断推进，Ag纳米粒子涂膜9A也不会致密化。因此，煅烧后的Ag纳米粒子涂膜9A成为在表面或内部形成有许多微细孔的多孔膜。而且，与漏极电极6接触的界面成为局部金属接合的状态。
其次，利用药液或纯水来清洗硅晶片12，以此将在所述加热、煅烧步骤中生成的氧化层等异物去除，接着如图13(c)所示，使用金刚石刀片等对硅晶片12进行切割，从而获得在漏极电极6的表面形成有Ag纳米粒子涂膜9A的硅芯片3A。
图14是表示包含所述图9和图12所示的制造流程的SOP8(半导体装置1A)的全体制造流程的示图。
为了将硅芯片3A搭载在以所述方法而制造的引线框LF的芯片垫部4D上，首先，如图15所示，将Ag膏5填充到分配器41的注射器42内，且如图16所示，将Ag膏5供给到引线框LF的芯片垫部4D上。接着，如图17所示，将主面朝上的硅芯片3A按压到芯片垫部4D上。此时，Ag膏5中所含的未固化的液状环氧树脂的一部分会浸入到Ag纳米粒子涂膜9A、9B的微细的孔内。
然后，以200℃左右的温度对引线框LF进行加热以使Ag膏5固化。当进行此固化处理时，Ag膏5中的环氧树脂在其一部分进入到Ag纳米粒子涂膜9A、9B的微细的孔内的状态下固化。因此，在Ag纳米粒子涂膜9A、9B与Ag膏5的界面上机械锚定效果会发挥作用，从而硅芯片3A与芯片垫部4D经由Ag纳米粒子涂膜9A、9B及Ag膏5而牢固地密着。而且，在Ag纳米粒子涂膜9A与漏极电极6的界面、以及Ag纳米粒子涂膜9B与芯片垫部4D的界面上分别形成有金属键，所以这些界面的接着强度会增强，同时电阻会降低。
其次，通过使用有超声波的楔焊法来将Al带10焊接到硅芯片3A的源极垫7与源极引线Ls上。
图18是表示Al带10的焊接中所使用的楔形工具的前端部附近的侧视图。如图所示，在楔形工具44的其中一个侧面上，安装有带导向件45，以将穿过此带导向件45中的Al带10送出到楔形工具44的前端部。而且，在楔形工具44的另一个侧面上，以可上下移动的方式安装有对已送出到楔形工具44前端部的Al带10进行切断的切刀46。
为了使用所述楔形工具44而将Al带10焊接到硅芯片3A与源极引线Ls上，首先，如图19所示，将从带导向件45送出的Al带10的前端部定位到硅芯片3A的源极垫7上，然后将楔形工具44的底面压接到Al带10上并施加超声波振动。由此，与楔形工具44的底面接触的区域的Al带10会接合于源极垫7的表面。
接着，如图20所示，在使楔形工具44移动后，再一次将其底面压接到Al带10上并施加超声波振动。由此，与楔形工具44的底面接触的区域的Al带10会接合于源极垫7的表面。这样，在源极垫7的二个部位对Al带10进行楔焊，以此可确保Al带10与源极垫7的连接面积。
接着，如图21所示，使楔形工具44进一步移动，将其底面的中心定位到源极引线Ls的中心，然后将楔形工具44的底面压接到源极引线Ls上的Al带10上并施加超声波振动。由此，与楔形工具44的底面接触的区域的Al带10会接合于源极引线Ls的表面。
接着，如图22所示，将切刀46定位到源极引线Ls的端部上并使此切刀46下降。由此，未接合于源极引线Ls的区域的Al带10会被切断，从而Al带10连接于源极垫7与源极引线Ls。
根据以上所述，在将Al带10焊接到硅芯片3A与源极引线Ls上之后，如图23所示，通过利用有热与超声波的球形焊接法而将Au线11焊接到硅芯片3A的栅极垫8与栅极引线Lg上。
其次，使用模铸模具，利用模铸树脂2将硅芯片3A(及芯片垫部4D、Al带10、Au线11、引线L的内部引线部)加以密封(图24)。在此模铸步骤中，构成模铸树脂2的环氧树脂在其一部分进入到形成于引线L表面上的Ag纳米粒子涂膜9B的微细孔内的状态下固化。因此，在Ag纳米粒子涂膜9B与模铸树脂2的界面上机械锚定效果会发挥作用，从而引线L与模铸树脂2经由Ag纳米粒子涂膜9B而牢固地密着。
然后，将露出到模铸树脂2外部的引线L的无用部分切断、去除之后，使引线L成形为鸥翼状(gull wing)，最后，经过判别产品良否的分选步骤而完成SOP8(半导体装置1A)。
这样，根据本实施形态，在硅芯片3A的背面上形成Ag纳米粒子涂膜9A，在芯片垫部4D及引线L的表面上形成Ag纳米粒子涂膜9B，由此可强化硅芯片3A与芯片垫部4D的密着力。
另外，本实施形态是在引线框LF(芯片垫部4D和引线L)的表面上形成Ag纳米粒子涂膜9B，且在硅芯片3A的背面的漏极电极6上形成Ag纳米粒子涂膜9A的，但为了简化制造步骤，也可以省略在漏极电极6的表面上形成Ag纳米粒子涂膜9A的步骤。在此情况下，硅芯片3A与芯片垫部4D的密着力会稍有降低，但相比仅利用Ag膏5来将硅芯片3A与芯片垫部4D加以接合的背景技术仍可获得较牢固的密着力。而且，引线L与模铸树脂2是经由Ag纳米粒子涂膜9B而牢固地密着，因此相比背景技术可获得较牢固的密着力。
而且，本实施形态是使用铜来作为引线框LF的材料，但也可使用例如Fe-Ni合金。在此情况下，以所述方法在Fe-Ni合金的表面上直接形成Ag纳米粒子涂膜9B，由此也可获得同样的效果。
(实施形态2)
图25是表示本实施形态的半导体装置的内部构造的俯视图，图26是沿着图25的C-C线的剖面图。
本实施形态的半导体装置1B是与所述实施形态1同样地应用于SOP8的装置，但与所述实施形态1的SOP8的不同点在于，并未使用Ag膏5而是将硅芯片3A与芯片垫部4D直接接合。而且，引线L与源极垫7并非利用Al带10、而是利用多条Au线11来电性连接。
即，硅芯片3A是以其主面朝上的状态而搭载在与漏极引线Ld一体形成的芯片垫部4D上。在硅芯片3B的背面上，形成有连接于功率MOSFET的漏极的漏极电极6，在此漏极电极6的表面上，形成有Ag纳米粒子涂膜9A。另一方面，芯片垫部4D和八条引线L是由铜或铜合金所构成，在它们的表面上形成有Ag纳米粒子涂膜9B。并且，硅芯片3A的背面(漏极电极6)与芯片垫部4D是通过两层的Ag纳米粒子涂膜9A、9B而彼此接合在一起。
在硅芯片3A的主面上，形成有源极垫(源极电极)7和栅极垫8。源极垫7和栅极垫8是由形成在硅芯片3A最上层的Al合金膜所构成。为了降低功率MOSFET的导通电阻，源极垫7是以相比栅极垫8较大的面积所构成。基于同样的理由，硅芯片3A的背面的整个面构成功率MOSFET的漏极电极6。
本实施形态的半导体装置1B中，三条源极引线Ls(第一条引线～第三条引线)在模铸树脂2的内部连结，此连结的部分与源极垫7是通过多条Au线11而电性连接。另一方面，一条栅极引线Lg与栅极垫8是通过一条Au线11而电性连接。
接着，根据图27的制造流程图来说明以所述方式构成的SOP8(半导体装置1A)的制造方法。
首先，以与所述实施形态1同样的方法，在引线框LF的表面上形成Ag纳米粒子涂膜9B，且在硅芯片3A的背面(漏极电极6)上形成Ag纳米粒子涂膜9A。此前的步骤与所述实施形态1中所说明的步骤相同。
接着，如图28所示，将引线框LF载置于包含加热机构(未图示)的芯片焊接平台48上，且以250～350℃的温度进行加热。然后，利用焊接夹头49来吸附、保持主面朝上的硅芯片3A并将其载置于芯片垫部4D上之后，利用焊接夹头49将硅芯片3A按压到芯片垫部4D上。
这样，通过将硅芯片3A热压接到芯片垫部4D上，使得表面或者内部形成有许多微细孔的多孔的Ag纳米粒子涂膜9A、9B互相侵入到彼此的内部，从而在两者的界面上产生机械锚定效果，因此硅芯片3A与芯片垫部4D经由Ag纳米粒子涂膜9A、9B而牢固地着。而且，Ag纳米粒子涂膜9A与漏极电极6的界面、以及Ag纳米粒子涂膜9B与芯片垫部4D的界面上分别形成有金属键，所以这些界面的接着强度会增强，同时电阻会降低。
其次，通过利用有热与超声波的球形焊接法，将Au线11焊接到硅芯片3A的源极垫7与源极引线Ls之间、以及栅极垫8与栅极引线Lg之间。代替Al带10而利用Au线11来连接源极垫7与源极引线Ls的理由是，为了减小对硅芯片3A的背面(漏极电极6)与芯片垫部4D的接合面所造成的损伤。即，Al带10焊接时施加到源极垫7表面的超声波振动能量，远大于Au线11焊接时施加到源极垫7表面的超声波振动能量。而且，在未使用Ag膏5的本实施形态中，硅芯片3A的背面(漏极电极6)与芯片垫部4D是经由薄的Ag纳米粒子涂膜9A、9B而密着。之所以如此，其原因在于，如果利用Al带10来连接源极垫7与源极引线Ls，则Ag纳米粒子涂膜9A、9B的接合面上会受到较大的损伤，从而导致两者的密着力降低。
随后，使用模铸模具，利用模铸树脂2将硅芯片3A(及芯片垫部4D、Au线11、引线L的内部引线部)加以密封。在此模铸步骤中，构成模铸树脂2的环氧树脂在其一部分进入到形成于引线L表面上的Ag纳米粒子涂膜9B的微细孔内的状态下固化。因此，在Ag纳米粒子涂膜9B与模铸树脂2的界面上机械锚定效果会发挥作用，从而引线L与模铸树脂2经由Ag纳米粒子涂膜9B而牢固地密着。
然后，在将露出到模铸树脂2外部的引线L的无用部分切断、除去之后，使引线L成形为鸥翼状，最后，经过判别产品良否的分选步骤而完成半导体装置1B。
这样，根据本实施形态的制造方法，由于无需将Ag膏5供给于芯片垫部4D上的步骤，所以可简化制造步骤。
而且，本实施形态是在引线框LF(芯片垫部4D和引线L)的表面上形成Ag纳米粒子涂膜9B，且在硅芯片3A的背面的漏极电极6上形成Ag纳米粒子涂膜9A，但为了进一步简化制造步骤，也可以省略在漏极电极6的表面上形成Ag纳米粒子涂膜9A的步骤、或者在引线框LF的表面上形成Ag纳米粒子涂膜9B的步骤的任一方。
(实施形态3)
图29是本实施形态的半导体装置的剖面图。本实施形态的半导体装置1C是将背面不具有漏极电极的硅芯片3C搭载在芯片垫部4D上的装置，其特征在于，并未使用焊锡材料或Ag膏5，而是将硅芯片3C与芯片垫部4D直接接合。另外，与所述实施形态1的半导体装置1A的不同点在于，硅芯片3C的尺寸大于所述实施形态1的硅芯片3A的尺寸。即，所述实施形态1中硅芯片3A的长边的尺寸小于4mm，而本实施形态中硅芯片3B的长边的尺寸大于4mm。因此，芯片尺寸增大，从而与所述实施形态1的半导体装置1A相比，功率MOSFET的容量会相应地增大。
以前，对于使用有背面不具有漏极电极的硅芯片的功率半导体装置而言，是通过在镀Au的引线框的芯片垫部上形成Au-Si共晶合金层而将硅芯片搭载在芯片垫部上。然而，Au-Si共晶合金的共晶点为363℃，在考虑到量产性的情况下，需要410℃～470℃左右的焊接温度，因此对功率元件所造成的热损伤较大。而且，Au-Si共晶合金层也被称作硬焊料(hard solder)，其硬度非常高，因此在考虑到硅芯片与芯片垫部的热膨胀系数差的情况下，难以将其应用于尺寸大的硅芯片的焊接中。
因此，本实施形态中，与所述实施形态2同样是使用Ag纳米粒子涂膜9A、9B来将硅芯片3C搭载在芯片垫部4D上。具体而言，利用所述方法在硅芯片3C的背面上形成Ag纳米粒子涂膜9A，也在引线框LF的整个面上以所述方法而形成Ag纳米粒子涂膜9B。并且，如所述图28所示，将引线框LF载置于芯片焊接平台48上，并以250～350℃的温度进行加热后，利用焊接夹头49来吸附、保持主面朝上的硅芯片3C以将其载置于芯片垫部4D上，且利用焊接夹头49将硅芯片3C向下方按压。此时的负载例如为50g～80g，时间为5msec～20msec。而且，在对引线框LF进行加热时，为了防止其表面氧化，较理想的是例如在氮等惰性气体环境中进行加热。
这样，根据本实施形态的制造方法，能够以相比Au-Si共晶合金层的共晶点(363℃)较低的温度来对硅芯片3C进行芯片焊接，因此可减轻对形成在硅芯片3C上的功率MOSFET所造成的热损伤。并且，由于Ag纳米粒子涂膜9A、9B相比Au-Si共晶合金层而言为低弹性，所以即便在应用于尺寸较大的硅芯片3C的芯片焊接时，也可以确保硅芯片3C与芯片垫部4D的接合可靠性。
另外，本实施形态中，为了进一步简化制造步骤，也可省略在硅芯片3C的背面上形成Ag纳米粒子涂膜9A的步骤、或者在引线框LF的表面上形成Ag纳米粒子涂膜9B的步骤的任一方。
(实施形态4)
图30～图32是表示本实施形态的半导体装置的示图，图30是表示表面侧的外观的俯视图，图31是表示背面侧的外观的俯视图，图32是表示内部构造的俯视图。
本实施形态的半导体装置1D是应用于作为小型表面安装封装的一种的HWSON8的装置。在由环氧系树脂所构成的模铸树脂2的底面上，露出有构成HWSON8的外部连接端子的八条引线L的外部引线部。在图30所示的引线L中，从第一条引线到第三条引线是源极引线Ls，第四条引线是栅极引线Lg，从第五条引线到第八条引线是漏极引线Ld。
在模铸树脂2的内部，密封有与所述实施形态1相同的形成有功率MOSFET的硅芯片3A。硅芯片3A以其主面朝上的状态搭载在与四条漏极引线Ld(第五条引线～第八条引线)一体形成的芯片垫部4D上。芯片垫部4D的背面是与八条引线L的外部引线部同样地从模铸树脂2的底面露出。芯片垫部4D和八条引线L(第一条引线～第八条引线)是由铜或Fe-Ni合金所构成，在它们的表面上形成有将Ni膜与Au膜积层所成的两层构造的镀敷层(未图示)。
与所述实施形态1相同，在硅芯片3A的主面上，形成有源极垫(源极电极)7与栅极垫8。并且，三条源极引线Ls(第一条引线～第三条引线)在模铸树脂2的内部连结，此连结的部分与源极垫7是通过Al带10而电性连接。而且，一条栅极引线Lg(第四条引线)与栅极垫8是通过一条Au线11而电性连接。
硅芯片3A的漏极电极6与芯片垫部4D是通过介在于它们之间的Ag膏14而彼此接合。关于此Ag膏14的构成，将于以下说明。
然而，像所述硅芯片3A那样，当通过Al带10将源极引线Ls与源极垫7连接时，Al带10焊接时会对源极垫7的表面施加有较大的超声波振动能量。此超声波振动能量远大于Au线11焊接时所施加的超声波振动能量(5W～10W左右)，因此会对介在于漏极电极6和芯片垫部4D之间的Ag膏造成损伤。其结果导致硅芯片3A与芯片垫部4D的接合强度降低，且根据情况，有时Ag膏上会产生龟裂而致使硅芯片3A从芯片垫部4D上剥离。
因此，本发明者在对Ag膏的物性进行了研究后结果发现，为了实现一种能够经受住Al带焊接时所施加的较大的超声波振动能量的Ag膏，重要的因素是，使Ag膏中所含的树脂的弹性模数(elastic modulus)降低，且使导电性树脂的剪切强度(shear strength)最佳化。
一般而言，硅芯片的芯片焊接中所使用的Ag膏是由将Ag填料混入到热固性环氧树脂中而成的导电性树脂所构成。因此，可将Ag膏中所使用的热固性树脂替换为热固性树脂与低弹性模数的热塑性树脂的混合树脂，从而可实现一种即便在Al带焊接时所施加的超声波振动能量的作用下也难以劣化的Ag膏。
然而，由于热塑性树脂相比热固性树脂而言耐热性较低，所以当对包含热塑性树脂的Ag膏施加高热时，树脂的块体强度(bulk strength)会降低，其结果导致Ag膏上产生龟裂，从而引起导电率及可靠性降低。特别是像本实施形态的半导体装置1D(HWSON8)，对于面积较大的芯片垫部4D从模铸树脂2的底面露出的封装而言，在将封装安装于配线基板上时的回流焊步骤中，对芯片垫部4D施加260℃左右的高热，因此当使用包含热塑性树脂的Ag膏时，树脂的块体强度容易降低。
本实施形态中所使用的Ag膏14是为了解决所述问题而开发，其特征在于，在向将Ag填料混入到作为基础树脂的热固性树脂(例如热固性环氧树脂)中所成的通常的Ag膏中，添加具有8μm～20μm、更优选8μm～10μm的粒径的由第二热固性树脂所构成的衬垫(spacer)树脂。如果衬垫树脂的粒径小于8μm，则难以确保能够经受住Al带焊接时的超声波振动能量的Ag膏厚度。另一方面，如果衬垫树脂的粒径大于20μm，则Ag膏的膜厚会变得过大，从而Ag膏中产生空隙(void)而致使接着强度降低。另外，衬垫树脂的弹性模数较理想的是4GPa以下。
图33是添加有衬垫树脂的Ag膏14的制造流程图。为了制造Ag膏14，首先，将通常的Ag膏中所使用的Ag填料和热固性树脂(例如热固性环氧树脂)添加到溶剂中并调节粘度，然后利用辊进行混炼。接着，对此混炼物进行真空脱泡处理以将内部的气泡去除后，添加例如具有10μm左右的粒径的由第二热固性树脂(例如热固性环氧树脂)所构成的衬垫树脂，并进一步进行混炼。在对衬垫树脂进行混炼时，为了防止其挤破或者毁坏，应避免使用辊来混炼，而要使用例如混合机来进行混炼。由此，完成了添加有具有10μm左右的粒径的衬垫树脂的Ag膏14。
图34是使用有此Ag膏14的半导体装置1D(HWSON8)的制造流程图。将Ag膏14供给于芯片垫部4D上的方法与所述图15、图16所示的方法相同，且与通常的供给Ag膏的方法相比并无变化。而且，对于其它的制造步骤而言，也可直接使用以前的制造步骤。
利用图35来说明添加有所述衬垫树脂的Ag膏14的效果。如图的比较例所示，在使将Ag填料填充到包含作为基础树脂的树脂与溶剂的液状树脂中所成的Ag膏固化时，由于液状树脂收缩的同时溶剂挥发，所以Ag膏的膜厚相比固化前变薄。在Ag膏的膜厚变薄时，由Al带焊接时的超声波振动能量而引起的Ag膏的变形量增大，最大应力变大。此处，最大应力是指施加到硅芯片3A、芯片垫部4D和介在于它们之间的Ag膏14的各部上的应力中的最大的应力，通常，施加到硅芯片3A的端部与Ag膏14的接合部上的应力成为最大。
与此相对，对于添加有以所述方式构成的衬垫树脂15的本发明的Ag膏14而言，在使包含作为基础树脂的树脂与溶剂的液状树脂固化时，即便基础树脂有所收缩，预先被固化的衬垫树脂15也不会收缩，因此Ag膏14的膜厚不会变薄成为衬垫树脂15的粒径以下。由此，Al带焊接时施加到Ag膏14上的最大应力减小，从而对于Al带焊接时所施加的超声波振动的耐受性有所提高。而且，由于本实施形态的Ag膏14不含热塑性树脂，所以具有如下特征：即便在回流焊步骤中对芯片垫部4D施加高热(约260℃)，树脂的块体强度也难以降低。
图36是表示Ag膏的厚度与Ag膏断裂超声波输出间的关系的图表。图中的□(方形)标记表示Ag膏的厚度为5μm、10μm、20μm时的Ag膏断裂超声波输出。此处，所谓Ag膏断裂超声波输出，是指金属带焊接时Ag膏断裂的超声波输出。而且，所谓金属带焊接稳定区域，是表示并未因金属带焊接时施加到Ag膏上的超声波振动能量(5W～10W左右)而导致Ag膏断裂的区域。
根据此图表可判断，Ag膏厚度为5μm时的Ag膏断裂超声波输出位于金属带焊接稳定区域之外，故无法不让Ag膏断裂来实施金属带焊接。另一方面可判断，Ag膏厚度为10μm、15μm时的Ag膏断裂超声波输出位于金属带焊接稳定区域之内，故可不让Ag膏断裂而进行金属带焊接。根据此结果，通过向Ag膏中添加衬垫树脂15，可确保Ag膏断裂超声波输出位于金属带焊接稳定区域之内的Ag膏厚度。
图37是表示Ag膏厚度与金属带焊接时施加到Ag膏上的最大应力间的关系的图表。图中的数值(5μm、10μm、20μm)分别表示Ag膏的厚度。而且，此处的芯片尺寸是指与施加到Ag膏上的应力方向平行的方向上的芯片边长。根据此图表而判断，与芯片尺寸无关，在Ag膏厚度为10～20μm时可减小最大应力。
以上，根据实施形态对由本发明者所完成的发明进行了具体的说明，但本发明并不限定于所述实施形态，毫无疑问，在不脱离其主旨的范围内可进行各种变更。
在所述实施形态中，对应用于SOP8及HWSON8的半导体装置进行了说明，而其也可应用于各种功率半导体用封装中。另外，形成在硅芯片上的功率元件并不限定于功率MOSFET，例如也可以是绝缘栅双极晶体管(Insulated Gate Bipolar Transistor：IGBT)等。
本发明中，作为衬垫树脂，可使用环氧树脂、丙烯酸树脂、聚酰亚胺树脂及聚酯树脂等。而且，这些树脂的弹性模数较理想的是0.5～4GPa。
[产业上的可利用性]
本发明可利用于便携式信息设备的电力控制开关或者充放电保护电路开关等中所使用的功率半导体装置。

Claims (26)

1.一种半导体装置，其特征在于：
包含：
引线框，其具有芯片垫部和配置在所述芯片垫部附近的第一引线；
半导体芯片，其以面朝上方式搭载在所述芯片垫部上，且在主面上具有第一垫；
导电体，其将所述第一引线与所述第一垫电性连接；及
树脂封装，其将所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以密封；且
在所述引线框的表面上，形成有将Ag的纳米粒子烧结所成的第一多孔质金属层；
所述芯片垫部与所述半导体芯片的背面经由Ag膏而黏接在一起。
2.根据权利要求1所述的半导体装置，其特征在于：
构成所述第一多孔质金属层的所述纳米粒子的平均粒径为1nm～50nm。
3.根据权利要求1所述的半导体装置，其特征在于：
将所述第一引线与所述第一垫电性连接的所述导电体是金属带。
4.根据权利要求3所述的半导体装置，其特征在于：
在所述半导体芯片上形成有功率MOSFET，所述第一垫构成所述功率MOSFET的源极电极。
5.根据权利要求4所述的半导体装置，其特征在于：
在所述半导体芯片的背面上，形成有所述功率MOSFET的漏极电极。
6.根据权利要求1所述的半导体装置，其特征在于：
在所述半导体芯片的背面上，形成有将Ag的纳米粒子烧结所成的第二多孔质金属层。
7.根据权利要求6所述的半导体装置，其特征在于：
构成所述第二多孔质金属层的所述纳米粒子的平均粒径为1nm～50nm。
8.一种半导体装置，其特征在于：
包含：
引线框，其具有芯片垫部和配置在所述芯片垫部附近的第一引线；
半导体芯片，其以面朝上方式搭载在所述芯片垫部上，且在主面上具有第一垫；
导电体，其将所述第一引线与所述第一垫电性连接；及
树脂封装，其将所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以密封；且
在所述引线框的表面和所述半导体芯片的背面的至少其中一者上，形成有将Ag的纳米粒子烧结所成的多孔质金属层；
所述芯片垫部与所述半导体芯片的背面经由所述多孔质金属层而黏接在一起。
9.根据权利要求8所述的半导体装置，其特征在于：
构成所述多孔质金属层的所述纳米粒子的平均粒径为1nm～50nm。
10.根据权利要求8所述的半导体装置，其特征在于：
将所述第一引线与所述第一垫电性连接的所述导电体是金属线或金属带。
11.根据权利要求8所述的半导体装置，其特征在于：
在所述半导体芯片上形成有功率MOSFET，所述第一垫构成所述功率MOSFET的源极电极。
12.根据权利要求11所述的半导体装置，其特征在于：
在所述半导体芯片的背面上，形成有所述功率MOSFET的漏极电极。
13.一种半导体装置，其特征在于：
包含：
引线框，其具有芯片垫部和配置在所述芯片垫部附近的第一引线；
半导体芯片，其以面朝上方式搭载在所述芯片垫部上，且在主面上具有第一垫；
导电体，其将所述第一引线与所述第一垫电性连接；及
树脂封装，其将所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以密封；且
所述芯片垫部与所述半导体芯片的背面经由Ag膏而黏接在一起，所述Ag膏含有Ag填料、作为基础树脂的第一热固性树脂、和具有8μm～20μm的粒径的由第二热固性树脂所构成的衬垫树脂。
14.根据权利要求13所述的半导体装置，其特征在于：
将所述第一引线与所述第一垫电性连接的所述导电体是金属带。
15.根据权利要求14所述的半导体装置，其特征在于：
在所述半导体芯片上形成有功率MOSFET，所述第一垫构成所述功率MOSFET的源极电极，在所述半导体芯片的背面上，形成有所述功率MOSFET的漏极电极。
16.一种半导体装置的制造方法，其包含以下步骤：
(a)准备具有芯片垫部和配置在所述芯片垫部附近的第一引线的引线框，并在所述引线框的表面上，形成将Ag的纳米粒子烧结所成的第一多孔质金属层；
(b)准备在主面上具有第一垫的半导体芯片；
(c)在将Ag膏供给到所述芯片垫部上之后，以面朝上方式将所述半导体芯片搭载在所述芯片垫部上；
(d)在所述(c)步骤之后，使所述Ag膏固化，以此将所述芯片垫部与所述半导体芯片的背面经由所述Ag膏而黏接在一起；
(e)在所述(d)步骤之后，通过导电体将所述第一引线与所述第一垫电性连接；及
(f)在所述(e)步骤之后，对所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以树脂密封。
17.根据权利要求16所述的半导体装置的制造方法，其特征在于：
构成所述第一多孔质金属层的所述纳米粒子的平均粒径为1nm～50nm。
18.根据权利要求16所述的半导体装置的制造方法，其特征在于：
将所述第一引线与所述第一垫电性连接的所述导电体是金属带，所述金属带是通过施加有超声波振动的楔焊法而连接到所述第一引线和所述第一垫。
19.根据权利要求16所述的半导体装置的制造方法，其特征在于：
在所述半导体芯片上形成有功率MOSFET，所述第一垫构成所述功率MOSFET的源极电极。
20.根据权利要求19所述的半导体装置的制造方法，其特征在于：
在所述半导体芯片的背面上，形成有所述功率MOSFET的漏极电极。
21.根据权利要求16所述的半导体装置的制造方法，其特征在于：
所述(b)步骤包含下述步骤：
(b1)在半导体晶片的主面上形成半导体元件和连接于所述半导体元件的所述第一垫；
(b2)在所述(b1)步骤之后，在所述半导体晶片的背面上，形成将Ag的纳米粒子烧结所成的第二多孔质金属层；及
(b3)在所述(b2)步骤之后，对所述半导体晶片进行切割，由此获得在背面上形成有所述第二多孔质金属层的所述半导体芯片。
22.根据权利要求21所述的半导体装置的制造方法，其特征在于：
构成所述第二多孔质金属层的所述纳米粒子的平均粒径为1nm～50nm。
23.一种半导体装置的制造方法，其包含以下步骤：
(a)在半导体晶片的主面上形成半导体元件和连接于所述半导体元件的第一垫；
(b)在所述(a)步骤之后，对所述半导体晶片进行切割，由此获得半导体芯片；
(c)准备具有芯片垫部和配置在所述芯片垫部附近的第一引线的引线框；
(d)在所述(a)步骤之后且所述(b)步骤之前，在所述半导体晶片的背面上，形成将Ag的纳米粒子烧结所成的多孔质金属层，及/或在所述引线框的表面上，形成将Ag的纳米粒子烧结所成的多孔质金属层；
(e)在所述(d)步骤之后，将所述半导体芯片以面朝上方式搭载在已加热到既定温度的所述芯片垫部上，并且将所述半导体芯片压接到所述芯片垫部，以此将所述芯片垫部与所述半导体芯片的背面经由所述多孔质金属层黏接在一起；
(f)所述(e)步骤之后，通过导电体将所述第一引线与所述第一垫电性连接；及
(g)在所述(f)步骤之后，对所述芯片垫部、所述半导体芯片、所述导电体和所述第一引线的内部引线部加以树脂密封。
24.根据权利要求23所述的半导体装置的制造方法，其特征在于：
构成所述多孔质金属层的所述纳米粒子的平均粒径为1nm～50nm。
25.根据权利要求23所述的半导体装置的制造方法，其特征在于：
在所述(f)步骤中，将所述第一引线与所述第一垫电性连接的所述导电体是金属线或金属带。
26.根据权利要求23所述的半导体装置的制造方法，其特征在于：
在所述(e)步骤中，对所述芯片垫部进行加热的温度是比Au-Si共晶合金的共晶点低的温度。
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JP2009206482A (ja) 2009-09-10
US8252632B2 (en) 2012-08-28
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