CN112786546A - 半导体封装和用于制造半导体封装的方法 - Google Patents

半导体封装和用于制造半导体封装的方法 Download PDF

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CN112786546A
CN112786546A CN202011167240.2A CN202011167240A CN112786546A CN 112786546 A CN112786546 A CN 112786546A CN 202011167240 A CN202011167240 A CN 202011167240A CN 112786546 A CN112786546 A CN 112786546A
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semiconductor chip
power semiconductor
less
metal layer
semiconductor package
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R·奥特伦巴
P·弗兰克
A·海因里希
A·卢德施特克-佩希洛夫
D·佩多内
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

一种半导体封装，包括：包括SiC的功率半导体芯片；包括Cu的引线框部分，其中，功率半导体芯片布置在引线框部分上；以及将功率半导体芯片电和机械地耦合到引线框部分的焊接接合部，其中，焊接接合部包括至少一种金属间相。

Description

半导体封装和用于制造半导体封装的方法
技术领域
本公开内容总体上涉及一种半导体封装及制造半导体封装的方法。
背景技术
半导体封装，特别是包括被配置为处理高电压和/或高电流的半导体芯片(功率半导体芯片)的半导体封装，可能在操作期间产生大量的热。因此，适当地冷却这种半导体封装可能是具有挑战性的。冷却例如可以通过包括功率半导体芯片所附着到的管芯载体的热通路来完成。冷却的效率可以取决于沿着该热通路的热阻。此外，将功率半导体芯片附着到管芯载体可以通过焊接完成，然而这可能导致焊料渗出。焊料渗出可能占据管芯载体表面上的空间和/或甚至可能造成短路故障。改进的半导体封装和用于制造半导体封装的改进方法可以帮助解决这些和其它问题。
本公开内容所基于的问题通过独立权利要求的特征来解决。在从属权利要求中描述了另外的有利示例。
发明内容
各个方面涉及一种半导体封装，包括：包括SiC的功率半导体芯片；包括Cu的引线框部分，其中，功率半导体芯片布置在引线框部分上；以及将功率半导体芯片电和机械地耦合到引线框部分的焊接接合部，其中，焊接接合部包括至少一种金属间相。
各个方面涉及一种用于制造半导体封装的方法，所述方法包括：提供包括多个功率晶体管电路的SiC半导体晶圆；在SiC半导体晶圆上沉积第一金属层；将SiC半导体晶圆切单(singulate)成单独的功率半导体芯片，每个功率半导体芯片包括至少一个功率晶体管电路；提供包括Cu的引线框部分；将功率半导体芯片中的至少一个布置在引线框部分上，使得第一金属层面向引线框部分；以及将至少一个功率半导体芯片扩散焊接到引线框部分，使得第一金属层和引线框部分形成至少一种金属间相。
附图说明
附图示出了示例，并且与说明书一起用于解释本公开内容的原理。将容易理解本公开内容的其它示例和许多预期优点，因为通过参考以下具体实施方式它们变得更好理解。附图中的元件不一定相对于彼此成比例。相同的附图标记表示相应的类似部件。
图1是包括SiC芯片和扩散焊接接合部的半导体封装的示意性截面图。
图2A至图2F是根据用于制造半导体封装的方法的处于各个制造阶段的半导体封装的示意性截面图。
图3是被向下按压到引线框部分上的功率半导体芯片的截面图。
图4是包括功率半导体芯片和多个金属层的叠层的截面图。
图5是示出用于制造半导体封装的方法的流程图。
图6是表面安装器件形式的半导体封装的透视图。
具体实施方式
在以下具体实施方式中，参考附图，其中通过说明示出了可以实践本公开内容的具体示例。在这方面，参考所描述的(一个或多个)附图的取向使用诸如“顶部”、“底部”、“前面”、“后面”、“上部”、“下部”等的方向术语。因为示例的部件可以以多个不同的取向定位，所以方向术语用于说明的目的而绝不是限制。
如本说明书中所采用的，术语“接合”、“附着”、“连接”、“耦合”和/或“电连接/电耦合”不意味着表示元件或层必须直接接触在一起；可以分别在“接合”、“附着”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间提供中间元件或层。然而，根据本公开内容，上述术语可以可选地还具有元件或层直接接触在一起的特定含义，即，分别在“接合”、“附着”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间不提供中间元件或层。
本文提及的功率半导体芯片可以具有垂直结构，也就是说，半导体芯片可以以电流可以在垂直于半导体芯片的主表面的方向上流动的方式制造。一种具有垂直结构的半导体芯片在其两个主表面上具有电极。垂直功率半导体芯片可以例如被配置为功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)、JFET(结型场效应晶体管)、功率双极晶体管或功率二极管。作为示例，功率MOSFET的源极触点电极和栅极触点电极可以位于一个主表面上，而功率MOSFET的漏极触点电极可以布置在另一个主表面上。
可以用包封材料覆盖(一个或多个)功率半导体芯片。包封材料可以是电绝缘的。包封材料可以包括任何适当的塑料或聚合物材料，或者由任何适当的塑料或聚合物材料制成，例如硬塑料、热塑性或热固性材料或层合材料(预浸料)，并且可以例如包含填充材料。可以采用各种技术来用包封材料包封半导体芯片，例如压缩成型、注射成型、粉末成型、液体成型或层合。可以使用热和/或压力来施加包封材料。
图1示出了包括功率半导体芯片110、引线框部分120和焊接接合部(solderjoint)130的半导体封装100。
功率半导体芯片110是SiC芯片，这意味着功率半导体芯片110所包括的半导体材料是SiC。功率半导体芯片110可以具有面向引线框部分120的第一主侧111和相对的第二主侧112。功率半导体芯片110还可以包括连接第一主侧111和第二主侧112的侧面113。
根据示例，功率半导体芯片110可以包括垂直晶体管结构，其中第一(功率)电极被布置在第一主侧111上，并且第二(功率)电极被布置在第二主侧112上。例如，第一(功率)电极可以是漏电极，第二(功率)电极可以是源电极。相反的情况也是可能的。此外，可以在例如第二主侧112上布置像栅电极的控制电极。
功率半导体芯片110可以是薄的。功率半导体芯片110可以例如具有在第一主侧111和第二主侧112之间测量的350μm或更小、或者250μm或更小、或者150μm或更小、或者100μm或更小、或者50μm或更小的厚度。功率半导体芯片110的外延层到引线框部分的距离可以为300μm或更小、或者200μm或更小、或者150μm或更小、或者100μm或更小、或者50μm或更小。主侧111、112可以例如各自具有在1mm2至25mm2范围内的表面积。主侧111、112可以基本上具有矩形或正方形形状。
引线框部分120可以包括Cu。引线框部分120也可以完全由Cu构成。根据另一示例，引线框部分120可以包括Ag、Au或Ni或由Ag、Au或Ni构成。
引线框部分120可以例如具有0.2mm或更大、或者0.5mm或更大、或者1.0mm或更大、或者1.5mm或更大的厚度(垂直于主侧111、112测量)。引线框部分120的厚度与功率半导体芯片110的厚度的比率可以是大约5、大约10、大约15或大约20。
引线框部分120可以是管芯载体。在引线框部分120上可以单独布置功率半导体芯片110或者根据另一示例布置多于一个(功率)半导体芯片。制造半导体封装100可以包括冲压或切割引线框以便获得引线框部分120。
根据示例，半导体封装100可以包括一个或多个附加的引线框部分。一个或多个附加的引线框部分可以与引线框部分120电绝缘。一个或多个附加的引线框部分可以电耦合到功率半导体芯片110。一个或多个附加的引线框部分可以例如包括半导体封装100的外部引线。
焊接接合部130将功率半导体芯片110电和机械地耦合到引线框部分120。焊接接合部130包括至少一种金属间相或金属间化合物。焊接接合部130可以是扩散焊接接合部(即，通过扩散焊接工艺形成的焊接接合部)。焊接接合部130例如可以包括金属间化合物或由金属间化合物构成，所述金属间化合物例如为AgSnCu或AuSnCu或CuSn或NiSnCu或AgInCu或AuInCu或CuIn或NiInCu。
焊接接合部130可以具有20μm或更小、或者10μm或更小、或者5μm或更小的厚度(垂直于主侧111、112测量)。根据一个示例，焊接接合部130可以具有在2μm至4μm范围内的厚度。薄的焊接接合部130可以具有比厚的焊接接合部更小的热阻。因此，由功率半导体芯片110产生的热量可以更容易地经由焊接接合部130和引线框部分120耗散。此外，薄的焊接接合部130可以较不易于焊料渗出。
根据示例，功率半导体芯片110的厚度与焊接接合部130的厚度的比率可以是10或更大、20或更大、50或更大、或者100或更大。
焊接接合部130可以完全覆盖第一主侧111。根据示例，焊接接合部130可以与所有侧面113齐平。特别地，半导体封装100可以没有任何焊料渗出。根据另一示例，在侧面113中的至少一个上可以存在一些焊料渗出。
图2A-2F示出了根据制造半导体封装的方法的处于各个制造阶段的半导体封装100。
如图2A所示，提供包括多个功率晶体管电路210的半导体晶圆200。半导体晶圆200包括SiC或由SiC构成。功率晶体管电路210可各自包括垂直晶体管结构，并且可例如各自包括源电极、漏电极和栅电极。漏电极可以例如布置在半导体晶圆200的第一主侧201上，并且源电极和栅电极可以例如布置在半导体晶圆200的相对的第二主侧202上。
如图2B所示，将第一金属层220沉积在半导体晶圆200上。第一金属层220可以沉积在第一主侧201上。第一金属层220可以完全覆盖第一主侧201。第一金属层220可以包括适合于扩散焊接的焊料材料，例如AgSn、AuSn、CuSn、NiSn、AgIn、CuIn或NiIn。第一金属层220可以使用任何合适的沉积技术沉积在半导体晶圆200上，例如分配(dispensing)、(化学)气相沉积、溅射等。
如图2C所示，将半导体晶圆200切单成单独的功率半导体芯片110，其中每个功率半导体芯片110包括至少一个功率晶体管电路210。经切单的功率晶体管芯片110的第一主侧111可以(完全)被第一金属层220覆盖。切单可以包括例如机械地或使用激光沿着切割线切割半导体晶圆200。此外，第一金属层220可以与半导体晶圆200同时切割。经切单的功率半导体芯片110的侧面113可以包括第一金属层220的材料的一些污染。类似地，第一金属层220可以在侧面113处包括半导体晶圆200的材料的一些污染。
如图2D所示，提供引线框部分120。引线框部分120可以包括Cu或由Cu构成。提供引线框部分120可以可选地包括从引线框带切割出或冲压出引线框部分。
如图2E所示，将功率半导体芯片110中的至少一个布置在引线框部分120上，使得第一金属层220面向引线框部分120。将功率半导体芯片110布置在引线框部分120上可以例如包括使用拾取和放置过程。
如图2F所示，将至少一个功率半导体芯片110扩散焊接到引线框部分120，从而形成焊接接合部130。焊接接合部130可以由第一金属层220的材料和引线框部分120的材料构成，它们一起形成至少一种金属间相。
关于图2A-2F描述的至少一些或所有过程可以在受控气氛中执行。例如，可以使用包括88％的N2和12％的H2的气氛。受控气氛可以例如有助于防止Cu的氧化。
根据示例，将至少一个功率半导体芯片110扩散焊接到引线框部分120还可以包括施加380℃或更高的热。例如，可以将如图2E所示的功率半导体芯片110、第一金属层220和引线框部分120放置在炉中并且加热到380℃或更高。要使用的确切温度可以例如取决于第一金属层220和引线框部分120的材料组合和/或取决于扩散焊接工艺的期望时间长度。
图3示出了被配置为将功率半导体芯片110和第一金属层220按压到引线框部分120上的压机300。例如关于图2A-2F描述的将功率半导体芯片110扩散焊接到引线框部分120可以可选地包括将至少一个功率半导体芯片110按压到引线框部分120上。这可以例如使用压机300来完成。
压机300可以例如被配置为施加1N/mm2或更大、2N/mm2或更大、3N/mm2或更大、或者4N/mm2或更大的压力。由于功率半导体芯片110是SiC芯片，所以它可以比例如Si芯片承受高得多的压力而不被损坏。
将功率半导体芯片110和第一金属层220按压到引线框部分120上可以例如在如上所述施加热的同时进行。一前一后的热和压力可以促进至少一种金属间相的形成。较高的压力可以减少扩散焊接工艺所需的时间长度。
根据示例，压机300可以是被配置为将功率半导体芯片110放置到引线框部分120上的拾取和放置装置的一部分。换句话说，将功率半导体芯片110放置到引线框部分120上和将功率半导体芯片110向下按压到引线框部分120上可以通过压机300执行。
根据另一示例，通过不同于压机300的装置将功率半导体芯片110拾取并放置到引线框部分120上，并且压机300仅在已经将功率半导体芯片110放置到引线框部分120上之后使用。
图4示出了包括功率半导体芯片110、第一金属层220和至少一个附加金属层的叠层400。可以将一个或多个附加金属层布置在功率半导体芯片110与第一金属层220之间。可以将叠层400包括在半导体封装100中。
一个或多个附加金属层可以具有各种功能，并且可以例如被配置为扩散阻挡层、种子层、粘附层等。一个或多个附加金属层可以包括任何合适的金属或金属合金。
根据示例，叠层400可以包括可以直接邻接功率半导体芯片110的第一附加金属层402。第一附加金属层402可以例如包括TiSi或由TiSi构成。
根据示例，叠层400可以包括第二附加金属层404。第二附加金属层404可以直接邻接第一附加金属层402。第二附加金属层404可以例如包括NiV或由NiV构成。
根据示例，叠层400可以包括第三附加金属层406。第三附加金属层406可以直接邻接第二附加金属层404。第三附加金属层406可以例如包括Al或由Al构成。
根据示例，叠层400可以包括第四附加金属层408。第四附加金属层408可以直接邻接第三附加金属层406。第四附加金属层408可以例如包括Ti或由Ti构成。第一金属层220可以直接邻接第四附加金属层408。
根据另一示例，叠层400可以仅包括附加金属层402到408中的一个、两个或三个。例如，叠层400可以包括第一附加金属层402、第二附加金属层404和第四附加金属层408，但不包括第三金属层406。在这种情况下，第四附加金属层408可以直接邻接第二附加金属层404。
此外，单独的附加金属层402至408不一定需要包括上述示例性金属，而是可以包括一种或多种其它合适的金属。单独的附加金属层402至408可以具有任何合适的厚度，例如，每层可以具有100nm至300nm范围内的厚度。
图5是用于制造半导体封装的方法500的流程图。方法500可以例如用于制造半导体封装100。
方法500包括：在501处提供包括多个功率晶体管电路的SiC半导体晶圆；在502处在SiC半导体晶圆上沉积第一金属层；在503处将SiC半导体晶圆切单成单独的功率半导体芯片，每个功率半导体芯片包括至少一个功率晶体管电路；在504处提供包括Cu的引线框部分；在505处将至少一个功率半导体芯片布置在引线框部分上，使得第一金属层面向引线框部分；以及在506处将至少一个功率半导体芯片扩散焊接到引线框部分，使得第一金属层和引线框部分形成至少一种金属间相。
根据方法500的示例，在SiC半导体晶圆上沉积502第一金属层可以包括使用溅射技术、分配技术、(化学)气相沉积技术或本领域已知的任何其他合适的技术。第一金属层可以例如被沉积为使得其具有1.2μm或更小的厚度。
方法500可以可选地包括在至少一个功率半导体芯片的扩散焊接506期间施加热和/或压力。例如，可以将380℃或更高的热和/或4N/mm2或更大的压力施加到第一金属层上。
图6是半导体封装600的透视图，其可以与半导体封装100类似或相同。
半导体封装600包括关于半导体封装100描述的所有部件，并且其还包括包封体602和外部触点604。包封体602例如可以是模制体或层合体。外部触点604可以例如是引线框的一部分。功率半导体芯片可以电耦合到外部触点604中的一个或多个。
半导体封装600可以可选地包括金属板606。金属板606可以与引线框部分120相同。金属板606可以至少部分地在包封体602处暴露，并且其可以被配置为帮助耗散由功率半导体芯片110生成的热量和/或被配置为从外部电接触功率半导体芯片110的功率电极。
根据一个示例，半导体封装600可以是表面安装器件(SMD)。然而，半导体封装600也可以是通孔器件(THD)。半导体封装600可以是标准化晶体管外形(TO)封装，例如TO 263-7类型的封装。
示例
在下文中，使用特定示例进一步描述半导体封装和用于制造半导体封装的方法。
示例1是一种半导体封装，包括：包括SiC的功率半导体芯片；包括Cu的引线框部分，其中，功率半导体芯片布置在引线框部分上；以及将功率半导体芯片电和机械地耦合到引线框部分的焊接接合部，其中，焊接接合部包括至少一种金属间相。
示例2是示例1的半导体封装，其中，功率半导体芯片被配置为在175℃或更高的温度下或者在200℃或更高的温度下进行操作。
示例3是示例1或2的半导体封装，其中，焊接接合部包括AgSnCu、AuSnCu、CuSn、NiSnCu、AgInCu、AuInCu、CuIn或NiInCu。
示例4是前述示例之一的半导体封装，其中，焊接接合部具有10μm或更小的厚度。
示例5是前述示例之一的半导体封装，其中，功率半导体芯片具有200μm或更小、或者150μm或更小、或者100μm或更小的厚度。
示例6是前述示例之一的半导体封装，其中，功率半导体芯片的栅极氧化物与引线框部分之间的距离是300μm或更小，或者200μm或更小，或者150μm或更小，或者100μm或更小，或者50μm或更小。
示例7是前述示例之一的半导体封装，还包括布置在功率半导体芯片和焊接接合部之间的NiV层，其中，NiV层具有300nm或更小的厚度。
示例8是前述示例之一的半导体封装，其中，功率半导体芯片具有第一主面、相对的第二主面以及连接第一主面和第二主面的侧面，其中，将焊接接合部布置在第一主面上并且完全覆盖第一主面，并且其中，焊接接合部与所有侧面齐平。
示例9是一种用于制造半导体封装的方法，该方法包括：提供包括多个功率晶体管电路的SiC半导体晶圆；在SiC半导体晶圆上沉积第一金属层；将SiC半导体晶圆切单成单独的功率半导体芯片，每个功率半导体芯片包括至少一个功率晶体管电路；提供包括Cu的引线框部分；将功率半导体芯片中的至少一个布置在引线框部分上，使得第一金属层面向引线框部分；以及将至少一个功率半导体芯片扩散焊接到引线框部分，使得第一金属层和引线框部分形成至少一种金属间相。
示例10是示例9的方法，其中，第一金属层包括AgSn、AuSn、CuSn、NiSn、AgIn、AuIn、CuIn或NiIn。
示例11是示例9或10的方法，其中，在SiC半导体晶圆上沉积第一金属层包括将第一金属层溅射到1.2μm或更小的厚度。
示例12是示例9至11中的一个的方法，其中，将至少一个功率半导体芯片扩散焊接到引线框部分还包括施加380℃或更高的热。
示例13是示例9至12中的一个的方法，其中，将至少一个功率半导体芯片扩散焊接到引线框部分还包括：以4N/mm2或更大的压力将至少一个功率半导体芯片按压到引线框部分上。
示例14是示例9至13中的一个的方法，其中，扩散焊接之后的接合层(bond line)厚度为4μm或更小。
示例15是示例9至14中的一个的方法，其中，至少一个功率半导体芯片具有150μm或更小的厚度。
示例16是示例1至8中的一个的半导体封装，其中，引线框部分具有0.5mm或更大的厚度。
示例17是示例1的半导体封装，其中，焊接接合部是扩散焊接接合部。
示例19是包括用于执行根据示例9至15中的一个的方法的模块的装置。
虽然已经关于一个或多个实施方式图示和描述了本公开内容，但是可以在不脱离所附权利要求的精神和范围的情况下对图示的示例进行更改和/或修改。特别地，关于由上述部件或结构(组件、设备、电路、系统等)执行的各种功能，除非另外指出，否则用于描述这些部件的术语(包括对“模块”的引用)旨在对应于执行所述部件的指定功能的任何部件或结构(例如，功能上等同)，即使结构上不等同于执行本公开内容的本文所示的示例性实施方式中的功能的所公开的结构。

Claims (15)

1.一种半导体封装，包括：
功率半导体芯片，其包括SiC，
引线框部分，其包括Cu，其中，所述功率半导体芯片布置在所述引线框部分上，以及
焊接接合部，其将所述功率半导体芯片电和机械地耦合到所述引线框部分，其中，所述焊接接合部包括至少一种金属间相。
2.根据权利要求1所述的半导体封装，其中，所述功率半导体芯片被配置为在175℃或更高的温度下或者在200℃或更高的温度下进行操作。
3.根据权利要求1或2所述的半导体封装，其中，所述焊接接合部包括AgSnCu、AuSnCu、CuSn、NiSnCu、AgInCu、AuInCu、CuIn或NiInCu。
4.根据前述权利要求中的任一项所述的半导体封装，其中，所述焊接接合部具有10μm或更小的厚度。
5.根据前述权利要求中的任一项所述的半导体封装，其中，所述功率半导体芯片具有200μm或更小、或者150μm或更小、或者100μm或更小的厚度。
6.根据前述权利要求中的任一项所述的半导体封装，其中，所述功率半导体芯片的栅极氧化物与所述引线框部分之间的距离是300μm或更小，或者200μm或更小，或者150μm或更小，或者100μm或更小，或者50μm或更小。
7.根据前述权利要求中的任一项所述的半导体封装，还包括：
NiV层，其布置在所述功率半导体芯片和所述焊接接合部之间，其中，所述NiV层具有300nm或更小的厚度。
8.根据前述权利要求中的任一项所述的半导体封装，其中，所述功率半导体芯片具有第一主面、相对的第二主面以及连接所述第一主面和所述第二主面的侧面，
其中，所述焊接接合部布置在所述第一主面上并且完全覆盖所述第一主面，并且
其中，所述焊接接合部与所有侧面齐平。
9.一种用于制造半导体封装的方法，所述方法包括：
提供包括多个功率晶体管电路的SiC半导体晶圆，
在所述SiC半导体晶圆上沉积第一金属层，
将所述SiC半导体晶圆切单成单独的功率半导体芯片，每个功率半导体芯片包括至少一个功率晶体管电路，
提供包括Cu的引线框部分，
将所述功率半导体芯片中的至少一个功率半导体芯片布置在所述引线框部分上，使得所述第一金属层面向所述引线框部分，以及
将所述至少一个功率半导体芯片扩散焊接到所述引线框部分，使得所述第一金属层和所述引线框部分形成至少一种金属间相。
10.根据权利要求9所述的方法，其中，所述第一金属层包括AgSn、AuSn、CuSn、NiSn、AgIn、AuIn、CuIn或NiIn。
11.根据权利要求9或10所述的方法，其中，在所述SiC半导体晶圆上沉积所述第一金属层包括将所述第一金属层溅射到1.2μm或更小的厚度。
12.根据权利要求9至11中的任一项所述的方法，其中，将所述至少一个功率半导体芯片扩散焊接到所述引线框部分还包括：
施加380℃或更高的热。
13.根据权利要求9至12中的任一项所述的方法，其中，将所述至少一个功率半导体芯片扩散焊接到所述引线框部分还包括：
以4N/mm2或更大的压力将所述至少一个功率半导体芯片按压到所述引线框部分上。
14.根据权利要求9至13中的任一项所述的方法，其中，扩散焊接之后的接合层的厚度为4μm或更小。
15.根据权利要求9至14中的任一项所述的方法，其中，所述至少一个功率半导体芯片具有150μm或更小的厚度。
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