CN113206048A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN113206048A
CN113206048A CN202110115889.8A CN202110115889A CN113206048A CN 113206048 A CN113206048 A CN 113206048A CN 202110115889 A CN202110115889 A CN 202110115889A CN 113206048 A CN113206048 A CN 113206048A
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bonding
edge
bonding wires
horizontal direction
active region
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CN113206048B (zh
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F·绍尔兰德
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明公开了一种半导体装置,其包括:包括有源区的可控半导体元件;以及被布置为在第一水平方向上彼此平行的多个键合线。有源区在第一水平方向上具有第一长度,并且在垂直于第一水平方向的第二水平方向上具有第一宽度。多个键合线中的每个通过第一数量的键合连接电耦合和机械耦合到可控半导体元件,其中,第一数量的键合连接中的每个被布置为在垂直于第一水平方向和第二水平方向的垂直方向上处于有源区上方。多个键合线中的每个的第一键合连接被布置为在第一水平方向上与有源区的第一边缘相距第一距离,并且多个键合线中的每个的第二键合连接被布置为在第一水平方向上与有源区的第二边缘相距第二距离,其中,第二边缘被布置为与第一边缘相对。

Description

半导体装置及其制造方法
技术领域
本公开涉及半导体装置及其制造方法。
背景技术
功率半导体模块装置常常包括布置在壳体中的至少一个半导体衬底。包括多个可控半导体元件(例如,半桥构造中的两个IGBT)的半导体装置布置在至少一个衬底中的每个上。每个衬底通常包括衬底层(例如,陶瓷层)、沉积在衬底层的第一侧上的第一金属化层、以及沉积在衬底层的第二侧上的第二金属化层。例如,可控半导体元件安装在第一金属化层上。第二金属化层可以可选地附接到基板。通常采用焊接或烧结技术将可控半导体器件安装到半导体衬底上。此外,可控半导体器件的顶侧可以通过键合线电接触。键合线可以用第二端部电耦合和机械耦合到可控半导体元件的顶侧,并且可以用第一端部电耦合和机械耦合到半导体衬底。当使用半导体装置时,电流流过键合线、衬底的金属化层、和可控半导体元件。可控半导体元件常常被反复地导通和关断。这导致不同部件的加热和随后的冷却。不同的部件常常包括具有不同膨胀系数的不同材料。因此,部件可能暴露于应力或张力,该应力或张力可能对连接的稳定性造成负面影响,并因此对半导体装置的性能和整体寿命造成负面影响。
需要改善了键合线与可控半导体元件之间的连接的可靠性从而增加半导体装置的寿命的半导体装置。
发明内容
半导体装置包括可控半导体元件以及被布置为在第一水平方向上彼此平行的多个键合线,该可控半导体元件包括有源区。有源区在第一水平方向上具有第一长度,并且在垂直于第一水平方向的第二水平方向上具有第一宽度。多个键合线中的每个通过第一数量的键合连接电耦合和机械耦合到可控半导体元件,其中,第一数量的键合连接中的每个被布置为在垂直于第一水平方向和第二水平方向的垂直方向上处于有源区上方。多个键合线中的每个的第一键合连接被布置为在第一水平方向上与有源区的第一边缘相距第一距离,其中,第一距离小于第一长度除以键合连接的第一数量的两倍,并且其中,多个键合线中的每个的第一键合连接是被布置为最靠近第一边缘的键合连接,并且多个键合线中的每个的第二键合连接被布置为在第一水平方向上与有源区的第二边缘相距第二距离,其中,第二边缘被布置为与第一边缘相对,并且其中,第二距离小于第一长度除以键合连接的第一数量的两倍,并且其中,多个键合线中的每个的第二键合连接是被布置为最靠近第二边缘的键合连接。
用于制造半导体装置的方法包括:将多个键合线安装到可控半导体元件上,该可控半导体元件包括有源区。将多个键合线安装到可控半导体元件上包括:对于多个键合线中的每个,在键合线和可控半导体元件之间形成第一数量的键合连接,从而将键合线电耦合和机械耦合到可控半导体元件。多个键合线被布置为在第一水平方向上彼此平行。有源区在第一水平方向上具有第一长度,并且在垂直于第一水平方向的第二水平方向上具有第一宽度。第一数量的键合连接中的每个被布置为在垂直于第一水平方向和第二水平方向的垂直方向上处于有源区上方。多个键合线中的每个的第一键合连接上被布置为在第一水平方向与有源区的第一边缘相距第一距离,其中,第一距离小于第一长度除以键合连接的第一数量的两倍,并且其中,多个键合线中的每个的第一键合连接是被布置为最靠近第一边缘的键合连接,并且多个键合线中的每个的第二键合连接被布置为在第一水平方向上与有源区的第二边缘相距第二距离,其中,第二边缘被布置为与第一边缘相对,并且其中,第二距离小于第一长度除以键合连接的第一数量的两倍,并且其中,多个键合线中的每个的第二键合连接是被布置为最靠近第二边缘的键合连接。
参考以下附图和描述可以更好地理解本发明。附图中的部件不必成比例,而是将重点放在说明本发明的原理上。此外,在附图中,贯穿不同的视图,相似的附图标记指示对应的部分。
附图说明
图1是常规功率半导体模块装置的截面图。
图2是半导体装置的截面图。
图3是半导体装置的俯视图。
图4是根据一个示例的半导体装置的俯视图。
图5是根据另一个示例的半导体装置的俯视图。
图6是根据一个示例的半导体装置的截面图。
图7是根据另一个示例的半导体装置的截面图。
具体实施方式
在下面的具体实施方式中,参考了附图。附图示出了可以实施本发明的具体示例。应当理解的是,除非另外特别指出,否则关于各种示例描述的特征和原理可以彼此组合。在说明书以及权利要求中,某些元件被指定为“第一元件”、“第二元件”、“第三元件”等不被理解为列举。相反,这样的指定仅用于称呼不同的“元件”。即,例如,“第三元件”的存在不需要“第一元件”和“第二元件”的存在。电线和电连接可以包括金属和/或半导体材料,并且可以是永久导电的(即,不可开关的)。如本文所述的半导体主体或可控半导体元件可以由(掺杂的)半导体材料制成,并且可以是半导体芯片或被包括在半导体芯片中。半导体主体或可控半导体元件具有电连接焊盘并且包括电极。
参考图1,示意性地示出了功率半导体模块装置的截面图。功率半导体模块装置包括半导体衬底10。半导体衬底10包括电介质绝缘层11、附接到电介质绝缘层11的第一(结构化的)金属化层111、和附接到电介质绝缘层11的第二(结构化的)金属化层112。电介质绝缘层11设置在第一和第二金属化层111、112之间。然而,半导体衬底10也可以仅包括第一金属化层111,而省略第二金属化层112。
第一和第二金属化层111、112中的每个可以由以下材料中的一个组成或包括以下材料中的一个:铜;铜合金;铝;铝合金;或在功率半导体模块装置的操作期间保持固态的任何其他金属或合金。半导体衬底10可以是陶瓷衬底,即,其中电介质绝缘层11是陶瓷(例如,薄陶瓷层)的衬底。陶瓷可以由以下材料中的一个组成或包括以下材料中的一个:氧化铝;氮化铝;氧化锆;氮化硅;氮化硼;或任何其他电介质陶瓷。例如,电介质绝缘层11可以由以下材料中的一个组成或包括以下材料中的一个:Al2O3、AlN、SiC、BeO或Si3N4。例如,衬底10可以是例如直接铜键合(DCB)衬底、直接铝键合(DAB)衬底、或活性金属钎焊(AMB)衬底。此外,衬底10可以是绝缘金属衬底(IMS)。例如,绝缘金属衬底通常包括电介质绝缘层11,电介质绝缘层11包括(填充)材料,例如,环氧树脂或聚酰亚胺。例如,电介质绝缘层11的材料可以填充有陶瓷颗粒。这样的颗粒可以包括例如Si2O、Al2O3、AlN、或BN,并且可以具有在约1μm和约50μm之间的直径。衬底10也可以是具有非陶瓷电介质绝缘层11的常规印刷电路板(PCB)。例如,非陶瓷电介质绝缘层11可以由固化树脂组成或包括固化树脂。
半导体衬底10布置在壳体5中。在图1中所示的装置中,半导体衬底10形成壳体5的接地表面,而壳体5本身仅包括侧壁。然而,这仅是示例。壳体5还可以包括接地表面和/或顶盖或盖,并且半导体衬底10布置在壳体5内部。
一个或多个可控半导体元件(半导体主体)20可以布置在半导体衬底10上。布置在至少一个半导体衬底10上的可控半导体元件20中的每个可以包括IGBT(绝缘栅双极型晶体管)、MOSFET(金属氧化物半导体场效应晶体管)、JFET(结型场效应晶体管)、HEMT(高电子迁移率晶体管)、和/或任何其他合适的半导体元件。一个或多个可控半导体元件20可以在半导体衬底10上形成半导体装置。在图1中,仅示例性地示出了两个可控半导体元件20。
图1中的半导体衬底10的第二金属化层112是连续层。在图1中所示的装置中,第一金属化层111是结构化层。“结构化层”是指第一金属化层111不是连续层,而在层的不同区段之间包括凹陷。在图1中示意性地示出了这样的凹陷。在该装置中的第一金属化层111包括三个不同的区段。不同的可控半导体元件20可以安装在第一金属化层111的相同区段上或安装到第一金属化层111的不同区段。第一金属化层的不同区段可以不具有电连接,或者可以使用第一电连接3(例如,键合线或键合带)电连接到一个或多个其他区段。仅举几个例子,第一电连接3也可以包括连接板或导电轨。一个或多个可控半导体元件20可以通过导电连接层30电连接和机械连接到半导体衬底10。例如,这样的导电连接层30可以是焊料层、导电粘合剂层、或烧结的金属粉末(例如,烧结的银粉末)层。
图1中所示的功率半导体模块装置还包括端子元件4。端子元件4电连接到第一金属化层111,并在半导体衬底10和壳体5的外部之间提供电连接。端子元件4可以用第一端部电连接到第一金属化层111,而端子元件4的第二端部突出到壳体5之外。可以在其第二端部处从外部电接触端子元件4。
例如,端子元件4的第二端部可以机械连接和电连接到电子板7,例如具有电介质绝缘层的印刷电路板(PCB)。这样的电子板7可以形成壳体的顶盖并且可以包括通孔。端子元件4可以插入到电子板7的通孔中。
壳体5可以至少部分地填充有密封树脂8。例如,密封树脂8可以包括(填充的)环氧树脂、硅凝胶或其他树脂材料。密封树脂8被配置为密封功率半导体模块的部件以提供对器件的绝缘和保护,所述部件例如半导体衬底10,尤其是由第一金属化层111、可控半导体元件20、第一电连接3和端子元件4形成的金属图案。例如,密封树脂8可以保护部件免受某些环境状况和机械损伤。密封树脂8可以至少部分地填充壳体5的内部,从而覆盖布置在半导体衬底10上的部件和电连接。
功率半导体模块还可以包括散热器6。半导体衬底10可以经由连接层(未示出)连接到散热器6。例如,这样的连接层可以是焊料层、粘合剂层、或烧结的金属粉末(例如,烧结的银粉末)层。
图1示意性地示出了没有基板的功率半导体装置。然而,半导体衬底10也可以安装在基板上。例如,这样的基板可以布置在散热器6上,使得该基板布置在散热器6与半导体衬底10之间。在一些功率半导体模块装置中,在单个基板上布置多于一个的半导体衬底。然后,例如,基板(而不是半导体衬底10)可以形成壳体5的接地表面。可控半导体元件20可以布置在多个半导体衬底10中的一个或多个上。
现在参考图2,更详细地示出了布置在半导体衬底10上的可控半导体元件20。在图2中未明确示出电介质绝缘层11以及第一和第二金属化层111、112。如以上关于图1所描述的,例如,不仅可以通过导电连接层30,而且还可以通过至少一个第一电连接3(例如键合线)将可控半导体元件20电耦合和机械耦合到半导体衬底10。第一电连接3可以用第二端部电耦合和机械耦合到可控半导体元件20的顶侧,并且用第一端部耦合到半导体衬底10(例如,第一金属化层111)。可控半导体元件20的顶侧是可控半导体元件20的背离半导体衬底10的一侧。通常,第一电连接3键合到可控半导体元件20。在许多情况下,在第一电连接3和可控半导体元件20之间形成不止一个键合连接。常常,可以在第一电连接3和可控半导体元件20之间形成两个键合连接32、34。如图2中示意性地示出的,第一电连接3(例如,键合线)可以在第一键合连接32和第二键合连接34之间以弧形或弓形延伸。在第一电连接3和可控半导体元件20之间形成两个键合连接32、34通过使键合线3的自加热最小化增加了半导体装置的可靠性。
更进一步地,通常使用多于一个的第一电连接3来与可控半导体元件20电接触。图3的俯视图中示意性地示出了这样的具有多个键合线3n的冗余设计。图3示意性地示出了可控半导体元件20。多个第一电连接(键合线)3n机械耦合和电耦合到可控半导体元件20的顶侧。在图3中,示出了七个第一电连接31-37。然而,这仅是示例。任何合适的数量n的第一电连接3n可以用于接触可控半导体元件20(例如,n>1,或n>5)。例如,第一电连接3n的数量n可以取决于可控半导体元件20的尺寸、通过第一电连接3n的最大电压、以及成本要求。
在图3的示例中,键合线3n与可控半导体元件20之间的键合连接32、34朝向可控半导体元件20的中心来形成。可控半导体元件20包括有源区200。有源区200可以是在使用可控半导体元件20时可控半导体元件20的承载电流的区。有源区200可以被无源区210(也称为边缘区)围绕。与有源区200不同,在使用可控半导体元件20时,边缘区210不承载任何电流。第一键合连接32和第二键合连接34两者通常在有源区200上方(在垂直方向z上)垂直地形成。垂直方向z是垂直于可控半导体元件20的顶表面的方向。边缘区210在水平平面中围绕有源区200。
多个键合线3n在第一水平方向x上从可控半导体元件20延伸到形成在半导体衬底10上的另外的键合连接(未具体示出),并且多个键合线3n被布置为彼此平行。对于所有键合线3n,两个相邻的键合线3n之间的距离d1可以相等。如上已经提及到的,第一键合连接32和第二键合连接34常常朝向可控半导体元件20的中心,并且特别是朝向有源区200的中心来形成。有源区200在第一水平方向x上可以具有长度X,并且在垂直于第一水平方向x和垂直方向z的第二水平方向y上具有宽度Y。就距离d1而言,可以适用以下内容:d1=Y/n,其中,n是键合线3的总数量。有源区200的第一边缘和第一键合连接32之间的距离d32可以至少为X/4(d32≥X/4)。这改善了可控半导体元件20内的电分布。这同样适用于第二键合连接34与有源区200的第二边缘之间的距离d34,第二边缘与第一边缘相对。类似地,最外面的键合线(在图3的示例中为31和37)可以被布置为分别与有源区200的对应的第三和第四边缘相距距离d31和d37。如果d1=Y/n,则d31=d37=Y/(2*n)。
现在参考图4,示意性地示出了根据一个示例的半导体装置。在该示例中,与以上关于图3已经描述的内容相反,第一键合连接32和第二键合连接34更靠近有源区200的相应边缘移动。即,该示例中的第一键合连接32被布置为与有源区200的第一边缘相距距离d32<X/4。第二键合连接34被布置为与有源区200的第二边缘相距距离d34<X/4,其中,第二边缘被布置为与第一边缘相对。使键合连接32、34朝向有源区200的边缘移动,从而增加了第一键合连接32和第二键合连接34之间的距离,在一定程度上使可控半导体元件20内的电分布变差。然而,键合连接32、34的可靠性显著增加。因此,即使电分布稍微变差,键合连接32、34的寿命并且因此整个半导体装置的寿命也被增加。
在图4的示例性半导体装置中,每个键合线3n两次地机械耦合和电耦合到可控半导体元件20。即,每个键合线3n经由第一键合连接32和第二键合连接34机械耦合和电耦合到可控半导体元件20。然而,这仅是示例。对于多个键合线3n中的每个也可以形成多于两个的键合连接。例如,可以在第一键合连接32和第二键合连接34之间形成第三键合连接。也可以在第一键合连接32和第二键合连接34之间形成另外的键合连接。这样的另外的键合连接在附图中未具体示出。然而,大部分应力和张力发生在最外面的键合连接中,即在第一键合连接32和第二键合连接34中,第一键合连接32是最靠近有源区200的第一边缘的键合连接,并且第二键合连接34是最靠近有源区的第二边缘的键合连接。第一键合连接32与第一边缘之间的距离d32以及第二键合连接34与第二边缘之间的距离d34取决于形成用于每个个体的键合线3n的键合连接的总数量。
第一键合连接32(最靠近第一边缘的键合连接)与第一边缘之间的距离d32可以被定义为d32<X/(2*m),其中,X是有源区200的在第一水平方向x上的长度,并且m是用于每个键合线3n的键合连接的数量。即,如果每个键合线3n通过两个键合连接32、34机械耦合和电耦合到可控半导体元件20,如图4中所示,则m=2,并且距离d32的结果为d32<X/(2*2)=X/4。这同样适用于第二键合连接34(最靠近第二边缘的键合连接)与第二边缘之间的距离d34,距离d34可以被定义为d34<X/(2*m)。如果m=2,则d34<X/(2*m)=X/4。
如果每个键合线3n多于两次地电耦合或机械耦合到可控半导体元件20,则最外面的键合连接32、34之间的距离甚至可以更小。例如,如果m=3,则d32<X/(2*3)=X/6,并且d34<X/(2*3)=X/6。当m≥2时,这同样适用于键合连接的任何其他数量m。在第一键合连接32和第二键合连接34之间形成的任何附加的键合连接通常不太容易受到应力和张力。因此,将这种附加的键合连接布置为更靠近有源区的中心是可接受的。通常,附加的键合连接可以布置在第一键合连接32和第二键合连接34之间的任何位置。
在图4中所示的示例中,个体的键合线3n在第二水平方向y上的分布可以与上面关于图3所述的布置中的相同。然而,为了进一步增加键合连接32、34的鲁棒性和半导体装置的寿命,键合线3n也可以进一步被布置为更靠近第三和第四边缘,如图5的示例中示意性示出的。即,最外面的键合线(在图5的示例中为31和36)可以分别被布置为与第三边缘和第四边缘相距距离d31和d36,其中,d31<Y/(2*n)且d36<Y/(2*n),并且其中,第四边缘被布置为与第三边缘相对,并且第三和第四边缘被布置为垂直于第一和第二边缘。即,对于总数量n为七的键合线3n,d31<Y/(2*7)=Y/14且d36<Y/(2*7)=Y/14。通常,键合线3n的任何数量n是可能的,其中n>1。
键合线3n的数量n可以保持与图4的示例相同。然而,如图5的示例中所示,键合线3n的数量n也可能减少。键合线3n可以被布置为第一组3A和第二组3B。同一组3A、3B内的两个相邻的键合线3之间的距离d1可以相等。键合线的第一组3A与键合线的第二组3B之间的距离d2可以大于同一组内的两个相邻的键合线3之间的距离d1。以此方式,在可控半导体元件20的有源区200的中心中形成尽可能少的键合连接32、34。当键合线3n的总数量减少时,这导致总电阻的增加。因此,需要做出折衷以受益于足够低的电阻、和适当的电分布两者、以及键合线3n和可控半导体元件20之间的连接的足够的可靠性,从而导致半导体装置的增加的寿命。
每个键合线的第一端部321可以电耦合和机械耦合到其上安装有可控半导体元件20的半导体衬底10。第一端部321可以从每个键合线3n的第一键合连接32朝向半导体衬底10延伸。以这种方式,例如,可控半导体元件20的顶侧(例如,可控半导体元件20的第一接触端子或电极)可以耦合到第一电势。键合线3n中的每个的第二端部341可以终止于可控半导体元件20。即,第二键合连接34可以形成相应的键合线3n的第二端部(参见图2)。然而,根据另一个示例,每个键合线3n的第二端部341还可以从相应的第二键合连接34进一步延伸并且不机械耦合或电耦合到半导体装置的任何其他部件。这在图6中示意性地示出。在该示例中,第二端部341从第二键合连接34向上延伸并且终止在半空中。例如,第二端部341可以具有至少1mm、至少3mm、或至少5mm的长度l341。延长的第二端部341有助于键合线3的冷却。
根据另一个示例,如图7中示意性示出的,第二端部341也可以进一步朝向半导体衬底10延伸,并且可以机械耦合和电耦合到半导体衬底10。即,第二端部341的长度l341可以更进一步延伸。这还可以增加冷却效果并减少键合线3的温度。例如,第二端部341可以机械耦合和电耦合到第一金属化层111的与第一端部321不同的区段。以这种方式,第二端部341可以耦合到与第一端部321不同的电势。根据一个示例,键合线3n的第二端部341耦合到第一金属化层111的完全没有耦合到任何电势的区段。也就是说,例如,第一金属化层111的区段可以不通过任何其他部件或端子接触。因此,键合线3n的第二端部341与半导体衬底10之间的附加键合连接具有冷却键合线3n的唯一功能。第二端部341不用于电接触可控半导体元件20。仅通过键合线3n的第一端部321提供电接触。
如关于图6和图7所描述的第二端部341的布置可以与如以上关于图4和图5所描述的第一和第二键合连接32、34的布置组合。

Claims (13)

1.一种半导体装置,包括:
可控半导体元件(20),所述可控半导体元件(20)包括有源区(200);以及
多个(n)键合线(3n),所述多个(n)键合线(3n)被布置为在第一水平方向(x)上彼此平行;其中:
所述有源区(200)在所述第一水平方向(x)上具有第一长度(X),并且在垂直于所述第一水平方向(x)的第二水平方向(y)上具有第一宽度(Y),
所述多个键合线(3n)中的每个通过第一数量(m)的键合连接电耦合和机械耦合到所述可控半导体元件(20),其中,所述第一数量(m)的键合连接中的每个被布置为在垂直于所述第一水平方向(x)和所述第二水平方向(y)的垂直方向(z)上处于所述有源区(200)上方,
所述多个键合线(3n)中的每个的第一键合连接(32)被布置为在所述第一水平方向(x)上与所述有源区(200)的第一边缘相距第一距离(d32),其中,所述第一距离(d32)小于所述第一长度(X)除以键合连接的所述第一数量(m)的两倍,并且其中,所述多个键合线(3n)中的每个的所述第一键合连接(32)是被布置为最靠近所述第一边缘的键合连接;并且
所述多个键合线(3n)中的每个的第二键合连接(34)被布置为在所述第一水平方向(x)上与所述有源区(200)的第二边缘相距第二距离(d34),其中,所述第二边缘被布置为与所述第一边缘相对,并且其中,所述第二距离(d34)小于所述第一长度(X)除以键合连接的所述第一数量(m)的两倍,并且其中,所述多个键合线(3n)中的每个的所述第二键合连接(34)是被布置为最靠近所述第二边缘的键合连接。
2.根据权利要求1所述的半导体装置,其中:
所述多个键合线(3n)中的第一键合线(31)被布置为最靠近所述有源区(200)的垂直于所述第一边缘和所述第二边缘的第三边缘,并且其中,所述第一键合线(31)和所述第三边缘之间的距离(d31)小于所述第一宽度(Y)除以键合线(3n)的总数量(n)的两倍;并且
所述多个键合线(3n)中的第二键合线(37)被布置为最靠近所述有源区(200)的与所述第三边缘相对的第四边缘,并且其中,所述第二键合线(37)和所述第四边缘之间的距离(d37)小于所述第一宽度(Y)除以键合线(3n)的所述总数量(n)的两倍。
3.根据权利要求1或2所述的半导体装置,其中,对于所述多个键合线(3n),两个相邻的键合线(3n)之间的距离(d1)相等。
4.根据权利要求1或2所述的半导体装置,其中:
所述多个键合线(3n)被布置为第一组(3A)和第二组(3B);
所述第一组(3A)和所述第二组(3B)中的每个内的所述键合线(3n)彼此等间隔;并且
键合线的所述第一组(3A)和键合线的所述第二组(3B)之间的距离(d2)大于每个组(3A、3B)的个体的键合线(3n)之间的距离(d1)。
5.根据权利要求1至4中任一项所述的半导体装置,其中,所述多个键合线(3n)中的每个的第一端部(321)从所述相应的第一键合连接(32)延伸,并且机械耦合和电耦合到半导体衬底(10)。
6.根据权利要求5所述的半导体装置,其中,所述多个键合线(3n)中的每个的第二端部(341)从所述相应的第二键合连接(34)延伸,并且不机械耦合或电耦合到任何其他部件。
7.根据权利要求5所述的半导体装置,其中,所述多个键合线(3n)中的每个的第二端部(341)从所述相应的第二键合连接(34)延伸,并且机械耦合和电耦合到所述半导体衬底(10),其中,所述多个键合线(3n)中的每个的所述第二端部(341)不用于电接触所述可控半导体元件(20),并且电接触部仅由所述多个键合线(3n)的所述第一端部(321)提供。
8.根据权利要求7所述的半导体装置,其中:
所述半导体衬底(10)包括电介质绝缘层(11)和附接到所述电介质绝缘层(11)的第一金属化层(111);
所述第一金属化层(111)是包括至少两个不同区段的结构化层,其中,在所述不同区段之间形成凹陷;
所述可控半导体元件(20)安装在所述第一金属化层(111)上;
每个键合线(3n)的所述第一端部(321)机械耦合和电耦合到所述第一金属化层(111)的第一区段;并且
每个键合线(3n)的所述第二端部(341)机械耦合和电耦合到所述第一金属化层(111)的不同于所述第一区段的第二区段。
9.根据权利要求7或8所述的半导体装置,其中,所述多个键合线(3n)中的每个的所述第一端部(321)电耦合到与所述多个键合线(3n)中的每个的所述第二端部(341)不同的电势。
10.根据权利要求6至9中任一项所述的半导体装置,其中,所述多个键合线(3n)中的每个的所述第二端部(341)的长度(l341)为至少1mm、至少3mm、或至少5mm。
11.根据前述权利要求中任一项所述的半导体装置,其中,所述可控半导体元件(20)的所述有源区(200)是承载电流的区。
12.根据权利要求11所述的半导体装置,其中,所述可控半导体元件(20)还包括在水平平面中围绕所述有源区(200)的边缘区(210),其中,所述可控半导体元件(20)的所述边缘区(210)是不承载任何电流的区。
13.一种用于制造半导体装置的方法,所述方法包括:将多个(n)键合线(3n)安装在可控半导体元件(20)上,所述可控半导体元件(20)包括有源区(200),其中,将所述多个键合线(3n)安装在所述可控半导体元件(20)上包括:
对于所述多个键合线(3n)中的每个,在所述键合线(3n)和所述可控半导体元件(20)之间形成第一数量(m)的键合连接,从而将所述键合线(3n)电耦合和机械耦合到所述可控半导体元件(20),其中:
所述多个键合线(3n)被布置为在第一水平方向(x)上彼此平行,
所述有源区(200)在所述第一水平方向(x)上具有第一长度(X),并且在垂直于所述第一水平方向(x)的第二水平方向(y)上具有第一宽度(Y),
所述第一数量(m)的键合连接中的每个被布置为在垂直于所述第一水平方向(x)和所述第二水平方向(y)的垂直方向(z)上处于所述有源区(200)上方,
所述多个键合线(3n)中的每个的第一键合连接(32)被布置为在所述第一水平方向(x)上与所述有源区(200)的第一边缘相距第一距离(d32),其中,所述第一距离(d32)小于所述第一长度(X)除以键合连接的所述第一数量(m)的两倍,并且其中,所述多个键合线(3n)中的每个的所述第一键合连接(32)是被布置为最靠近所述第一边缘的键合连接;并且
所述多个键合线(3n)中的每个的第二键合连接(34)被布置为在所述第一水平方向(x)上与所述有源区(200)的第二边缘相距第二距离(d34),其中,所述第二边缘被布置为与所述第一边缘相对,并且其中,所述第二距离(d34)小于所述第一长度(X)除以键合连接的所述第一数量(m)的两倍,并且其中,所述多个键合线(3n)中的每个的所述第二键合连接(34)是被布置为最靠近所述第二边缘的键合连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499450A (zh) * 2008-01-28 2009-08-05 株式会社瑞萨科技 半导体装置及其制造方法
US20110241198A1 (en) * 2010-04-02 2011-10-06 Hitachi, Ltd. Power Semiconductor Module
US20170125322A1 (en) * 2015-10-31 2017-05-04 Ixys Corporation Bridging DMB Structure for Wire Bonding in a Power Semiconductor Module
CN109155301A (zh) * 2018-08-13 2019-01-04 长江存储科技有限责任公司 具有帽盖层的键合触点及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499450A (zh) * 2008-01-28 2009-08-05 株式会社瑞萨科技 半导体装置及其制造方法
US20110241198A1 (en) * 2010-04-02 2011-10-06 Hitachi, Ltd. Power Semiconductor Module
US20170125322A1 (en) * 2015-10-31 2017-05-04 Ixys Corporation Bridging DMB Structure for Wire Bonding in a Power Semiconductor Module
CN109155301A (zh) * 2018-08-13 2019-01-04 长江存储科技有限责任公司 具有帽盖层的键合触点及其形成方法

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