CN112530915A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112530915A
CN112530915A CN202010091929.5A CN202010091929A CN112530915A CN 112530915 A CN112530915 A CN 112530915A CN 202010091929 A CN202010091929 A CN 202010091929A CN 112530915 A CN112530915 A CN 112530915A
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China
Prior art keywords
plate
ceramic
ceramic plate
metal
semiconductor device
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CN202010091929.5A
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English (en)
Inventor
山田武范
井口知洋
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication of CN112530915A publication Critical patent/CN112530915A/zh
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/186Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

实施方式的半导体装置具备:第一半导体芯片;金属板,具有第一面和与第一面对置的第二面,并且具有设置在第一面与第二面之间的第一陶瓷板;以及第一绝缘基板,设置在第一半导体芯片与金属板之间,与第一面对置,在第一半导体芯片与第二面之间不存在第一陶瓷板。

Description

半导体装置
关联申请
本申请享受以日本专利申请2019-169906号(申请日:2019年9月18日)为基础申请的优先权。本申请通过参照该基础申请,包含基础申请的全部内容。
技术领域
实施方式主要涉及半导体装置。
背景技术
功率半导体模块中,例如在金属基底板之上安装功率半导体芯片,在功率半导体芯片之间夹着绝缘基板。功率半导体芯片例如是绝缘栅双极晶体管(Insulated GateBipolar Transistor,IGBT)、金属氧化物半导体场效应晶体管(Metal Oxide FieldEffect Transistor,MOSFET)、或二极管。
功率半导体芯片以高电压而流过高电流,因此发热量大。如果功率半导体模块的散热性低,则由于功率半导体芯片的发热,例如产生功率半导体模块的可靠性不良。可靠性不良例如是焊丝的断开不良。因此,功率半导体模块中,要求提高散热性。
发明内容
实施方式提供能够提高散热性的半导体装置。
实施方式的半导体装置具备:第一半导体芯片;金属板,具有第一面和与上述第一面对置的第二面,并且具有设置在上述第一面与上述第二面之间的第一陶瓷板;以及第一绝缘基板,设置在上述第一半导体芯片与上述金属板之间,与上述第一面对置,在上述第一半导体芯片与上述第二面之间不存在上述第一陶瓷板。
附图说明
图1A~图1C是第一实施方式的半导体装置的示意图。
图2A~图2C是第一实施方式的金属板的示意图。
图3A~图3C是比较例的半导体装置的示意图。
图4A~图4C是比较例的半导体装置的问题点的说明图。
图5A~图5C是第二实施方式的金属板的示意图。
图6A~图6C是第二实施方式的变形例的金属板的示意图。
图7A~图7C是第三实施方式的金属板的示意图。
图8A~图8C是第四实施方式的金属板的示意图。
图9A~图9C是第五实施方式的金属板的示意图。
图10A~图10C是第六实施方式的金属板的示意图。
图11A~图11C是第七实施方式的金属板的示意图。
具体实施方式
本说明书中,有对于相同或类似的部件附加相同的附图标记并省略重复说明的情况。
本说明书中,为了表示部件等的位置关系,有将附图的上方向记述为“上”、将附图的下方向记述为“下”的情况。本说明书中,“上”、“下”的概念并不一定是表示与重力方向的关系的用语。
(第一实施方式)
第一实施方式的半导体装置具备:第一半导体芯片;金属板,具有第一面和与第一面对置的第二面,具有设置在第一面与第二面之间的第一陶瓷板;以及第一绝缘基板,设置在第一半导体芯片与金属板之间,与第一面对置,在第一半导体芯片与第二面之间不存在第一陶瓷板。
图1A~图1C是第一实施方式的半导体装置的示意图。图1A是第一实施方式的半导体装置的俯视图。图1B是第一实施方式的半导体装置的截面图。图1B是图1A的AA’截面。图1C是第一实施方式的半导体装置的截面图。图1C是图1A的BB’截面。另外,图1A中省略了盖的图示。
第一实施方式的半导体装置是具备MOSFET的功率半导体模块100。MOSFET是半导体芯片的一例。
第一实施方式的功率半导体模块100具备第一MOSFET10a(第一半导体芯片)、第二MOSFET10b(第二半导体芯片)、第三MOSFET10c、第四MOSFET10d、第五MOSFET10e(第三半导体芯片)、第六MOSFET10f、第七MOSFET10g、第八MOSFET10h、金属基底板14(金属板)、第一绝缘电路基板16(第一绝缘基板)、第二绝缘电路基板18(第二绝缘基板)、第一接合层20、第二接合层22、焊丝24、树脂壳体26、盖28、第一电力端子30、第二电力端子32、硅凝胶34。
金属基底板14具有第一陶瓷板14a。金属基底板14具有螺纹孔15。金属基底板14具有第一面P1和第二面P2。
第一绝缘电路基板16具有第一下部金属层16a、第一上部金属层16b、第一陶瓷层16c(陶瓷层)。第二绝缘电路基板18具有第二下部金属层18a、第二上部金属层18b、第二陶瓷层18c。
第一MOSFET10a(第一半导体芯片)、第二MOSFET10b(第二半导体芯片)、第三MOSFET10c、第四MOSFET10d设置在第一绝缘电路基板16之上。
第五MOSFET10e(第三半导体芯片)、第六MOSFET10f、第七MOSFET10g、第八MOSFET10h设置在第二绝缘电路基板18之上。
第一MOSFET10a~第八MOSFET10h是高耐压的功率MOSFET。第一MOSFET10a~第八MOSFET10h例如是使用了硅或碳化硅的纵型MOSFET。
第一MOSFET10a~第四MOSFET10d通过第二接合层22固定于第一绝缘电路基板16。第五MOSFET10e~第八MOSFET10h通过第二接合层22固定于第二绝缘电路基板18。
第二接合层22例如是焊料。第二接合层22例如是银浆。
金属基底板14具有第一面P1和第二面P2。第二面P2与第一面P1对置。第一面P1是金属基底板14的上表面,第二面P2是金属基底板14的下表面。
金属基底板14是金属。金属基底板14例如是铝。金属基底板14例如也可以是纯铜或铜合金。
金属基底板14具有提升功率半导体模块100的机械强度的功能。此外,金属基底板14具有使在第一MOSFET10a~第八MOSFET10h的动作时产生的热传导至功率半导体模块100外的功能。
例如,在将功率半导体模块100安装到产品时,在金属基底板14的下表面连接未图示的散热片等散热部件。例如,使用螺纹孔15将功率半导体模块100的四个角和散热部件进行螺钉固定,由此金属基底板14与散热部件被固定。
第一绝缘电路基板16设置在第一MOSFET10a~第四MOSFET10d与金属基底板14之间。第一绝缘电路基板16与金属基底板14的第一面P1对置。
第一绝缘电路基板16具有确保第一MOSFET10a~第四MOSFET10d与金属基底板14之间的电绝缘的功能。
第一绝缘电路基板16具有第一下部金属层16a、第一上部金属层16b、第一陶瓷层16c(陶瓷层)。第一陶瓷层16c被夹在第一下部金属层16a与第一上部金属层16b之间。
第一下部金属层16a、以及第一上部金属层16b例如包含铜。第一下部金属层16a、以及第一上部金属层16b例如是纯铜。
第一陶瓷层16c是陶瓷。第一陶瓷层16c例如是氮化铝、氮化硅或氧化铝。
第二绝缘电路基板18设置在第五MOSFET10e~第八MOSFET10h与金属基底板14之间。第二绝缘电路基板18与金属基底板14的第一面P1对置。
第二绝缘电路基板18具有确保第五MOSFET10e~第八MOSFET10h与金属基底板14之间的电绝缘的功能。
第二绝缘电路基板18具有第二下部金属层18a、第二上部金属层18b、第二陶瓷层18c(陶瓷层)。第二陶瓷层18c夹在第二下部金属层18a与第二上部金属层18b之间。
第二下部金属层18a、以及第二上部金属层18b例如包含铜。第二下部金属层18a、以及第二上部金属层18b例如是纯铜。
第二陶瓷层18c是陶瓷。第二陶瓷层18c例如是氮化铝、氮化硅或氧化铝。
第一绝缘电路基板16以及第二绝缘电路基板18使用第一接合层20而被固定于金属基底板14。第一接合层20例如是焊料。第一接合层20例如是银浆。
树脂壳体26包围第一绝缘电路基板16以及第二绝缘电路基板18的周围而设置。在树脂壳体26之上设有树脂的盖28。在盖28与金属基底板14之间夹着第一绝缘电路基板16以及第二绝缘电路基板18。
此外,在功率半导体模块100的内部,作为封固材料而填充有硅凝胶34。树脂壳体26、金属基底板14、盖28以及硅凝胶34具有对功率半导体模块100内的部件进行保护或绝缘的功能。
在树脂壳体26的上部,设有第一电力端子30、以及第二电力端子32。在树脂壳体26的上部,例如设有未图示的AC输出端子、以及栅极端子。通过第一电力端子30以及第二电力端子32,进行功率半导体模块100与外部的电连接。
焊丝24例如将第一电力端子30、第一MOSFET10a~第八MOSFET10h、以及第二电力端子32电连接。焊丝24例如是铝丝。
图2A~图2C是第一实施方式的金属板的示意图。图2A是金属板的俯视图。图2B是金属板的截面图。图2B是图2A的CC’截面。图2C是金属板的截面图。图2C是图2A的DD’截面。
金属基底板14具有第一陶瓷板14a以及第二陶瓷板14b。第一陶瓷板14a以及第二陶瓷板14b设置在第一面P1与第二面P2之间。第一陶瓷板14a以及第二陶瓷板14b与第一面P1以及第二面P2分离。
第一陶瓷板14a以及第二陶瓷板14b的至少一部分被埋入金属基底板14。例如,第一陶瓷板14a以及第二陶瓷板14b的至少其余一部分从金属基底板14的侧面露出。第一陶瓷板14a以及第二陶瓷板14b例如使用金属的熔融法在金属基底板14的形成时埋入于内部。
图2A中,用实线显示位于金属基底板14的内部的第一陶瓷板14a以及第二陶瓷板14b的轮郭。图2A中关于第一MOSFET10a~第八MOSFET10h的图案,将能够朝向第一面P1的法线方向投影到金属基底板14的图案用虚线表示。
第一陶瓷板14a与第二陶瓷板14b相分离。
在第一MOSFET10a与第二面P2之间不存在第一陶瓷板14a。在第二MOSFET10b与第二面P2之间不存在第一陶瓷板14a。同样,在第三MOSFET10c~第八MOSFET10h与第二面P2之间不存在第一陶瓷板14a。在第一MOSFET10a~第八MOSFET10h中任何一个的第一面P1的法线方向上都没有配置第一陶瓷板14a。
在第一MOSFET10a与第二面P2之间不存在第二陶瓷板14b。在第二MOSFET10b与第二面P2之间不存在第二陶瓷板14b。同样,在第三MOSFET10c~第八MOSFET10h与第二面P2之间不存在第二陶瓷板14b。在第一MOSFET10a~第八MOSFET10h中任何一个的第一面P1的法线方向上都没有配置第二陶瓷板14b。
在第一MOSFET10a~第八MOSFET10h与第二面P2之间的金属基底板14的内部,不存在第一陶瓷板14a以及第二陶瓷板14b。在第一MOSFET10a~第八MOSFET10h的正下方的区域,不存在第一陶瓷板14a以及第二陶瓷板14b。
第二面P2与第一陶瓷板14a之间的第一距离(图2C中的d1)和第二面P2与第二陶瓷板14b之间的第二距离(图2C中的d2)相等。第一陶瓷板14a以及第二陶瓷板14b在金属基底板14的内部位于与第一面P1以及第二面P2平行的同一面内。
第一陶瓷板14a以及第二陶瓷板14b是陶瓷。第一陶瓷板14a以及第二陶瓷板14b例如是氮化铝、氮化硅或氧化铝。第一陶瓷板14a以及第二陶瓷板14b例如是与第一陶瓷层16c以及第二陶瓷层18c相同的材料。
接着,对第一实施方式的半导体装置的作用以及效果进行说明。
图3A~图3C是比较例的半导体装置的示意图。图3A是比较例的半导体装置的俯视图。图3B是比较例的半导体装置的截面图。图3B是图3A的AA’截面。图3C是比较例的半导体装置的截面图。图3C是图3A的BB’截面。另外,图3A中省略了盖的图示。
比较例的半导体装置是具备MOSFET的功率半导体模块900。比较例的功率半导体模块900仅在金属基底板14不具有第一陶瓷板14a以及第二陶瓷板14b这一点上与第一实施方式的功率半导体模块100不同。
图4A~图4C是比较例的半导体装置的问题点的说明图。图4A~图4C图示了功率半导体模块900、散热部件、以及散热膏。
在将功率半导体模块900安装到产品时,在金属基底板14的背面连接散热片等散热部件40。例如,通过将功率半导体模块900的四方和散热部件40进行螺钉固定而推压金属基底板14,从而将金属基底板14与散热部件40密接而固定。
在金属基底板14与散热部件40之间,为了减小接触面的热阻而夹着散热膏42。散热膏42由于热传导度高,所以接触面的热阻下降,热从金属基底板14向散热部件40高效地传递。
图4A表示金属基底板14与散热部件40被理想地固定的状态。金属基底板14的下表面(第二面P2)平坦,金属基底板14的下表面与散热部件40之间的散热膏42的厚度均匀。
图4B表示比较例的功率半导体模块900中实际可能产生的状态。在制造功率半导体模块900时,第一绝缘电路基板16以及第二绝缘电路基板18例如利用焊接而被固定于金属基底板14。
例如,第一绝缘电路基板16与金属基底板14的线膨胀系数不同。因此,通过在金属基底板14上焊接第一绝缘电路基板16时被施加的热处理,如图4B所示在金属基底板14的下表面产生凹凸。因而,金属基底板14的下表面与散热部件40之间的散热膏42的厚度变得不均匀。
图4C表示使比较例的功率半导体模块900的动作持续的状态。如果使功率半导体模块900的动作持续,则通过MOSFET的发热,金属基底板14反复伸缩。因此,金属基底板14的下表面与散热部件40之间的间隙的大小变动。结果,产生散热膏42从金属基底板14的下表面与散热部件40之间向外露出的现象,所谓的挤出(pump out)现象。
如果产生挤出现象,则金属基底板14的下表面与散热部件40之间的散热膏42的量减少。因而,产生散热膏42不足的区域,接触面的热阻增大,功率半导体模块900的散热性降低。因此,例如,产生功率半导体模块900的可靠性不良。
为了提高功率半导体模块900的散热性,希望抑制在制造时产生的金属基底板14的下表面的凹凸、以及抑制动作时的金属基底板14的伸缩。
第一实施方式的功率半导体模块100中,金属基底板14在内部具有线膨胀系数小的第一陶瓷板14a以及第二陶瓷板14b。因而,例如,第一绝缘电路基板16与金属基底板14的线膨胀系数的差变小。因而,即使在焊接第一绝缘电路基板16时被施加热处理,也可抑制在金属基底板14的下表面产生凹凸。此外,金属基底板14的实际的线膨胀系数变小。因此,功率半导体模块100的动作时的金属基底板14的伸缩得到抑制。因此,不易产生挤出现象。
此外,功率半导体模块100中,在第一MOSFET10a~第八MOSFET10h的正下方的区域,不存在第一陶瓷板14a以及第二陶瓷板14b。因而,在第一MOSFET10a~第八MOSFET10h中产生的热向散热部件40传递的路径上不存在第一陶瓷板14a以及第二陶瓷板14b。因此,由第一陶瓷板14a以及第二陶瓷板14b带来的散热性的降低得到抑制。
第一陶瓷板14a以及第二陶瓷板14b的形状、大小、厚度、配置位置等可根据安装于功率半导体模块100的半导体芯片的位置、数量等来最优化。
从使第一绝缘电路基板16与金属基底板14的线膨胀系数的差变小的观点出发,第一陶瓷板14a以及第二陶瓷板14b优选的是与第一陶瓷层16c以及第二陶瓷层18c相同的材料。例如,第一陶瓷板14a、第二陶瓷板14b、第一陶瓷层16c、以及第二陶瓷层18c优选的是氮化铝。
从使金属基底板14的制造变得容易的观点出发,金属基底板14优选的是铝。
以上,根据第一实施方式,能够实现可提高散热性的半导体装置。
(第二实施方式)
第二实施方式的半导体装置在金属板不具有第二陶瓷板这一点上与第一实施方式的半导体装置不同。以下,关于与第一实施方式重复的内容,省略一部分记述。
图5A~图5C是第二实施方式的金属板的示意图。图5A是金属板的俯视图。图5B是金属板的截面图。图5B是图5A的CC’截面。图5C是金属板的截面图。图5C是图5A的DD’截面。
第二实施方式的金属基底板14具有第一陶瓷板14a。第一陶瓷板14a设置在第一MOSFET10a~第四MOSFET10d与第五MOSFET10e~第八MOSFET10h之间的区域的正下方。
图6A~图6C是第二实施方式的变形例的金属板的示意图。图6A是金属板的俯视图。图6B是金属板的截面图。图6B是图6A的CC’截面。图6C是金属板的截面图。图6C是图6A的DD’截面。
关于第二实施方式的变形例的金属基底板14,第二面P2与第一陶瓷板14a之间的第一距离(图6C中的d1)和第二实施方式的金属基底板14的第二面P2与第一陶瓷板14a之间的第一距离(图5C中的d1)不同。
以上,根据第二实施方式以及变形例,与第一实施方式同样,能够实现可提高散热性的半导体装置。
(第三实施方式)
第三实施方式的半导体装置在金属板还具有第三陶瓷板、第四陶瓷板、以及第五陶瓷板这一点上与第一实施方式的半导体装置不同。以下,关于与第一实施方式重复的内容,省略一部分记述。
图7A~图7C是第三实施方式的金属板的示意图。图7A是金属板的俯视图。图7B是金属板的截面图。图7B是图7A的CC’截面。图7C是金属板的截面图。图7C是图7A的DD’截面。
第三实施方式的金属基底板14具有第一陶瓷板14a、第二陶瓷板14b、第三陶瓷板14c、第四陶瓷板14d以及第五陶瓷板14e。第一陶瓷板14a、第二陶瓷板14b、第三陶瓷板14c、第四陶瓷板14d以及第五陶瓷板14e在金属基底板14的内部、位于与第一面P 1以及第二面P2平行的同一面内。
以上,根据第三实施方式,与第一实施方式同样能够实现可提高散热性的半导体装置。
(第四实施方式)
第四实施方式的半导体装置在第二面与第一陶瓷板之间的第一距离和第二面与第二陶瓷板之间的第二距离不同这一点上,与第三实施方式的半导体装置不同。以下,关于与第一实施方式或第三实施方式重复的内容,省略一部分记述。
图8A~图8C是第四实施方式的金属板的示意图。图8A是金属板的俯视图。图8B是金属板的截面图。图8B是图8A的CC’截面。图8C是金属板的截面图。图8C是图8A的DD’截面。
第四实施方式的金属基底板14具有第一陶瓷板14a、第二陶瓷板14b、第三陶瓷板14c、第四陶瓷板14d以及第五陶瓷板14e。第二面P2与第一陶瓷板14a之间的第一距离(图8C中的d1)不同于第二面P2与第二陶瓷板14b之间的第二距离(图8B中的d2)、第二面P2与第三陶瓷板14c之间的第二距离d2、第二面P2与第四陶瓷板14d之间的第二距离d2、第二面P2与第五陶瓷板14e之间的第二距离d2。
以上,根据第四实施方式,与第一实施方式同样能够实现可提高散热性的半导体装置。
(第五实施方式)
第五实施方式的半导体装置在第一陶瓷板和第二陶瓷板在第一面的法线方向上至少一部分重叠这一点上与第一实施方式的半导体装置不同。以下,关于与第一实施方式重复的内容,省略一部分记述。
图9A~图9C是第五实施方式的金属板的示意图。图9A是金属板的俯视图。图9B是金属板的截面图。图9B是图9A的CC’截面。图9C是金属板的截面图。图9C是图9A的DD’截面。
第五实施方式的金属基底板14具有第一陶瓷板14a、第二陶瓷板14b以及第三陶瓷板14c。第一陶瓷板14a和第二陶瓷板14b的一部分在第一面P1的法线方向上重叠。第一陶瓷板14a和第三陶瓷板14c的一部分在第一面P1的法线方向上重叠。
以上,根据第五实施方式,与第一实施方式同样能够实现可提高散热性的半导体装置。
(第六实施方式)
第六实施方式的半导体装置在金属板具有与第一陶瓷板及第二陶瓷板平行地延伸的第三陶瓷板、第四陶瓷板、第五陶瓷板这一点上与第一实施方式的半导体装置不同。以下,关于与第一实施方式重复的内容,省略一部分记述。
图10A~图10C是第六实施方式的金属板的示意图。图10A是金属板的俯视图。图10B是金属板的截面图。图10B是图10A的CC’截面。图10C是金属板的截面图。图10C是图10A的DD’截面。
第六实施方式的金属基底板14具有第一陶瓷板14a、第二陶瓷板14b、第三陶瓷板14c、第四陶瓷板14d以及第五陶瓷板14e。第一陶瓷板14a、第二陶瓷板14b、第三陶瓷板14c、第四陶瓷板14d以及第五陶瓷板14e平行地延伸。第一陶瓷板14a、第二陶瓷板14b、第三陶瓷板14c、第四陶瓷板14d以及第五陶瓷板14e在金属基底板14的内部位于与第一面P1以及第二面P2平行的同一面内。
以上,根据第六实施方式,与第一实施方式同样能够实现可提高散热性的半导体装置。
(第七实施方式)
第七实施方式的半导体装置在第一陶瓷板位于第二半导体芯片与第二面之间、并且第一陶瓷板位于第三半导体芯片与第二面之间这一点上与第二实施方式的半导体装置不同。以下,关于与第一实施方式或第二实施方式重复的内容,省略一部分记述。
图11A~图11C是第七实施方式的金属板的示意图。图11A是金属板的俯视图。图11B是金属板的截面图。图11B是图11A的CC’截面。图11C是金属板的截面图。图11C是图11A的DD’截面。
第七实施方式的金属基底板14在第一MOSFET10a(第一半导体芯片)以及第三MOSFET10c与第二面P2之间没有配置第一陶瓷板14a。此外,在第六MOSFET10f以及第八MOSFET10h与第二面P2之间没有配置第一陶瓷板14a。
第七实施方式的金属基底板14在第一MOSFET10a(第一半导体芯片)以及第三MOSFET10c的第一面P1的法线方向上没有配置第一陶瓷板14a。此外,在第六MOSFET10f以及第八MOSFET10h的第一面P1的法线方向上没有配置第一陶瓷板14a。
另一方面,第七实施方式的金属基底板14在第二MOSFET10b(第二半导体芯片)以及第四MOSFET10d与第二面P2之间配置有第一陶瓷板14a。此外,在第五MOSFET10e(第三半导体芯片)以及第七MOSFET10g与第二面P2之间配置有第一陶瓷板14a。
第七实施方式的金属基底板14在第二MOSFET10b(第二半导体芯片)以及第四MOSFET10d的第一面P1的法线方向上配置有第一陶瓷板14a。此外,在第五MOSFET10e(第三半导体芯片)以及第七MOSFET10g的第一面P1的法线方向上配置有第一陶瓷板14a。
以上,根据第七实施方式,与第一实施方式同样能够实现可提高散热性的半导体装置。
第一至第七实施方式中,作为半导体芯片以MOSFET为例进行了说明,但半导体芯片也可以是IGBT,也可以是二极管。此外,例如,也可以是MOSFET与二极管的组合,或者IGBT与二极管的组合。
此外,安装于1个绝缘电路基板之上的半导体芯片的数量并不限定于4个,也可以是3个以下,也可以是5个以上。此外,功率半导体模块100的绝缘电路基板的数量也可以是1个,也可以是3个。
第一至第七实施方式中,以使用硅凝胶34作为封固材料的情况为例进行了说明,但也可以代替硅凝胶34而例如使用环氧树脂等其他树脂材料。
说明了本发明的几个实施方式,但这些实施方式是作为例子来提示的,并不是要限定发明的范围。这些新的实施方式能够以其他多种形态实施,在不脱离发明的主旨的范围内能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围及主旨中,并且包含于权利要求书中记载的发明及其均等的范围中。

Claims (10)

1.一种半导体装置,其中,具备:
第一半导体芯片;
金属板,具有第一面和与上述第一面对置的第二面,并且具有设置在上述第一面与上述第二面之间的第一陶瓷板;以及
第一绝缘基板,设置在上述第一半导体芯片与上述金属板之间,与上述第一面对置,
在上述第一半导体芯片与上述第二面之间不存在上述第一陶瓷板。
2.如权利要求1所述的半导体装置,其中,
上述金属板具有设置在上述第一面与上述第二面之间的第二陶瓷板。
3.如权利要求2所述的半导体装置,其中,
上述第二面与上述第一陶瓷板之间的第一距离和上述第二面与上述第二陶瓷板之间的第二距离相同。
4.如权利要求2所述的半导体装置,其中,
上述第二面与上述第一陶瓷板之间的第一距离和上述第二面与上述第二陶瓷板之间的第二距离不同。
5.如权利要求4所述的半导体装置,其中,
上述第一陶瓷板与上述第二陶瓷板在上述第一面的法线方向上至少一部分重叠。
6.如权利要求1所述的半导体装置,其中,
还具备第二半导体芯片,在上述第二半导体芯片与上述金属板之间配置有上述第一绝缘基板;
在上述第二半导体芯片与上述第二面之间不存在上述第一陶瓷板。
7.如权利要求1所述的半导体装置,其中,
还具备:
第三半导体芯片;以及
第二绝缘基板,设置在上述第三半导体芯片与上述金属板之间,与上述第一面对置,
在上述第三半导体芯片与上述第二面之间不存在上述第一陶瓷板。
8.如权利要求1所述的半导体装置,其中,
上述第一绝缘基板具有陶瓷层;
上述第一陶瓷板和上述陶瓷层是同一材料。
9.如权利要求1所述的半导体装置,其中,
上述金属板是铝。
10.如权利要求1所述的半导体装置,其中,
上述第一陶瓷板是氮化铝、氮化硅或氧化铝。
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