IT1400538B1 - Dispositivo elettronico e metodo di collegamento di una piastrina ad un terminale di connessione - Google Patents
Dispositivo elettronico e metodo di collegamento di una piastrina ad un terminale di connessioneInfo
- Publication number
- IT1400538B1 IT1400538B1 ITTO2010A000448A ITTO20100448A IT1400538B1 IT 1400538 B1 IT1400538 B1 IT 1400538B1 IT TO2010A000448 A ITTO2010A000448 A IT TO2010A000448A IT TO20100448 A ITTO20100448 A IT TO20100448A IT 1400538 B1 IT1400538 B1 IT 1400538B1
- Authority
- IT
- Italy
- Prior art keywords
- plate
- electronic device
- connection terminal
- terminal
- connection
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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- H01L2224/37001—Core members of the connector
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- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITTO2010A000448A IT1400538B1 (it) | 2010-05-28 | 2010-05-28 | Dispositivo elettronico e metodo di collegamento di una piastrina ad un terminale di connessione |
US13/117,340 US8513811B2 (en) | 2010-05-28 | 2011-05-27 | Electronic device and method for connecting a die to a connection terminal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITTO2010A000448A IT1400538B1 (it) | 2010-05-28 | 2010-05-28 | Dispositivo elettronico e metodo di collegamento di una piastrina ad un terminale di connessione |
Publications (2)
Publication Number | Publication Date |
---|---|
ITTO20100448A1 ITTO20100448A1 (it) | 2011-11-29 |
IT1400538B1 true IT1400538B1 (it) | 2013-06-11 |
Family
ID=43304161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITTO2010A000448A IT1400538B1 (it) | 2010-05-28 | 2010-05-28 | Dispositivo elettronico e metodo di collegamento di una piastrina ad un terminale di connessione |
Country Status (2)
Country | Link |
---|---|
US (1) | US8513811B2 (it) |
IT (1) | IT1400538B1 (it) |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6528880B1 (en) * | 2001-06-25 | 2003-03-04 | Lovoltech Inc. | Semiconductor package for power JFET having copper plate for source and ribbon contact for gate |
US20040217488A1 (en) * | 2003-05-02 | 2004-11-04 | Luechinger Christoph B. | Ribbon bonding |
DE602004011195T2 (de) * | 2004-05-31 | 2009-01-08 | Stmicroelectronics S.R.L., Agrate Brianza | Vertikal leitender Leistungselektronikvorrichtungs-Baustein sowie entsprechendes Montageverfahren |
JP4526957B2 (ja) * | 2005-01-13 | 2010-08-18 | ルネサスエレクトロニクス株式会社 | 半導体装置、ボンディング方法およびボンディングリボン |
DE102005039165B4 (de) * | 2005-08-17 | 2010-12-02 | Infineon Technologies Ag | Draht- und streifengebondetes Halbleiterleistungsbauteil und Verfahren zu dessen Herstellung |
US7443018B2 (en) * | 2005-11-09 | 2008-10-28 | Stats Chippac Ltd. | Integrated circuit package system including ribbon bond interconnect |
JP2007220704A (ja) * | 2006-02-14 | 2007-08-30 | Mitsubishi Electric Corp | 半導体装置 |
US8237268B2 (en) * | 2007-03-20 | 2012-08-07 | Infineon Technologies Ag | Module comprising a semiconductor chip |
TWI456707B (zh) * | 2008-01-28 | 2014-10-11 | Renesas Electronics Corp | 半導體裝置及其製造方法 |
US8138585B2 (en) * | 2008-05-28 | 2012-03-20 | Fairchild Semiconductor Corporation | Four mosfet full bridge module |
-
2010
- 2010-05-28 IT ITTO2010A000448A patent/IT1400538B1/it active
-
2011
- 2011-05-27 US US13/117,340 patent/US8513811B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20110291286A1 (en) | 2011-12-01 |
ITTO20100448A1 (it) | 2011-11-29 |
US8513811B2 (en) | 2013-08-20 |
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