IT1398937B1 - Metodo per eseguire un testing elettrico di dispositivi elettronici - Google Patents

Metodo per eseguire un testing elettrico di dispositivi elettronici

Info

Publication number
IT1398937B1
IT1398937B1 ITMI2010A000238A ITMI20100238A IT1398937B1 IT 1398937 B1 IT1398937 B1 IT 1398937B1 IT MI2010A000238 A ITMI2010A000238 A IT MI2010A000238A IT MI20100238 A ITMI20100238 A IT MI20100238A IT 1398937 B1 IT1398937 B1 IT 1398937B1
Authority
IT
Italy
Prior art keywords
electronic devices
electrical testing
performing electrical
testing
electronic
Prior art date
Application number
ITMI2010A000238A
Other languages
English (en)
Inventor
Alberto Pagani
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITMI2010A000238A priority Critical patent/IT1398937B1/it
Priority to US13/027,617 priority patent/US8479066B2/en
Publication of ITMI20100238A1 publication Critical patent/ITMI20100238A1/it
Application granted granted Critical
Publication of IT1398937B1 publication Critical patent/IT1398937B1/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/3025—Wireless interface with the DUT
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
ITMI2010A000238A 2010-02-17 2010-02-17 Metodo per eseguire un testing elettrico di dispositivi elettronici IT1398937B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITMI2010A000238A IT1398937B1 (it) 2010-02-17 2010-02-17 Metodo per eseguire un testing elettrico di dispositivi elettronici
US13/027,617 US8479066B2 (en) 2010-02-17 2011-02-15 Process for making an electric testing of electronic devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2010A000238A IT1398937B1 (it) 2010-02-17 2010-02-17 Metodo per eseguire un testing elettrico di dispositivi elettronici

Publications (2)

Publication Number Publication Date
ITMI20100238A1 ITMI20100238A1 (it) 2011-08-18
IT1398937B1 true IT1398937B1 (it) 2013-03-28

Family

ID=42792439

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2010A000238A IT1398937B1 (it) 2010-02-17 2010-02-17 Metodo per eseguire un testing elettrico di dispositivi elettronici

Country Status (2)

Country Link
US (1) US8479066B2 (it)
IT (1) IT1398937B1 (it)

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US8402321B2 (en) * 2010-06-21 2013-03-19 Litepoint Corporation System and method of providing driver software to test controller to facilitate testing by wireless transceiver tester of a device under test
US10082535B2 (en) * 2011-03-21 2018-09-25 Ridgetop Group, Inc. Programmable test structure for characterization of integrated circuit fabrication processes
US9910086B2 (en) 2012-01-17 2018-03-06 Allen Czamara Test IP-based A.T.E. instrument architecture
US9625720B2 (en) 2012-01-24 2017-04-18 Accipiter Radar Technologies Inc. Personal electronic target vision system, device and method
DE102013006011A1 (de) * 2013-04-09 2014-10-09 Airbus Defence and Space GmbH Modulare Testumgebung für eine Mehrzahl von Testobjekten
US9234940B2 (en) * 2014-01-10 2016-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out wafer architecture and test method
US9934179B2 (en) 2015-02-17 2018-04-03 Mediatek Inc. Wafer-level package with at least one input/output port connected to at least one management bus
US10152445B2 (en) * 2015-02-17 2018-12-11 Mediatek Inc. Signal count reduction between semiconductor dies assembled in wafer-level package
JP6491507B2 (ja) * 2015-03-20 2019-03-27 ルネサスエレクトロニクス株式会社 半導体装置、電子装置および半導体装置の自己診断方法
EP3157172B1 (en) * 2015-10-15 2018-11-28 Menta System and method for testing and configuration of an fpga
KR102583174B1 (ko) 2018-06-12 2023-09-26 삼성전자주식회사 테스트 인터페이스 보드, 이를 포함하는 테스트 시스템 및 이의 동작 방법
TWI710778B (zh) 2019-12-04 2020-11-21 瑞軒科技股份有限公司 自動化測試系統及其裝置
TWI748297B (zh) 2019-12-04 2021-12-01 瑞軒科技股份有限公司 自動化測試方法

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US5307290A (en) * 1988-10-18 1994-04-26 Fiat Auto S.P.A. System for the automatic testing, preferably on a bench, of electronic control systems which are intended to be fitted in vehicles
US5295079A (en) * 1991-07-18 1994-03-15 National Semiconductor Corporation Digital testing techniques for very high frequency phase-locked loops
US6988232B2 (en) * 2001-07-05 2006-01-17 Intellitech Corporation Method and apparatus for optimized parallel testing and access of electronic circuits
US7137053B2 (en) 2001-09-04 2006-11-14 Verigg Ipco Bandwidth matching for scan architectures in an integrated circuit
US7265570B2 (en) * 2001-09-28 2007-09-04 Inapac Technology, Inc. Integrated circuit testing module
EP1351066A1 (en) 2002-04-04 2003-10-08 Texas Instruments Incorporated Configurable scan path structure
US7408358B2 (en) * 2003-06-16 2008-08-05 Midtronics, Inc. Electronic battery tester having a user interface to configure a printer
US7512851B2 (en) 2003-08-01 2009-03-31 Syntest Technologies, Inc. Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
US8581610B2 (en) * 2004-04-21 2013-11-12 Charles A Miller Method of designing an application specific probe card test system
US7428678B1 (en) 2004-09-22 2008-09-23 Cypress Semiconductor Corporation Scan testing of integrated circuits with high-speed serial interface
US7412342B2 (en) * 2004-10-28 2008-08-12 Intel Corporation Low cost test for IC's or electrical modules using standard reconfigurable logic devices
US7245134B2 (en) * 2005-01-31 2007-07-17 Formfactor, Inc. Probe card assembly including a programmable device to selectively route signals from channels of a test system controller to probes
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US7343558B2 (en) * 2005-03-31 2008-03-11 Teradyne, Inc. Configurable automatic-test-equipment system
US7673200B2 (en) * 2007-10-10 2010-03-02 Asix Electronics Corporation Reprogrammable built-in-self-test integrated circuit and test method for the same
US8289039B2 (en) * 2009-03-11 2012-10-16 Teradyne, Inc. Pin electronics liquid cooled multi-module for high performance, low cost automated test equipment

Also Published As

Publication number Publication date
US8479066B2 (en) 2013-07-02
ITMI20100238A1 (it) 2011-08-18
US20110202799A1 (en) 2011-08-18

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