CN101356303B - 用反相图案工艺形成凹陷结构的方法 - Google Patents

用反相图案工艺形成凹陷结构的方法 Download PDF

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Publication number
CN101356303B
CN101356303B CN200580016113.XA CN200580016113A CN101356303B CN 101356303 B CN101356303 B CN 101356303B CN 200580016113 A CN200580016113 A CN 200580016113A CN 101356303 B CN101356303 B CN 101356303B
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China
Prior art keywords
layer
multilayer structure
substrate
shape
etching
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Expired - Lifetime
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CN200580016113.XA
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English (en)
Chinese (zh)
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CN101356303A (zh
Inventor
S·V·斯里尼瓦桑
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Canon Nanotechnologies Inc
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Molecular Imprints Inc
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Publication of CN101356303A publication Critical patent/CN101356303A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/0046—Surface micromachining, i.e. structuring layers on the substrate using stamping, e.g. imprinting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
CN200580016113.XA 2004-05-21 2005-05-19 用反相图案工艺形成凹陷结构的方法 Expired - Lifetime CN101356303B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US85087604A 2004-05-21 2004-05-21
US10/850,876 2004-05-21
US10/946,570 US7186656B2 (en) 2004-05-21 2004-09-21 Method of forming a recessed structure employing a reverse tone process
US10/946,570 2004-09-21
PCT/US2005/017756 WO2005114719A2 (en) 2004-05-21 2005-05-19 Method of forming a recessed structure employing a reverse tone process

Publications (2)

Publication Number Publication Date
CN101356303A CN101356303A (zh) 2009-01-28
CN101356303B true CN101356303B (zh) 2012-04-04

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CN200580016113.XA Expired - Lifetime CN101356303B (zh) 2004-05-21 2005-05-19 用反相图案工艺形成凹陷结构的方法

Country Status (7)

Country Link
US (1) US7186656B2 (enExample)
EP (1) EP1761949A4 (enExample)
JP (2) JP5059608B2 (enExample)
KR (1) KR101139302B1 (enExample)
CN (1) CN101356303B (enExample)
TW (1) TWI289326B (enExample)
WO (1) WO2005114719A2 (enExample)

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US7384569B1 (en) * 2004-08-02 2008-06-10 Advanced Micro Devices, Inc. Imprint lithography mask trimming for imprint mask using etch
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US7252777B2 (en) * 2004-09-21 2007-08-07 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US7547504B2 (en) * 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7585424B2 (en) * 2005-01-18 2009-09-08 Hewlett-Packard Development Company, L.P. Pattern reversal process for self aligned imprint lithography and device
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TW200603261A (en) 2006-01-16
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US20050260848A1 (en) 2005-11-24
TWI289326B (en) 2007-11-01
US7186656B2 (en) 2007-03-06
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