CN101335181B - 使用间隔物作为蚀刻掩模制造半导体器件的方法 - Google Patents
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Abstract
本发明公开了一种使用间隔物作为用于形成微细图案的蚀刻掩模的制造半导体器件的工艺。该工艺包括在要被蚀刻的目标层上方形成硬质掩模层。随后在硬质掩模层上方形成牺牲层图案。间隔物形成在牺牲层图案的侧壁上。保护层形成在形成有间隔物的牺牲层图案之间的硬质掩模层的部分上。之后移除牺牲层图案和保护层。使用间隔物作为蚀刻掩模,蚀刻硬质掩模层。蚀刻之后,移除间隔物。最后,使用蚀刻的硬质掩模层作为蚀刻,掩模蚀刻目标层。
Description
技术领域
本发明涉及一种制造半导体器件的方法,且更具体地,涉及一种能容易地形成微细图案的制造半导体器件的方法。
背景技术
随着半导体器件变得高度集成,图案的临界尺寸和距离已被小型化。一般地,在半导体的制造中,进行曝光和蚀刻工艺以形成期望的图案。具体地,光致抗蚀剂材料在图案形成膜上使用光刻工艺形成图案。随后使用光致抗蚀剂材料图案作为蚀刻掩模蚀刻图案形成膜。
因此,光刻技术是形成微细图案的重要因素。常规光刻这样进行:使用KrF或ArF在光致抗蚀剂材料上曝光光刻板(reticle)的图案以及对光刻板的图案显影以形成光致抗蚀剂材料图案。
然而,在高度集成的半导体器件中,台阶高度增加且使用ArF曝光的光致抗蚀剂材料的图案形成方法造成限制。该限制由于短波长的光学效应和使用化学放大光致抗蚀剂材料引起的化学效应而引起。
为了克服该限制,已经使用了在要被蚀刻的目标层上形成氮化物层系列材料或非晶碳且用作蚀刻掩模的方法。前面提到的用作蚀刻掩模的除了光致抗蚀剂材料的硬质材料被称为硬质掩模。
以下,将简要描述根据常规技术使用硬质掩模形成图案的方法。
由氮化物系列材料或非晶碳制成的硬质掩模层形成在图案形成膜上,即,在要被蚀刻的目标层上。由比如SiON的材料制成的抗反射层形成在硬质掩模层上。然后光致抗蚀剂材料被涂覆在抗反射层上且随后该光致抗蚀剂材料涂层被曝光和显影而形成光致抗蚀剂材料图案。
使用光致抗蚀剂材料图案作为蚀刻掩模蚀刻抗反射层和硬质掩模层以形成硬质掩模。然后移除存留的光致抗蚀剂材料图案。存留的SiON抗反射层和光致抗蚀剂材料图案被一起移除。可以省略光致抗蚀剂材料图案的移除。目标层使用硬质掩模作为蚀刻掩模被蚀刻以形成期望的图案。
然而,半导体器件的集成的进展远快于曝光设备的发展。结果,使用当前的曝光设备不可能形成40nm技术或更小的半导体器件所需的微细图案。此外,使用硬质掩模的图案形成方法不能在特征尺寸小于40nm的半导体器件中获得微细尺寸的硬质掩模且引起额外的问题,即图案塌陷。
因此,急切需要使用现有曝光设备形成40nm技术或更小的半导体器件所需的微细图案的方法,以消除在新曝光设备中的进一步投资的需要。
发明内容
本发明的实施例涉及制造半导体器件的方法,该方法能使用现有的曝光设备容易地形成具有小于40nm的特征尺寸的半导体器件所需的微细图案。
在一个实施例中,制造半导体器件的方法包括步骤:在要被蚀刻的目标层上形成硬质掩模层;在硬质掩模层上方形成牺牲层图案;在牺牲层图案的侧壁上形成间隔物;在形成有间隔物的牺牲层图案之间的硬质掩模层的部分上形成保护层;移除牺牲层图案,保留间隔物;移除保护层;使用间隔物作为蚀刻掩模,蚀刻硬质掩模层;移除间隔物;以及使用蚀刻的硬质掩模作为蚀刻掩模,蚀刻目标层。
硬质掩模层是非晶碳层和SiON层或SiN层的叠层。
非晶碳层在500~700℃的温度形成。
SiON层或SiN层在100~400℃的温度形成。
牺牲层是氧化物层。
氧化物层形成为具有0.1~0.5%的TEOS/O2比率。
氧化物层以等离子体增强化学气相沉积(PECVD)工艺形成。
PECVD工艺通过施加300~800W的等离子体功率来实施。
形成保护层的步骤还包括步骤:在硬质掩模层上方形成保护层以覆盖形成有间隔物的牺牲层图案;以及蚀刻保护层以曝光牺牲层图案。
保护层是光敏膜或非晶碳膜。
移除牺牲层的步骤使用湿式化学制剂来实施。
湿式化学制剂是HF∶DI的1∶10~1∶20的混合物。
间隔物是多晶硅层。
多晶硅层以CVD工艺形成。
CVD工艺在300~500℃的温度来实施。
移除保护层的步骤用O2等离子体处理来实施。
附图说明
图1A到图1H是示出根据本发明的实施例制造半导体器件的方法的步骤的截面图。
具体实施方式
本发明的优选实施例涉及半导体封装,其中微细图案使用间隔物作为蚀刻掩模形成在半导体上。根据本发明的实施例,可以仅通过控制间隔物沉积厚度来控制图案的尺寸,而无论曝光设备的分辨率如何。
因此,在本发明的实施例中,可以避免新曝光设备的成本并通过使用现有的曝光设备来降低成本。
可以形成微细图案而不依赖于曝光设备的分辨率,并且因此获得40nm技术或更小的高集成的半导体器件,因为当使用间隔物作为蚀刻掩模时仅通过控制间隔物沉积厚度来控制图案的尺寸。
以下,将参照附图描述根据本发明的实施例的制造半导体器件的方法。
图1A到图1H是示出根据本发明的实施例的制造半导体器件的方法的步骤的截面图。
参照图1A,硬质掩模层108由第一硬质掩模层104和第二硬质掩模层106的叠层构成。硬质掩模层108形成在具有要被蚀刻的目标层102的半导体基板100上方。随后牺牲层110和抗反射层112形成在硬质掩模层108上方。
第一硬质掩模层104在500~700℃的温度由非晶碳层形成。第二硬质掩模层106在100~400℃由SiON层或SiN层形成。牺牲层110是以等离子体增强化学气相沉积(PECVD)工艺形成的氧化物层。进行PECVD工艺,其中使用300~800W的等离子体功率以方便在随后的工艺中用湿式化学制剂移除且TEOS/O2比率低于0.5%,优选0.1~0.5%。抗反射层112由底抗反射涂层(BARC)形成。
参照图1B,在抗反射层112上涂覆、曝光和显影光敏膜以形成光敏膜图案114。牺牲层图案110a通过使用光敏膜图案114作为蚀刻掩模和蚀刻抗反射层112和牺牲层110形成以暴露第二硬质掩模层106。
参照图1C,移除在牺牲层图案110a上方存留的光敏膜图案114和抗反射层112。根据第二硬质掩模层106和牺牲层图案110a的轮廓,在包括牺牲层图案110a的第二硬质掩模层106上沉积间隔物层。然后间隔物层被回蚀以在牺牲层图案110a的侧壁上形成间隔物116。间隔物116是根据在300~500℃的温度的CVD工艺形成的氮化硅层。
参照图1D,保护层118形成在第二硬质掩模层106上方以覆盖形成有间隔物116的牺牲层图案110a。保护层118由光敏膜或非晶碳层形成。保护层118防止在移除牺牲层图案110a的后续工艺中的第二硬质掩模层的损失。保护层118优选地形成为具有一厚度以防止在移除牺牲层图案110a中的第二硬质掩模层106的损失。
参照图1F,牺牲层图案110a通过湿法蚀刻工艺使用湿式化学制剂移除以暴露第二硬质掩模层106。一般用于移除氧化物层的HF和DI的溶液混合物具有增加的HF,其中HF∶DI的比率是1∶10到1∶20,该溶液混合物在湿法蚀刻工艺中用作湿式化学制剂以移除牺牲层图案110a。
参照图1F,布置在第二硬质掩模层106上方的保护层118通过O2等离子体处理移除。使用存留在第二硬质掩模层106上的间隔物116作为蚀刻掩模蚀刻第二硬质掩模层106。
参照图1G,移除间隔物116。随后使用蚀刻的第二硬质掩模层106作为蚀刻掩模,蚀刻第一硬质掩模层104以暴露目标层102。
参照图1H,移除蚀刻的第二硬质掩模层106。使用第一硬质掩模层104作为蚀刻掩模来蚀刻目标层102以形成期望的微细图案102a。
随后进行一系列已知的后续工艺(没有示出)以完成具有微细图案的半导体器件的制造。
从上面的描述可知,在本发明的实施例中,可以使用现有的曝光设备形成微细图案,因为该微细图案使用间隔物作为蚀刻掩模形成。结果,由于降低了成本,本发明是有利的,因为不需要在新曝光设备中投资。
此外,根据本发明的实施例,因为使用间隔物作为蚀刻掩模,所以可以仅通过控制间隔物厚度来形成具有期望尺寸的微细图案。因此,可以稳定地形成微细图案,因为微细图案的形成不依赖于曝光设备的分辨率。
结果,可以制造高度集成的可靠的半导体器件。
虽然为说明性的目的描述了本发明的具体实施例,本领域的技术人员应该理解,各种修改、增添和替换是可能的,只要不偏离如所附的权利要求中公开的本发明的范围和精神。
本申请要求于2007年6月29日提交的韩国专利申请第10-2007-0065489号的优先权,其全部内容通过引用的方式引入于此。
Claims (14)
1.一种制造半导体器件的方法,包括步骤:
在要被蚀刻的目标层上形成硬质掩模层;
在所述硬质掩模层上方形成牺牲层图案;
在所述牺牲层图案的侧壁上形成间隔物;
在形成有所述间隔物的所述牺牲层图案之间的所述硬质掩模层的部分上形成保护层;
移除所述牺牲层图案,选择性地存留所述间隔物,其中所述保护层防止在移除所述牺牲层图案过程中所述硬质掩模层的损失;
移除所述保护层,所述保护层由光敏膜或非晶碳层形成;
使用所述间隔物作为蚀刻掩模,蚀刻所述硬质掩模层;
移除所述间隔物;以及
使用所述蚀刻的硬质掩模层作为蚀刻掩模,蚀刻所述目标层。
2.如权利要求1所述的制造半导体器件的方法,其中所述硬质掩模层由第一硬质掩模层和第二硬质掩模层的叠层组成,且第一硬质掩模层由非晶碳层形成,且第二硬质掩模层由SiON层或SiN层形成。
3.如权利要求2所述的制造半导体器件的方法,其中所述非晶碳层在500~700℃的温度形成。
4.如权利要求2所述的制造半导体器件的方法,其中所述SiON层或SiN层在100~400℃的温度形成。
5.如权利要求1所述的制造半导体器件的方法,其中所述牺牲层是氧化物层。
6.如权利要求5所述的制造半导体器件的方法,其中所述氧化物层形成为具有0.1~0.5%的TEOS/O2比率。
7.如权利要求5所述的制造半导体器件的方法,其中所述氧化物层以等离子体增强化学气相沉积工艺形成。
8.如权利要求7所述的制造半导体器件的方法,其中所述等离子体增强化学气相沉积工艺通过施加300~800W的等离子体功率来实施。
9.如权利要求1所述的制造半导体器件的方法,其中形成所述保护层的步骤还包括:
在所述硬质掩模层上方形成所述保护层以覆盖形成有所述间隔物的所述牺牲层图案;以及
移除所述保护层以暴露所述牺牲层图案。
10.如权利要求1所述的制造半导体器件的方法,其中移除所述牺牲层的步骤使用湿式化学制剂实施。
11.如权利要求1所述的制造半导体器件的方法,其中所述间隔物是多晶硅层。
12.如权利要求1所述的制造半导体器件的方法,其中所述多晶硅层以化学气相沉积工艺形成。
13.如权利要求12所述的制造半导体器件的方法,其中所述化学气相沉积工艺在300~500℃的温度实施。
14.如权利要求1所述的制造半导体器件的方法,其中移除所述保护层的步骤用O2等离子体处理实施。
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KR100983708B1 (ko) * | 2007-12-28 | 2010-09-24 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
KR20100083581A (ko) * | 2009-01-14 | 2010-07-22 | 삼성전자주식회사 | 반도체 소자의 형성방법 |
US8692310B2 (en) | 2009-02-09 | 2014-04-08 | Spansion Llc | Gate fringing effect based channel formation for semiconductor device |
JP2011066164A (ja) * | 2009-09-16 | 2011-03-31 | Tokyo Electron Ltd | マスクパターンの形成方法及び半導体装置の製造方法 |
KR101175247B1 (ko) * | 2010-11-30 | 2012-08-21 | 에스케이하이닉스 주식회사 | 스페이서패터닝을 이용한 반도체장치 제조 방법 |
CN102867735A (zh) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | 一种mom电容制造方法 |
CN103779191B (zh) * | 2012-10-26 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN104078366B (zh) * | 2014-07-16 | 2018-01-26 | 上海集成电路研发中心有限公司 | 双重图形化鳍式晶体管的鳍结构制造方法 |
KR102192350B1 (ko) * | 2014-08-05 | 2020-12-18 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조방법 |
KR102403736B1 (ko) * | 2015-11-02 | 2022-05-30 | 삼성전자주식회사 | 반도체 소자 및 그 반도체 소자의 제조 방법 |
KR102617139B1 (ko) * | 2018-04-09 | 2023-12-26 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
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DE102020202262A1 (de) * | 2020-02-21 | 2021-08-26 | Robert Bosch Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung einer nanoskaligen Kanalstruktur |
US11232952B2 (en) * | 2020-03-05 | 2022-01-25 | Nanya Technology Corporation | Semiconductor device structure with fine patterns and method for forming the same |
CN112017947A (zh) * | 2020-07-17 | 2020-12-01 | 中国科学院微电子研究所 | 一种半导体结构的制造方法 |
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